View MPC5606BK_7693941.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MPC5606BK microcontroller reference manual devices supported: MPC5606BKrm rev. 2 05/2014 MPC5606BK mpc5605bk
this page is intentionally left blank.
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 3 chapter 1 preface 1.1 overview ................................................................................................................... ......................21 1.2 audience ................................................................................................................... .......................21 1.3 guide to this refe rence manua l ............................................................................................. ...........21 1.4 register descripti on conventions ........................................................................................... .........25 1.5 references ................................................................................................................. ......................26 1.6 how to use the MPC5606BK documents .......................................................................................26 1.6.1 the MPC5606BK document set .....................................................................................26 1.6.2 reference manual content ..............................................................................................27 1.7 using the MPC5606BK ........................................................................................................ ..........28 1.7.1 hardware design .......................................................................................................... ...28 1.7.2 input/output pins ........................................................................................................ .....29 1.7.3 software de sign .......................................................................................................... ....29 1.7.4 other featur es ........................................................................................................... ......30 chapter 2 introduction 2.1 the MPC5606BK microcontro ller family ......................................................................................3 1 2.2 MPC5606BK device comparison ................................................................................................ ....31 2.3 device block diagram ....................................................................................................... ...............32 2.4 feature details ............................................................................................................ .....................35 2.4.1 e200z0h core processor ..................................................................................................3 5 2.4.2 crossbar switch (xbar) ................................................................................................35 2.4.3 interrupt controller (intc) ............................................................................................35 2.4.4 system integration unit lite (siul) ..............................................................................36 2.4.5 flash memory ............................................................................................................. ....36 2.4.6 sram ..................................................................................................................... ........38 2.4.7 memory protection unit (mpu) ....................................................................................38 2.4.8 boot assist module (bam) ...........................................................................................38 2.4.9 enhanced modular input out put system (emios) ........................................................39 2.4.10 deserial serial peripheral interface module (dspi) ......................................................40 2.4.11 controller area network module (flexcan) ................................................................40 2.4.12 system clocks and clock generation ...............................................................................41 2.4.13 system time rs ........................................................................................................... ......42 2.4.14 system watchdog timer ..................................................................................................4 3 2.4.15 inter-integrated circ uit (i2c) module ............................................................................43 2.4.16 on-chip voltage regul ator (vreg) ................................................................................43 2.4.17 analog-to-digital c onverter (adc) ..............................................................................44 2.4.18 enhanced direct memory access controller (edma) ...................................................45 2.4.19 cross trigger unit (ctu) ..............................................................................................45 2.4.20 serial communication interf ace module (lin flex) .......................................................46 2.4.21 jtag controller (jtagc) .............................................................................................47 2.5 developer support ......................................................................................................... .................47
MPC5606BK microcontroller reference manual, rev. 2 4 freescale semiconductor chapter 3 memory map chapter 4 signal description 4.1 package pinouts ............................................................................................................ ...................53 4.2 pin muxing ................................................................................................................. .....................55 chapter 5 microcontroller boot 5.1 boot mechanism ............................................................................................................. .................75 5.1.1 flash memory boot ........................................................................................................ .76 5.1.2 serial boot mode ......................................................................................................... ....78 5.1.3 censorship ............................................................................................................... .......78 5.2 boot assist m odule (bam) ................................................................................................... .........83 5.2.1 bam software flow ........................................................................................................ 83 5.2.2 linflex (rs232) boot ....................................................................................................9 1 5.2.3 flexcan boot ............................................................................................................. ...92 5.3 system status and configur ation module (s scm) ........................................................................94 5.3.1 introducti on ............................................................................................................. .......94 5.3.2 features ................................................................................................................. ..........94 5.3.3 modes of ope ration ............ ........................................................................................... ..95 5.3.4 memory map and regist er description ............................................................................95 chapter 6 clock description 6.1 clock archite cture ......................................................................................................... ................105 6.2 clock gating ............................................................................................................... ...................106 6.3 fast external crystal oscillator (fxosc) digital interface ............................................................107 6.3.1 main featur es ............................................................................................................ ....107 6.3.2 functional descri ption ..................................................................................................1 07 6.3.3 register desc ription ..................................................................................................... .108 6.4 slow external crysta l oscillator (sxosc) di gital interface ..........................................................109 6.4.1 introducti on ............................................................................................................. .....109 6.4.2 main featur es ............................................................................................................ ....109 6.4.3 functional descri ption ..................................................................................................1 09 6.4.4 register desc ription ..................................................................................................... .110 6.5 slow internal rc oscillator (sirc) digital interface .................................................................... 111 6.5.1 introducti on ............................................................................................................. ..... 111 6.5.2 functional descri ption ..................................................................................................1 12 6.5.3 register desc ription ..................................................................................................... .112 6.6 fast internal rc oscillator (f irc) digital interface ......................................................................1 13 6.6.1 introducti on ............................................................................................................. .....113 6.6.2 functional descri ption ..................................................................................................1 13 6.6.3 register desc ription ..................................................................................................... .114
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 5 6.7 frequency-modulated phase-l ocked loop (fmpll) .....................................................................115 6.7.1 introducti on ............................................................................................................. .....115 6.7.2 overview ................................................................................................................. .....115 6.7.3 features ................................................................................................................. ........115 6.7.4 memory map ............................................................................................................... .116 6.7.5 register desc ription ..................................................................................................... .116 6.7.6 functional descri ption ..................................................................................................1 20 6.7.7 recommendati ons ........................................................................................................12 2 6.8 clock monitor uni t (cmu) ................................................................................................... .........123 6.8.1 introducti on ............................................................................................................. .....123 6.8.2 main featur es ............................................................................................................ ....123 6.8.3 block diagram ............................................................................................................ ..124 6.8.4 functional descri ption ..................................................................................................1 24 6.8.5 memory map and regist er description ..........................................................................126 chapter 7 clock generation module (mc_cgm) 7.1 overview ................................................................................................................... ....................131 7.2 features ................................................................................................................... ......................132 7.3 modes of ope ration ......................................................................................................... ...............133 7.3.1 normal and reset mode s of operation ...........................................................................133 7.4 external signal description ................................................................................................ ............133 7.5 memory map and regist er definition ......................................................................................... ....133 7.5.1 register descri ptions .................................................................................................... 137 7.5.2 output clock division select register (cgm_ocds_sc) ........................................138 7.5.3 system clock select status register (cgm_sc_ss) ..................................................139 7.6 functional description ..................................................................................................... .............142 7.6.1 system clock ge neration .............................................................................................142 7.6.2 output clock mu ltiplexing ...........................................................................................143 7.6.3 output clock divisi on selection ..................................................................................144 chapter 8 mode entry module (mc_me) 8.1 overview ................................................................................................................... ....................145 8.1.1 features ................................................................................................................. ........145 8.1.2 modes of ope ration ............ ........................................................................................... 146 8.2 external signal description ................................................................................................ ............147 8.3 memory map and regist er definition ......................................................................................... ....147 8.3.1 register descri ptions .................................................................................................... 150 8.4 functional description ..................................................................................................... ..............163 8.4.1 mode transition request ................................................................................................16 3 8.4.2 modes deta ils ............................................................................................................ ....164 8.4.3 mode transition process ................................................................................................16 7 8.4.4 protection of mode confi guration regist ers ..................................................................175 8.4.5 mode transition in terrupts ............................................................................................175
MPC5606BK microcontroller reference manual, rev. 2 6 freescale semiconductor 8.4.6 application ex ample .....................................................................................................1 77 chapter 9 reset generation module (mc_rgm) 9.1 introducti on ............................................................................................................... ....................179 9.1.1 overview ................................................................................................................. .....179 9.1.2 features ................................................................................................................. ........180 9.1.3 modes of ope ration ............ ........................................................................................... 181 9.2 external signal description ................................................................................................ ............181 9.3 memory map and regist er definition ......................................................................................... ....182 9.3.1 register descri ptions .................................................................................................... 183 9.4 functional description ..................................................................................................... ..............188 9.4.1 reset state ma chine ...................................................................................................... 188 9.4.2 destructive re sets ....................................................................................................... ...191 9.4.3 external re set ........................................................................................................... .....192 9.4.4 functional re sets ........................................................................................................ ...192 9.4.5 alternate event ge neration . ...........................................................................................192 9.4.6 boot mode capt uring ....................................................................................................19 3 chapter 10 power control unit (mc_pcu) 10.1 introducti on .............................................................................................................. .....................195 10.1.1 overview ................................................................................................................ ......195 10.1.2 features ................................................................................................................ .........196 10.1.3 modes of ope ration ............ .......................................................................................... .196 10.2 external signal description ............................................................................................... .............197 10.3 memory map and regist er definition ........................................................................................ .....197 10.3.1 register descri ptions ................................................................................................... .199 10.4 functional description .................................................................................................... ...............202 10.4.1 general ................................................................................................................. ........202 10.4.2 reset / power-on reset ................................................................................................20 3 10.4.3 mc_pcu configur ation ................................................................................................203 10.4.4 mode transi tions ........................................................................................................ ...203 10.5 initialization in formation ................................................................................................ ...............205 10.6 application information ................................................................................................... .............206 10.6.1 standby mode cons iderations ................................................................................206 chapter 11 voltage regulators and power supplies 11.1 voltage regulators ........................................................................................................ ..................207 11.1.1 high power regulat or (hpreg) ...................................................................................207 11.1.2 low power regulator (lpreg) ....................................................................................207 11.1.3 ultra low power regulator (ulpreg) .........................................................................208 11.1.4 lvds and por ............................................................................................................ .208 11.1.5 vreg digital in terface .................................................................................................2 08
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 7 11.1.6 register desc ription .................................................................................................... ..209 11.2 power supply strategy ..................................................................................................... ..............209 11.3 power domain or ganization ................................................................................................. ..........210 chapter 12 wakeup unit (wkpu) 12.1 overview .................................................................................................................. .....................213 12.2 features .................................................................................................................. .......................215 12.3 external signal description ............................................................................................... .............216 12.4 memory map and regist er description ....................................................................................... ....216 12.4.1 memory map .............................................................................................................. ..216 12.4.2 nmi status flag register (nsr) ..................................................................................217 12.4.3 nmi configuration re gister (ncr) .............................................................................218 12.4.4 wakeup/interrupt status flag register (wisr) ...........................................................219 12.4.5 interrupt request enable register (irer) ...................................................................219 12.4.6 wakeup request enable re gister (wrer) ..................................................................220 12.4.7 wakeup/interrupt rising- edge event enable re gister (wireer) .............................220 12.4.8 wakeup/interrupt falling-edge even t enable register (wifeer) .............................221 12.4.9 wakeup/interrupt filter enab le register (wifer) ......................................................221 12.4.10 wakeup/interrupt pullup enable register (wipuer) .................................................222 12.5 functional description .................................................................................................... ...............222 12.5.1 general ................................................................................................................. ........222 12.5.2 non-maskable in terrupts ..............................................................................................223 12.5.3 external wakeups/interrupts .........................................................................................224 12.5.4 on-chip wake ups ......................................................................................................... .226 chapter 13 real time clock / autonomous periodic interrupt (rtc/api) 13.1 overview .................................................................................................................. .....................227 13.2 features .................................................................................................................. .......................227 13.3 device-specific in formation ............................................................................................... ...........229 13.4 modes of ope ration ........................................................................................................ ................229 13.4.1 functional mo de ......................................................................................................... ..229 13.4.2 debug mode .............................................................................................................. ....230 13.5 register desc riptions ..................................................................................................... ................230 13.5.1 rtc supervisor control re gister (rtcsupv) ...........................................................230 13.5.2 rtc control regist er (rtcc) .....................................................................................231 13.5.3 rtc status register (rtcs) ........................................................................................233 13.5.4 rtc counter register (rtccnt) ...............................................................................234 13.6 rtc functional de scription ................................................................................................ ...........234 13.7 api functional description ................................................................................................ ............235 chapter 14 can sampler 14.1 introducti on .............................................................................................................. .....................237
MPC5606BK microcontroller reference manual, rev. 2 8 freescale semiconductor 14.2 main feat ures ............................................................................................................. ....................237 14.3 memory map and regist er description ....................................................................................... ....238 14.3.1 control register (cr) ................................................................................................... 238 14.3.2 can sampler sample registers 0?11 ..........................................................................239 14.4 functional description .................................................................................................... ...............239 14.4.1 enabling/disabling th e can sampler ...........................................................................240 14.4.2 selecting the rx port ................................................................................................... .240 14.4.3 baud rate gene ration .................................................................................................... .241 chapter 15 e200z0h core 15.1 overview .................................................................................................................. .....................245 15.2 microarchitectur e summary ................................................................................................. .........245 15.3 block diagram ............................................................................................................. ..................247 15.4 features .................................................................................................................. .......................247 15.4.1 instruction unit features ............................................................................................... .248 15.4.2 integer unit fe atures ................................................................................................... ...248 15.4.3 load/store unit f eatures ...............................................................................................2 49 15.4.4 e200z0h system bus features ........................................................................................249 15.5 core registers and pr ogrammer?s model ..................................................................................... ..249 chapter 16 enhanced direct me mory access (edma) 16.1 device-specific features .................................................................................................. ..............253 16.2 introducti on .............................................................................................................. .....................253 16.2.1 features ................................................................................................................ .........254 16.3 memory map and regist er definition ........................................................................................ .....255 16.3.1 memory map .............................................................................................................. ..255 16.3.2 register descri ptions ................................................................................................... .257 16.4 functional description .................................................................................................... ...............278 16.4.1 edma basic data flow ..................................................................................................28 0 16.5 initialization / applic ation information .................................................................................. ........283 16.5.1 edma initiali zation ..................................................................................................... .283 16.5.2 dma programming er rors ............................................................................................285 16.5.3 dma request assi gnments ............................................................................................286 16.5.4 dma arbitration mode considerations .........................................................................286 16.5.5 dma transf er ............................................................................................................ ....287 16.5.6 tcd status .............................................................................................................. ......290 16.5.7 channel linking ......................................................................................................... ...291 16.5.8 dynamic programming .................................................................................................292 chapter 17 edma channel multiplexer (dma_mux) 17.1 introducti on .............................................................................................................. .....................295 17.2 features .................................................................................................................. .......................295
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 9 17.3 modes of ope ration ........................................................................................................ ................296 17.4 external signal description ............................................................................................... .............296 17.5 memory map and regist er definition ........................................................................................ .....296 17.5.1 channel configuration regi sters (chconfign) ..........................................................297 17.6 dma_mux inputs ............................................................................................................ ...........298 17.6.1 dma_mux periphera l sources ...................................................................................298 17.6.2 dma_mux periodic tr igger inputs .............................................................................300 17.7 functional description .................................................................................................... ...............300 17.7.1 edma channels with period ic triggering capability ....................................................300 17.7.2 edma channels with no tr iggering capabil ity .............................................................302 17.8 initialization/applicat ion informat ion .................................................................................... .......303 17.8.1 reset ................................................................................................................... ..........303 17.8.2 enabling and configur ing sources ................................................................................303 chapter 18 interrupt controller (intc) 18.1 introducti on .............................................................................................................. .....................307 18.2 features .................................................................................................................. .......................307 18.3 block diagram ............................................................................................................. ..................309 18.4 modes of ope ration ........................................................................................................ ................309 18.4.1 normal m ode ............................................................................................................. ...309 18.5 memory map and regist er description ....................................................................................... ....311 18.5.1 module memory map ...................................................................................................311 18.5.2 register desc ription .................................................................................................... ..311 18.6 functional description .................................................................................................... ...............319 18.6.1 interrupt reques t sources ............................................................................................... 327 18.6.2 priority manage ment ....................................................................................................3 28 18.6.3 handshaking with processor .........................................................................................330 18.7 initialization/applica tion informat ion .................................................................................... ........332 18.7.1 initialization flow ..................................................................................................... ....332 18.7.2 interrupt exception handler ...........................................................................................33 2 18.7.3 isr, rtos, and task hierarchy .....................................................................................334 18.7.4 order of ex ecution ...................................................................................................... ..335 18.7.5 priority ceiling protocol ............................................................................................... .336 18.7.6 selecting priorities according to request rates and deadlines .......................................336 18.7.7 software configurable interrupt requests ......................................................................337 18.7.8 lowering priority within an isr ..................................................................................338 18.7.9 negating an interrupt request outside of its isr ..........................................................338 18.7.10 examining lifo c ontents ............................................................................................339 chapter 19 crossbar switch (xbar) 19.1 introducti on .............................................................................................................. .....................341 19.2 block diagram ............................................................................................................. ..................341 19.3 overview .................................................................................................................. .....................342
MPC5606BK microcontroller reference manual, rev. 2 10 freescale semiconductor 19.4 features .................................................................................................................. .......................342 19.5 modes of ope ration ........................................................................................................ ................342 19.5.1 normal m ode ............................................................................................................. ...342 19.5.2 debug mode .............................................................................................................. ....342 19.6 functional description .................................................................................................... ...............342 19.6.1 overview ................................................................................................................ ......342 19.6.2 general operation ....................................................................................................... ..343 19.6.3 master por ts ............................................................................................................ ......343 19.6.4 slave ports ............................................................................................................. .......344 19.6.5 priority assi gnment ..................................................................................................... ..344 19.6.6 arbitrati on ............................................................................................................. .......344 chapter 20 system integration unit lite (siul) 20.1 introducti on .............................................................................................................. .....................347 20.2 overview .................................................................................................................. .....................347 20.3 features .................................................................................................................. .......................349 20.4 external signal description ............................................................................................... .............349 20.4.1 detailed signal de scriptions ..........................................................................................35 0 20.5 memory map and regist er description ....................................................................................... ....351 20.5.1 siul memory map .......................................................................................................35 1 20.5.2 register prot ection ..................................................................................................... ...352 20.5.3 register descri ptions ................................................................................................... .353 20.6 functional description .................................................................................................... ...............372 20.6.1 pad control ............................................................................................................. .......372 20.6.2 general purpose input and out put pads (gpio) ...........................................................372 20.6.3 external interrupts ..................................................................................................... ...373 20.7 pin muxing ................................................................................................................ ....................374 chapter 21 memory protection unit (mpu) 21.1 introducti on .............................................................................................................. .....................375 21.2 features .................................................................................................................. .......................376 21.3 modes of ope ration ........................................................................................................ ................377 21.4 external signal description ............................................................................................... .............377 21.5 memory map and regist er description ....................................................................................... ....377 21.5.1 memory map .............................................................................................................. ..378 21.5.2 register desc ription .................................................................................................... ..379 21.6 functional description .................................................................................................... ...............390 21.6.1 access evaluation macro ..............................................................................................390 21.6.2 putting it all together and ahb error termin ations ......................................................391 21.7 initialization in formation ................................................................................................ ...............392 21.8 application information ................................................................................................... .............392
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 11 chapter 22 inter-integrated circuit bus controller module (i 2 c) 22.1 introducti on .............................................................................................................. .....................397 22.1.1 overview ................................................................................................................ ......397 22.1.2 features ................................................................................................................ .........397 22.1.3 block diagram ........................................................................................................... ...398 22.2 external signal description ............................................................................................... .............398 22.2.1 scl ..................................................................................................................... ..........398 22.2.2 sda ..................................................................................................................... .........398 22.3 memory map and regist er description ....................................................................................... ....398 22.3.1 module memory map ...................................................................................................398 22.3.2 i 2 c bus address regist er (ibad) ...............................................................................399 22.3.3 i 2 c bus frequency divider re gister (ibfd) ...............................................................400 22.3.4 i 2 c bus control register (ibcr) .................................................................................406 22.3.5 i 2 c bus status regist er (ibsr) ....................................................................................407 22.3.6 i 2 c bus data i/o register (ibdr) ...............................................................................408 22.3.7 i 2 c bus interrupt configurati on register (ibic) .........................................................409 22.4 dma interface ............................................................................................................. .................409 22.5 functional description .................................................................................................... ...............411 22.5.1 i-bus protocol .......................................................................................................... .....411 22.5.2 interrupts .............................................................................................................. .........414 22.6 initialization/applica tion informat ion .................................................................................... ........415 22.6.1 i 2 c programming examples ..........................................................................................415 chapter 23 lin controller (linflex) 23.1 introducti on .............................................................................................................. .....................421 23.2 main feat ures ............................................................................................................. ....................421 23.2.1 lin mode feat ures ....................................................................................................... .421 23.2.2 uart mode feat ures ....................................................................................................42 1 23.2.3 features common to lin and uart ...........................................................................421 23.3 general description ....................................................................................................... ................422 23.4 fractional baud rate generati on ........................................................................................... ..........423 23.5 operating modes ........................................................................................................... ................425 23.5.1 initialization mode ..................................................................................................... ...426 23.5.2 normal m ode ............................................................................................................. ...426 23.5.3 low power mode (sleep) .............................................................................................426 23.6 test modes ................................................................................................................ .....................426 23.6.1 loop back m ode .......................................................................................................... .426 23.6.2 self test mode .......................................................................................................... ....427 23.7 memory map and regist ers description ...................................................................................... ...427 23.7.1 memory map .............................................................................................................. ..427 23.8 functional description .................................................................................................... ...............453 23.8.1 uart mode ............................................................................................................... ...453 23.8.2 lin mode ................................................................................................................ ......455
MPC5606BK microcontroller reference manual, rev. 2 12 freescale semiconductor 23.8.3 8-bit timeout counter ................................................................................................... .463 23.8.4 interrupts .............................................................................................................. .........465 chapter 24 lin controller (linflexd) 24.1 introducti on .............................................................................................................. .....................467 24.2 main feat ures ............................................................................................................. ....................467 24.2.1 lin mode feat ures ....................................................................................................... .468 24.2.2 uart mode feat ures ....................................................................................................46 8 24.3 the lin protocol .......................................................................................................... .................469 24.3.1 dominant and recessive logic levels ............................................................................469 24.3.2 lin frames .............................................................................................................. ......469 24.3.3 lin header .............................................................................................................. ......470 24.3.4 response ................................................................................................................ .......471 24.4 linflexd and software interventi on ........................................................................................ ....472 24.5 summary of opera ting modes ................................................................................................ .......472 24.6 controller-level ope rating modes .......................................................................................... ........473 24.6.1 initialization mode ..................................................................................................... ...473 24.6.2 normal m ode ............................................................................................................. ...474 24.6.3 sleep (low-power ) mode ..............................................................................................474 24.7 lin modes ................................................................................................................. ....................474 24.7.1 master m ode ............................................................................................................. ....474 24.7.2 slave mode .............................................................................................................. .....476 24.7.3 slave mode with identi fier filtering ..............................................................................478 24.7.4 slave mode with automati c resynchronization .............................................................481 24.8 test modes ................................................................................................................ .....................482 24.8.1 loop back m ode .......................................................................................................... .482 24.8.2 self test mode .......................................................................................................... ....483 24.9 uart mode ................................................................................................................. .................483 24.9.1 data frame structure .................................................................................................... .483 24.9.2 buffer .................................................................................................................. ..........485 24.9.3 uart transmit ter ........................................................................................................ .485 24.9.4 uart receive r ........................................................................................................... ...486 24.10 memory map and regist er description ...................................................................................... .....488 24.10.1 lin control register 1 (lincr1) .................................................................................488 24.10.2 lin interrupt enable re gister (linier) .......................................................................491 24.10.3 lin status register (linsr) .........................................................................................493 24.10.4 lin error status register (linesr) ..............................................................................496 24.10.5 uart mode control register (uartcr) .....................................................................497 24.10.6 uart mode status regi ster (uartsr) .......................................................................500 24.10.7 lin timeout contro l status register (lintcsr) ..........................................................502 24.10.8 lin output compare regi ster (linocr) ......................................................................503 24.10.9 lin timeout control regi ster (lintocr) ....................................................................504 24.10.10 lin fractional baud rate register (linfbrr) ..............................................................505 24.10.11 lin integer baud rate re gister (linibrr) ...................................................................505
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 13 24.10.12 lin checksum field regi ster (lincfr) .......................................................................506 24.10.13 lin control register 2 (lincr2) .................................................................................507 24.10.14 buffer identifier re gister (bidr) ..................................................................................508 24.10.15 buffer data register leas t significant (bdrl) ..............................................................509 24.10.16 buffer data register most significant (bdrm) .............................................................510 24.10.17 identifier filter enable register (ifer) ..........................................................................511 24.10.18 identifier filter matc h index (ifmi) ..............................................................................512 24.10.19 identifier filter mode register (ifmr) ..........................................................................513 24.10.20 identifier filter control re gisters (ifcr0?i fcr15) ......................................................513 24.10.21 global control register (gcr) ......................................................................................514 24.10.22 uart preset timeout regi ster (uartpto) .................................................................516 24.10.23 uart current timeout regi ster (uartcto) ...............................................................516 24.10.24 dma tx enable regist er (dmatxe) ...........................................................................517 24.10.25 dma rx enable regist er (dmarxe) ..........................................................................518 24.11 dma interface ............................................................................................................ ...................518 24.11.1 master node, tx mode .................................................................................................51 9 24.11.2 master node, rx mode .................................................................................................52 2 24.11.3 slave node, tx mode ...................................................................................................5 24 24.11.4 slave node, rx mode ...................................................................................................5 27 24.11.5 uart node, tx mode .................................................................................................530 24.11.6 uart node, rx mode .................................................................................................532 24.11.7 use cases and li mitations .............................................................................................. 535 24.12 functional description ................................................................................................... ................536 24.12.1 8-bit timeout counter .................................................................................................. ..536 24.12.2 interrupts ............................................................................................................. ..........537 24.12.3 fractional baud rate generation ....................................................................................539 24.13 programming consid erations ............................................................................................... ..........540 24.13.1 master node ............................................................................................................ ......540 24.13.2 slave node ............................................................................................................. .......541 24.13.3 extended frames ........................................................................................................ ...545 24.13.4 timeout ................................................................................................................ .........545 24.13.5 uart mode .............................................................................................................. ....546 chapter 25 flexcan 25.1 information specific to this devi ce ....................................................................................... .........547 25.1.1 device-specific fe atures ...............................................................................................5 47 25.2 introducti on .............................................................................................................. .....................547 25.2.1 overview ................................................................................................................ ......548 25.2.2 flexcan module features ............................................................................................549 25.2.3 modes of ope ration ............ .......................................................................................... .549 25.3 external signal description ............................................................................................... .............550 25.3.1 overview ................................................................................................................ ......550 25.3.2 signal descri ptions ..................................................................................................... ...551 25.4 memory map/register definition ............................................................................................ ........551
MPC5606BK microcontroller reference manual, rev. 2 14 freescale semiconductor 25.4.1 flexcan memory mapping .........................................................................................551 25.4.2 message buffer st ructure .............................................................................................553 25.4.3 rx fifo structure ....................................................................................................... ..556 25.4.4 register descri ptions ................................................................................................... .557 25.5 functional description .................................................................................................... ...............576 25.5.1 overview ................................................................................................................ ......576 25.5.2 local priority tr ansmission ...........................................................................................57 7 25.5.3 transmit pr ocess ........................................................................................................ ...577 25.5.4 arbitration pr ocess ..................................................................................................... ..578 25.5.5 receive pro cess ......................................................................................................... ...579 25.5.6 matching pro cess ........................................................................................................ ..580 25.5.7 data coherence .......................................................................................................... ...581 25.5.8 rx fifo ................................................................................................................. .......584 25.5.9 can protocol relate d features ......................................................................................584 25.5.10 modes of operatio n details ...........................................................................................58 8 25.5.11 interrupt s ............................................................................................................. ..........589 25.5.12 bus interface .......................................................................................................... .......590 25.6 initialization/applica tion informat ion .................................................................................... ........591 25.6.1 flexcan initialization sequence ..................................................................................591 25.6.2 flexcan addressing and ram size configurations ....................................................592 chapter 26 deserial serial peripheral interface (dspi) 26.1 introducti on .............................................................................................................. .....................593 26.2 features .................................................................................................................. .......................594 26.3 modes of ope ration ........................................................................................................ ................595 26.3.1 master m ode ............................................................................................................. ....595 26.3.2 slave mode .............................................................................................................. .....595 26.3.3 module disable mode ...................................................................................................59 5 26.3.4 debug mode .............................................................................................................. ....596 26.4 external signal description ............................................................................................... .............596 26.4.1 signal overv iew ......................................................................................................... ...596 26.4.2 signal names and de scriptions ......................................................................................596 26.5 memory map and regist er description ....................................................................................... ....597 26.5.1 memory map .............................................................................................................. ..597 26.5.2 dspi module configuration register (dspix_mcr) .................................................598 26.5.3 dspi transfer count register (dspix_tcr) ..............................................................601 26.5.4 dspi clock and transfer attribut es registers 0?5 (dspix_ctarn) .........................602 26.5.5 dspi status register (dspix_sr) ...............................................................................610 26.5.6 dspi dma / interrupt request select a nd enable register (dspix_rser) ..............612 26.5.7 dspi push tx fifo regi ster (dspix_pushr) .......................................................614 26.5.8 dspi pop rx fifo regist er (dspix_popr) ............................................................616 26.5.9 dspi transmit fifo regi sters 0?3 (dspix_txfrn) .................................................617 26.6 functional description .................................................................................................... ...............618 26.6.1 modes of ope ration ............ .......................................................................................... .619
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 15 26.6.2 start and stop of ds pi transfers ...................................................................................620 26.6.3 serial peripheral interface (spi) configur ation .............................................................621 26.6.4 dspi baud rate and cloc k delay genera tion ..................................................................624 26.6.5 transfer formats ........................................................................................................ ...627 26.6.6 continuous serial comm unications clock .....................................................................634 26.6.7 interrupt/dma re quests ................................................................................................63 5 26.6.8 power saving f eatures ................................................................................................... 637 26.7 initialization and applic ation inform ation ................................................................................ .....638 26.7.1 how to change queues ..................................................................................................63 8 26.7.2 baud rate sett ings ...................................................................................................... ...638 26.7.3 delay settings .......................................................................................................... .....640 26.7.4 calculation of fifo poi nter addresses .........................................................................640 chapter 27 timers 27.1 introducti on .............................................................................................................. .....................645 27.2 technical ove rview ........................................................................................................ ................645 27.2.1 overview of th e stm ...................................................................................................64 7 27.2.2 overview of th e emios .... ...........................................................................................647 27.2.3 overview of the pit ..................................................................................................... 649 27.3 system timer m odule (stm) ................................................................................................. ......649 27.3.1 introducti on ............................................................................................................ ......649 27.3.2 external signal de scription ...........................................................................................65 0 27.3.3 memory map and regist er definition ............................................................................650 27.3.4 functional desc ription .................................................................................................. 654 27.4 enhanced modular io s ubsystem (emios) .................................................................................655 27.4.1 introducti on ............................................................................................................ ......655 27.4.2 external signal de scription ...........................................................................................65 8 27.4.3 memory map and regist er description ..........................................................................658 27.4.4 functional desc ription .................................................................................................. 670 27.4.5 initialization/applicat ion information ..........................................................................700 27.5 periodic interrupt timer (pit ) ............................................................................................ ..........704 27.5.1 introducti on ............................................................................................................ ......704 27.5.2 features ................................................................................................................ .........704 27.5.3 signal descri ption ...................................................................................................... ...705 27.5.4 memory map and regist er description ..........................................................................705 27.5.5 functional desc ription .................................................................................................. 709 27.5.6 initialization and applic ation informat ion ....................................................................710 chapter 28 analog-to-digital converter (adc) 28.1 overview .................................................................................................................. .....................715 28.1.1 device-specific fe atures ...............................................................................................7 15 28.1.2 device-specific impl ementation ...................................................................................716 28.2 introducti on .............................................................................................................. .....................717
MPC5606BK microcontroller reference manual, rev. 2 16 freescale semiconductor 28.3 functional description .................................................................................................... ...............717 28.3.1 analog channel c onversion ..........................................................................................717 28.3.2 analog clock generator and conversion timings ..........................................................720 28.3.3 adc sampling and conversion timing .........................................................................720 28.3.4 adc ctu (cross triggering unit) ..............................................................................725 28.3.5 presampling ............................................................................................................. .....726 28.3.6 programmable analog watchdog ..................................................................................727 28.3.7 dma functiona lity ....................................................................................................... 728 28.3.8 interrupts .............................................................................................................. .........728 28.3.9 external decode si gnals delay ......................................................................................729 28.3.10 power-down mode ........................................................................................................ 729 28.3.11 auto-clock-of f mode .................................................................................................... 729 28.4 register desc riptions ..................................................................................................... ................730 28.4.1 introducti on ............................................................................................................ ......730 28.4.2 control logic re gisters ................................................................................................. .737 28.4.3 interrupt regi sters ..................................................................................................... .....740 28.4.4 dma regist ers ........................................................................................................... ...748 28.4.5 threshold regi sters ..................................................................................................... ..752 28.4.6 presampling re gisters ................................................................................................... .753 28.4.7 conversion timing regi sters ctr[0..2] ........................................................................756 28.4.8 mask regist ers .......................................................................................................... .....757 28.4.9 delay regist ers ......................................................................................................... .....761 28.4.10 data registers ......................................................................................................... .......763 28.4.11 watchdog regi ster ...................................................................................................... ...765 chapter 29 cross triggering unit (ctu) 29.1 introducti on .............................................................................................................. .....................779 29.2 main feat ures ............................................................................................................. ....................779 29.3 block diagram ............................................................................................................. ..................779 29.4 memory map and regist er descriptions ...................................................................................... ...779 29.4.1 event configuration registers (c tu_evtcfgrx) (x = 0...63) .................................780 29.5 functional description .................................................................................................... ...............781 29.5.1 channel value ........................................................................................................... ....783 chapter 30 flash memory 30.1 introducti on .............................................................................................................. .....................789 30.2 main feat ures ............................................................................................................. ....................790 30.3 block diagram ............................................................................................................. ..................790 30.4 functional description .................................................................................................... ...............791 30.4.1 module struct ure ........................................................................................................ ...791 30.4.2 flash memory module sectorization .............................................................................792 30.4.3 testflash bl ock ......................................................................................................... ....793 30.4.4 shadow sect or ........................................................................................................... ....795
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 17 30.4.5 user mode ope ration .......... ........................................................................................... 795 30.4.6 reset ................................................................................................................... ..........796 30.4.7 power-down mode ........................................................................................................7 97 30.4.8 low power mode .......................................................................................................... 797 30.5 register desc ription ...................................................................................................... .................798 30.5.1 cflash register description ...........................................................................................79 9 30.5.2 dflash register description ...........................................................................................83 4 30.6 programming consid erations ................................................................................................ .........857 30.6.1 modify oper ation ........................................................................................................ ..857 30.6.2 double word pr ogram ...................................................................................................85 8 30.6.3 sector erase ............................................................................................................ .......860 30.7 platform flash memory controller .......................................................................................... .......868 30.7.1 introducti on ............................................................................................................ ......868 30.7.2 memory map and regist er description ..........................................................................871 30.8 functional description .................................................................................................... ...............880 30.8.1 access protec tions ...................................................................................................... ..880 30.8.2 read cycles ? bu ffer miss ............................................................................................880 30.8.3 read cycles ? buffer hit ...............................................................................................8 81 30.8.4 write cycles ............................................................................................................ ......881 30.8.5 error termin ation ....................................................................................................... ...881 30.8.6 access pipeli ning ....................................................................................................... ...881 30.8.7 flash error respons e operation ......................................................................................882 30.8.8 bank0 page read buffers a nd prefetch operation ..........................................................882 30.8.9 bank1 temporary holding register .............................................................................884 30.8.10 read-while-write f unctionality .....................................................................................885 30.8.11 wait-state em ulation ................................................................................................... ..886 chapter 31 static ram (sram) 31.1 introducti on .............................................................................................................. .....................889 31.2 low power config uration ................................................................................................... ...........889 31.3 register memory map ....................................................................................................... ............889 31.4 sram ecc mech anism ........................................................................................................ ........890 31.4.1 access timi ng ........................................................................................................... ....890 31.4.2 reset effects on sram accesses ..................................................................................891 31.5 functional description .................................................................................................... ...............891 31.6 initialization and applic ation inform ation ................................................................................ .....891 chapter 32 register protection 32.1 introducti on .............................................................................................................. .....................895 32.2 features .................................................................................................................. .......................895 32.3 modes of ope ration ........................................................................................................ ................896 32.4 external signal description ............................................................................................... .............896 32.5 memory map and regist er description ....................................................................................... ....896
MPC5606BK microcontroller reference manual, rev. 2 18 freescale semiconductor 32.5.1 memory map .............................................................................................................. ..897 32.5.2 register desc ription .................................................................................................... ..898 32.6 functional description .................................................................................................... ...............900 32.6.1 general ................................................................................................................. ........900 32.6.2 change lock settings .................................................................................................... .900 32.6.3 access erro rs ........................................................................................................... .....904 32.7 reset ..................................................................................................................... .........................904 32.8 protected registers ....................................................................................................... ..................904 chapter 33 software watchdog timer (swt) 33.1 overview .................................................................................................................. .....................913 33.2 features .................................................................................................................. .......................913 33.3 modes of ope ration ........................................................................................................ ................913 33.4 external signal description ............................................................................................... .............914 33.5 memory map and regist er description ....................................................................................... ....914 33.5.1 memory map .............................................................................................................. ..914 33.5.2 register desc ription .................................................................................................... ..915 33.6 functional description .................................................................................................... ...............919 chapter 34 error correction status module (ecsm) 34.1 introducti on .............................................................................................................. .....................923 34.2 overview .................................................................................................................. .....................923 34.3 features .................................................................................................................. .......................923 34.4 memory map and regist er description ....................................................................................... ....923 34.4.1 memory map .............................................................................................................. ..923 34.4.2 register desc ription .................................................................................................... ..924 34.4.3 register prot ection ..................................................................................................... ...942 chapter 35 ieee 1149.1 test access port controller (jtagc) 35.1 introducti on .............................................................................................................. .....................945 35.2 block diagram ............................................................................................................. ..................945 35.3 overview .................................................................................................................. .....................945 35.4 features .................................................................................................................. .......................946 35.5 modes of ope ration ........................................................................................................ ................946 35.5.1 reset ................................................................................................................... ..........946 35.5.2 ieee 1149.1-2001 defined test modes .........................................................................946 35.6 external signal description ............................................................................................... .............947 35.7 memory map and regist er description ....................................................................................... ....947 35.7.1 instruction re gister .................................................................................................... ....947 35.7.2 bypass regi ster ......................................................................................................... .....948 35.7.3 device identificati on register .......................................................................................948 35.7.4 boundary scan register .................................................................................................9 49
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 19 35.8 functional description .................................................................................................... ...............949 35.8.1 jtagc reset configuration ...........................................................................................949 35.8.2 ieee 1149.1-2001 (jtag) te st access port ................................................................949 35.8.3 tap controller st ate machin e .......................................................................................949 35.8.4 jtagc instructions ...................................................................................................... 951 35.8.5 boundary scan ........................................................................................................... ...953 35.9 e200z0 once controller .................................................................................................... ............953 35.9.1 e200z0 once controller block diagram .......................................................................953 35.9.2 e200z0 once controller functional description ...........................................................954 35.9.3 e200z0 once controller re gister description ...............................................................954 35.10 initialization/applica tion informat ion ................................................................................... .........956 appendix a revision history a.1 changes between revi sions 1 and 2 .......................................................................................... ..957
MPC5606BK microcontroller reference manual, rev. 2 20 freescale semiconductor
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 21 chapter 1 preface 1.1 overview the primary objective of th is document is to define the functi onality of the MPC5606BK microcontroller for use by software and hardware developers . the MPC5606BK is built on power architecture ? technology and integrates technol ogies that are important for today?s automotive vehicle body applications. the information in this book is subjec t to change without notic e, as described in the disclaimers on the title page. as with any technical documentation, it is the reader?s responsibil ity to be sure he or she is using the most recent version of the documentation. to locate any published errata or updates for this docum ent, visit the freescale we b site at freescale.com. 1.2 audience this manual is intended for system software and hardware developers and applications programmers who want to develop products with th e MPC5606BK device. it is assumed that the r eader understands operating systems, microprocessor syst em design, basic principles of software and hardware, and basic details of the power architecture. 1.3 guide to this reference manual table 1-1. guide to this reference manual chapter description functional group #title 2 introduction general overview, family description, feature list, and information on how to use the reference manual in conjunction with other available documents. introductory material 3 memory map memory map of all peripherals and memory. memory map 4 signal description pinout diagrams and descriptions of all pads. signals 5 microcontroller boot boot ? boot mechanism ? describes what configur ation is required by the user and what processes are involved when the microcontroller boots from flash memory or serial boot modes. ? describes censorship. ? boot assist module (bam) features of bam code and when it's used. ? system status and configuration module (sscm) reports information about current state and configuration of the microcontroller.
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 22 freescale semiconductor 6 clock description ? covers configuration of all of the clock sources in the system. ? describes the clock monitor unit (cmu). clocks and power (includes operating mode configuration and how to wake up from low power mode) 7 clock generation module (mc_cgm) determines how the clock sources are used (including clock dividers) to generate the reference clocks for all of the modules and peripherals. 8 mode entry module (mc_me) determines the clock source, memory, power, and peripherals that are availa ble in each operating mode. 9 reset generation module (mc_rgm) manages the process of entering and exiting reset, allows reset sources to be configured (including lvds), and provides status reporting. 10 power control unit (mc_pcu) controls the power to different power domains within the microcontroller (allowing sram to be selectively powered in standby mode). 11 voltage regulators and power supplies information on voltage regulator implementation. includes enable bit for 5 v lvd (see also mc_rgm). 12 wakeup unit (wkpu) always-active analog block. details configuration of two internal (api/rtc) and 27 external (pin) low power mode wakeup sources. 13 real time clock / autonomous periodic interrupt (rtc/api) details configuration and operation of timers that are predominately used for system wakeup. 14 can sampler details on how to configure the can sampler, which is used to capture the identifier frame of a can message when the microcontroller is in low power mode. table 1-1. guide to this reference manual (continued) chapter description functional group #title
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 23 15 e200z0h core overview on cores. for more details consult the core reference manuals available on www.freescale.com. core platform modules 16 enhanced direct memory access (edma) operation and configuration information on the 32-channel direct memory access that can be used to transfer data between any memory mapped locations. certain peripherals have edma triggers that can be used to feed configuration data to, or read results from the peripherals. 17 edma channel multiplexer (dma_mux) operation and configuration information for the edma multiplexer, which takes the possible edma sources (triggers from the dspi, emios, i 2 c, adc, and linflexd) and multiplexes them onto the edma channels. 18 interrupt controller (intc) provides the configuration and control of all of the external interrupts (non-core) that are then routed to the ivor4 core interrupt vector. 19 crossbar switch (xbar) describes the connections of the xbar masters and slaves on this microcontroller. 21 memory protection unit (mpu) the mpu sits on the slave side of the xbar and allows highly configurable control over all master accesses to the memory. 20 system integration unit lite (siul) how to configure the pins or ports for input or output functions including external interrupts. ports 22 inter-integrated circuit bus controller module (i2c) these chapters describe the configuration and operation of the various communication modules. some of these modules support dma requests to fill / empty buffer queues to minimize cpu overhead. communication modules 23 lin controller (linflex) 24 lin controller (linflexd) 25 flexcan 26 deserial serial peripheral interface (dspi) table 1-1. guide to this reference manual (continued) chapter description functional group #title
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 24 freescale semiconductor 27 timers timer modules ? technical overview gives an overview of the available system timer modules showing links to other modules as well as tables detailing the external pins associated with emios timer channels. ? system timer module (stm) a simple 32-bit free running counter with 4 compare channels with interrupt on match. it can be read at any time; this is very useful for measuring execution times. ? enhanced modular io subsystem (emios) highly configurable timer module(s) supporting pwm, output compare, and input ca pture features. includes interrupt and edma support. ? periodic interrupt timer (pit) set of 32-bit countdown timers that provide periodic events (which can trigger an interrupt) with automatic reload. 28 analog-to-digital converter (adc) details the configuration and operation of the adc modules as well as detailing the channels that are shared between the 10-bit and 12-bit adc. the adc is tightly linked to the intc, edma, pit, and ctu. when used in conjunction with these other modules, the cpu overhead for an adc conversion is significantly reduced. adc system 29 cross triggering unit (ctu) the ctu allows an adc conversion to be automatically triggered based on an emios event (like a pwm output going high) or a pit_rti event with no cpu intervention. 30 flash memory details the code and data flash memory structure (with ecc), block sizes and the flash memory port configuration, including wait states, line buffer configuration, and pre-fetch control. memory 31 static ram (sram) details the structure of the sram (with ecc). there are no user configurable registers associated with the sram. table 1-1. guide to this reference manual (continued) chapter description functional group #title
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 25 1.4 register description conventions the register information fo r MPC5606BK is presented in: ? memory maps containing: ? an offset from the module?s base address ? the name and acronym/abbr eviation of each register ? the page number on which eac h register is described ? register figures ? field-description tables ? associated text the register figures show the field structure using the conventions in figure 1-1 . figure 1-1. register figure conventions the numbering of register bits and fields on MPC5606BK is as follows: 32 register protection certain registers in each peripheral can be protected from further writes using the register protection mechanism detailed in this section. registers can either be configured to be unlocked via a soft lock bit or locked unit the next reset. integrity 33 software watchdog timer (swt) the swt offers a selection of configurable modes that can be used to monitor the operation of the microcontroller and /or reset the device or trigger an interrupt if the swt is not correctly serviced. the swt is enabled out of reset. 34 error correction status module (ecsm) provides information about the last reset, general device information, system fault information and detailed ecc error information. 35 ieee 1149.1 test access port controller (jtagc) used for boundary scan as well as device debug. debug table 1-1. guide to this reference manual (continued) chapter description functional group #title r0 1 w r field1 field2 w r field w reserved bits read-only fields read/write fields rfield ww1c ?write 1 to clear? field (field will always read 0) r0 00 w field1 field2 write-only fields
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 26 freescale semiconductor ? register bit numbers, shown at the top of each figure, use the standard power architecture bit ordering (0, 1, 2, ...) where bit 0 is the most significant bit (msb). ? multi-bit fields within a regist er use conventional bit ordering ( ..., 2, 1, 0) where bit 0 is the least significant bit (lsb). 1.5 references in addition to this reference manual, the followi ng documents provide additi onal information on the operation of the MPC5606BK: ? ieee 1149.1-2001 standard?ieee standard test access port and bounda ry-scan architecture ? power architecture book e v1.0 (http://www.freescale.com/files/ 32bit/doc/user_guide/book_eum.pdf) 1.6 how to use the MPC5606BK documents this section: ? describes how the MPC5606BK documents provide information on the microcontroller ? makes recommendations on how to us e the documents in a system design 1.6.1 the MPC5606BK document set the MPC5606BK document set comprises: ? this reference manual (provides in formation on the features of the logical blocks on the device and how they are integrated with each other) ? the device data sheet (specifies the el ectrical characteristics of the device) ? the device product brief the following reference documents (available online at www.freescale.com) are also available to support the cpu on this device: ? programmer?s reference manual for freescale embedded processors ? e200z0 power architectur e core reference manual ? variable-length encoding (vle) programming environments manual the aforementioned documents describe all of the functional and electrical characteristics of the MPC5606BK microcontroller. depending on your task, you may need to refer to multiple documents to make design decisions. however, in general the use of the documents can be divided up as follows: ? use the reference manual (this document) dur ing software development and when allocating functions during system design. ? use the data sheet when designing hard ware and optimizing power consumption. ? use the cpu reference documents when: ? configuring cpu memory and branch optimizations
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 27 ? doing detailed software development in assembly language ? debugging complex software interactions 1.6.2 reference manual content the content in this document focuses on the functi onality of the microcontroller rather than its performance. most chapters describe the functionality of a particular on-chip module, such as a can controller or timer. the remaining chapters describe how these modules are integrated into the memory map, how they are powered and clocked, and the pin-out of the device. in general, when an individual modul e is enabled for use all of the detail required to configure and operate it is contained in the dedicated chap ter. in some cases ther e are multiple implementa tions of this module, however, there is only one chapter for each type of mo dule in use. for this reas on, the address of registers in each module is normally provide d as an offset from a base address that can be found in chapter 3, memory map . the benefit of this approach is that software developed for a pa rticular module can be easily reused on this device and on other rela ted devices that use the same modules. the steps to enable a module for use varies but typi cally these require configur ation of the integration features of the microcontroller. the module will normally have to be power ed and enabled at system level, then a clock may have to be explic itly chosen, and finally (if required) the input a nd output connections to the external system must be configured. the primary integration chapters of the reference manual contain most of the information required to enable the modules. there are specia l cases where a chapter may describe module functionality and some integration features for convenience ? for example, the microcontroller input /output (siul) module. integration and functional content is provided in the manual as shown in table 1-2 . table 1-2. reference manual integration and functional content chapter integration content functional content introduction ? the main features on chip ? a summary of the functions provided by each module ? memory map how the memo ry map is allocated, including: ? internal ram ? flash memory ? external memory-mapped resources and the location of the registers used by the peripherals 1 ? signal description how the signals from each of the modules are combined and brought to a particular pin on a package ? boot assist module cpu boot sequence from reset implementation of the boot options if internal flash memory is not used clock description clocking architecture of the device (which clock is available for the system and each peripheral) description of operation of different clock sources
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 28 freescale semiconductor 1.7 using the MPC5606BK there are many different approaches to designing a system using the MPC5606BK so the guidance in this section is provided as an ex ample of how the documents can be applied in this task. familiarity with the MPC5606BK module s can help ensure that its features are bei ng optimally used in a system design. therefore, th e current chapter is a good starting point. further information on the detailed features of a module are provided within the module chapters. these, combined with the current chapter, should provide a good introduction to th e functions available on the mcu. 1.7.1 hardware design the MPC5606BK requires that certain pi ns are connected to particular power supplies, sy stem functions, and other voltage levels for operation. the MPC5606BK internal logic opera tes from 1.2 v (nominal) supplies th at are normally supplied by the on-chip voltage regulator from a 5 v or 3.3 v suppl y. the 3.3?5 v (10%) supply is also used to supply the input/output pins on the mcu. chapter 4, signal description, describes the power supply pin names, numbers, and their purpose. for more detail on the voltage suppl y of each pin, see chapter 11, voltage regulators and power supplies . for specifications of the voltage ranges and limits and decoupling of the power supplies see the MPC5606BK data sheet. certain pins have dedicated functions that affect the behavior of the mc u after reset. these include pins to force test or alternate boot conditions and debug features. these are described in chapter 4, signal description, and a hardware designer should take care that these pins are connected to allow correct operation. beyond power supply and pins that have special functions there are also pins that have special system purposes such as oscillator and rese t pins. these are also described in chapter 4, signal description . the reset pin is bidirectional, and its function is closely tied to the reset generation module [ chapter 9, reset generation module (mc_rgm) ]. the crystal oscillator pins are dedicated to this function but the edma channel multiplexer source values for module edma channels how to connect a module edma channel to the edma module interrupt controller interrupt vector table operation of the module mode entry module module numbering for cont rol and status operation of operating modes system integration unit lite how input signals are mapped to individual modules including external interrupt pins operation of gpio voltage regulators and power supplies power distribution to the mcu ? wakeup unit allocation of inputs to the wakeup unit operation of the wakeup feature 1 to find the address of a register in a particular module ta ke the start address of the module given in the memory map and add the offset for the register given in the module chapter. table 1-2. reference manual integration and functional content (continued) chapter integration content functional content
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 29 oscillator is not started automatically after reset. the oscillator module is described in section 6.3, fast external crystal oscillator (fxosc) digital interface, along with the internal clock architecture and the other oscillator sources on chip. 1.7.2 input/output pins the majority of the pins on the mcu are input/output pins, which may either operate as general purpose pins or be connected to a particul ar on-chip module. the arrangement al lows a function to be available on several pins. the system designer s hould allocate the function for the pi n before connecting to external hardware. the software should then choose the co rrect function to match the hardware. the pad characteristics can vary dependi ng on the functions on the pad. chapter 4, signal description, describes each pad type (for example, s, m, or j). two pads ma y be able to carry the same function but have different pad types. the electrical specificati on of the pads is described in the data sheet dependent on the function enabled and the pad type. there are three modules that configure the various functions available: ? system integration unit lite (siul) ? wakeup unit (wkpu) ? 32 khz oscillator (sxosc) the siul configures the di gital pin functions. each pin has a regi ster (pcr) in the module that allows selection of the output func tions that is connected to the pin. th e available settings for the pcr are described in section 4.2, pin muxing. inputs are selected using the psmi registers; these are described in chapter 20, system integr ation unit lite (siul) . (psmi registers c onnect a module to on e of several pins, whereas the pcr registers connect a pin to one of several modules). the wkpu provides the ability to cause interrupt s and wake the mcu from low power modes, and operates independently from the siul. in addition to digital i/o functions, th e sxosc is a ?special function? that provides a slow external crystal. the sxosc is enabled independently from the digital i/o, which means that the digital function on the pin must be disabled when the sxosc is active. the adc functions are enabled using the pcrs. 1.7.3 software design certain modules provide system inte gration functions, and ot her modules (such as ti mers) provide specific functions. from reset, the modules involved in configur ing the system for application software are: ? boot assist module (bam) ? determines the selected boot source ? reset generation module (mc_rgm) ? determines the behavior of the mcu when various reset sources are triggered and reports the source of the reset ? mode entry module (mc_me) ? controls the opera ting mode the mcu is in and configures the peripherals, clocks, and power supplies for each of the modes ? power control unit (mc_pcu) ? dete rmines which power domains are active
chapter 1 preface MPC5606BK microcontroller reference manual, rev. 2 30 freescale semiconductor ? clock generation module (mc_cgm) ? chooses the clock source for the system and many peripherals after reset, the mcu will automatical ly select the appropriate reset so urce and begin to execute code. at this point the system clock is the 16 mhz firc (inter nal) oscillator, the cpu is in supervisor mode and all the memory is available. initialization is required before most peripherals ma y be used and before the sram can be read (since the sram is protected by ecc, the syndrome will generally be uninitialized after reset and reads would fail th e check). accessing disabled feat ures causes error conditions or interrupts. a typical startup routine would invol ve initializing the soft ware environment including stacks, heaps, memory, and variable initia lization; and configuring th e mcu for the application. the mc_me module enables the modules and other features like clocks. it is therefore an essential part of the initialization and operation so ftware. in general, the software will configure an mc_me mode to make certain peripherals, clocks, and memory active and then switch to that mode. chapter 6, clock description, includes a graphic of the clock archit ecture of the mcu. this can be used to determine how to configure the mc_cgm module. in general software will configure the module to enable the required clocks and plls and route these to the active modules. after these steps are complete it is possible to c onfigure the input/output pins and the modules for the application. 1.7.4 other features the mc_me module manages low power m odes and so it is likely that it will be used to switch into different configurations (module sets, cloc ks) depending on the application requirements. the mcu includes two other features to im prove the integrity of the application: ? it is possible to enable a software watchdog (swt ) immediately at reset or afterwards to help detect code runaway. ? individual register settings can be protected fr om unintended writes using the features of the register protection module. the pr otected registers are shown in chapter 32, register protection . other integration f unctionality is provided by the system status and configur ation module (sscm).
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 31 chapter 2 introduction 2.1 the MPC5606BK microcontroller family the MPC5606BK is a family of power architecture ? -based microcontrollers that target automotive vehicle body applications such as: ? central body electronics ? vehicle body controllers ? smart junction boxes ? front modules ? body peripherals ? door control ? seat control the MPC5606BK family expands the range of the mp c560xb/c microcontroller fa mily. it provides the scalability needed to implement platform appr oaches and delivers the performance required by increasingly sophisticated software architectures. the advanced and cost-efficient host processor core of the MPC5606BK automotive controller family complie s with the power architecture embedded category, and only implements the vle (variable-length enc oding) apu, providing improved code density. it operates at speeds as high as 64 mhz and offers high performance processing optimized for low power consumption. it also capita lizes on the available devel opment infrastructure of cu rrent power architecture devices and is supported with software drivers, operati ng systems, and configuration code to assist with users implementations. this document describes the features of the family and opt ions available within the family members, and highlights important electri cal and physical character istics of the device. 2.2 MPC5606BK device comparison table 2-1 summarizes the MPC5606BK family of microcontrollers. table 2-1. MPC5606BK family comparison 1 feature mpc5605bk MPC5606BK package 100 lqfp 144 lqfp 176 lqfp 100 lqfp 144 lqfp 176 lqfp cpu e200z0h execution speed 2 up to 64 mhz code flash memory 768 kb 1024 kb 1 mb data flash memory 64 (4 x 16) kb sram 64 kb 64 kb 80 kb mpu 8-entry edma 16 ch
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 32 freescale semiconductor 2.3 device block diagram figure 2-1 shows a top-level block diagram of the MPC5606BK. 10-bit adc yes dedicated 3 7ch 15ch 29ch 7ch 15ch 29ch shared with 12-bit adc 19 ch 12-bit adc yes dedicated 4 5 ch shared with 10-bit adc 19 ch total timer i/o 5 emios 37 ch, 16-bit 64 ch, 16-bit 37 ch, 16-bit 64 ch, 16-bit counter / opwm / icoc 6 10 ch o(i)pwm / opwfmb / opwmcb / icoc 7 7ch o(i)pwm / icoc 8 7ch 14ch 7ch 14ch opwm / icoc 9 13 ch 33 ch 13 ch 33 ch sci (linflex) 468468 spi (dspi) 356356 can (flexcan) 6 i 2 c 1 32 khz oscillator yes gpio 10 77 121 149 77 121 149 debug jtag 1 feature set dependent on selected peripheral multiplexing; table shows example. 2 based on 125 ? c ambient operating temperature. 3 not shared with 12-bit adc, but possibly shared with other alternate functions. 4 not shared with 10-bit adc, but possibly shared with other alternate functions. 5 refer to emios section of device reference manual for information on the channel configuration and functions. 6 each channel supports a range of modes including modulus counters, pwm generation, input capture, output compare. 7 each channel supports a range of modes including pwm gen eration with dead time, input capture, output compare. 8 each channel supports a range of modes including pwm generation, input capture, output compare, period and pulse width measurement. 9 each channel supports a range of modes including pwm generation, input capture, and output compare. 10 maximum i/o count based on multiplexing with peripherals. table 2-1. MPC5606BK family comparison 1 (continued) feature mpc5605bk MPC5606BK
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 33 figure 2-1. MPC5606BK block diagram table 2-2 summarizes the functions of th e blocks present on the MPC5606BK. 6 x dspi fmpll sram siul reset control 80 kb external imux gpio & jtag pad control jtag port e200z0h interrupt requests 32-bit 3 3 crossbar switch 6 x flexcan peripheral bridge interrupt request interrupt request i/o clocks instructions data voltage regulator nmi swt pit stm nmi siul . . . intc i 2 c . . . 8 x linflex 64 ch 29 ch 10-bit mpu cmu sram flash memory code flash 1.0 mb data flash 64 kb mc_pcu mc_me mc_cgm mc_rgm bam ctu rtc sscm (master) (master) (slave) (slave) (slave) controller controller legend: adc analog-to-digital converter bam boot assist module flexcan controller area network cflash code flash memory cmu clock monitor unit ctu cross triggering unit dflash data flash memory dspi deserial serial peripheral interface edma enhanced direct memory access emios enhanced modular input output system fmpll frequency-modulated phase-locked loop i 2 c inter-integrated circuit bus imux internal multiplexer intc interrupt controller jtag jtag controller linflex serial communication interface (lin support) mc_cgm clock generation module mc_me mode entry module mpu memory protection unit nmi non-maskable interrupt mc_pcu power control unit mc_rgm reset generation module pit periodic interrupt timer rtc real-time clock siul system integration unit lite sram static random-access memory sscm system status configuration module stm system timer module swt software watchdog timer wkpu wakeup unit mpu ecsm from peripheral registers blocks adc emios 19 ch 10-bit/12-bit adc (master) . . . . . . . . . wkpu 5 ch 12-bit adc edma interrupt request with wakeup functionality
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 34 freescale semiconductor table 2-2. MPC5606BK series block summary block function analog-to-digital converter (adc) converts analog voltages to digital values boot assist module (bam) a block of read-only memory containing vle code which is executed according to the boot mode of the device clock generation module (mc_cgm) provides logic and control required for the generation of system and peripheral clocks crossbar switch (xbar) supports simultaneous connections between three master ports and three slave ports. the crossbar supports a 32-bit address bus width and a 64-bit data bus width. cross triggering unit (ctu) enables syn chronization of adc conversions with a timer event from the emios or from the pit deserial serial peripheral interface (dspi) provides a synchronous serial interface for communication with external devices enhanced modular input output system (emios) provides the functionality to generate or measure events flash memory provides non-volatile storage for program code, constants and variables flexcan (controller area network) supports the standard can communications protocol frequency-modulated phase-locked loop (fmpll) generates high-speed system clocks and supports programmable frequency modulation internal multiplexer (imux) siu subblock allows flexible mapping of peripheral interface on the different pins of the device inter-integrated circuit (i 2 c?) bus a two wire bidirectional serial bus that provides a simple and efficient method of data exchange between devices interrupt controller (intc) provides priority-bas ed preemptive scheduling of interrupt requests jtag controller provides the means to test chip fu nctionality and connectivity while remaining transparent to system logic when not in test mode linflex controller manages a high number of lin (local interconnect network protocol) messages efficiently with a minimum of cpu load memory protection unit (mpu) provides hardware access control for all memory references generated in a device periodic interrupt timer (pit) produces periodic interrupts and triggers real-time counter (rtc) a free running counter used for time keeping applications, the rtc can be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low-power mode) reset generation module (mc_rgm) centralizes reset sources and manages the device reset sequence of the device static random-access memory (sram) provides storage for program code, constants, and variables system integration unit lite (siul) provides control over all the electrical pad controls and up 32 ports with 16 bits of bidirectional, general-purpose input and output signals and supports up to 32 external interrupts with trigger event configuration system timer module (stm) provides a set of output com pare events to support the automotive open system architecture (autosar) and operating system tasks
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 35 2.4 feature details 2.4.1 e200z0h core processor the e200z0h core includes the following features: ? high performance, e200z0h core processo r for managing peripherals and interrupts ? single issue 4-stage pipeli ned in-order execution, 32-bit power architecture cpu ? variable length encoding (vle), allowi ng mixed 16-bit and 32-bit instructions ? results in efficient code size footprint ? minimizes impact on performance ? branch processing acceleration us ing lookahead instruction buffer ? load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles ? 32-bit general purpose registers (gprs) ? separate instruction bus and load/store bus harvard architecture ? hardware vectored interrupt support ? multi-cycle divide word (divw) and load multiple word (lmw) store multiple word (smw) multiple class instructions, can be interrupted to prevent increases in interrupt latency 2.4.2 crossbar switch (xbar) the following summarizes the MPC5606BK?s implementation of the crossbar switch: ? three master ports: ? cpu instruction bus ? cpu load/store bus ?edma ? multiple bus slaves to enable access to flash memory, sram, and peripherals ? crossbar supports as many as two co nsecutive transfers at any one time ? 32-bit internal address bus , 32-bit internal data bus ? fixed priority arbitrat ion based on port master 2.4.3 interrupt controller (intc) the MPC5606BK implements an interrupt c ontroller that features the following: ? unique 9-bit vector for each of the 231 separate interrupt sources ? eight software trigge rable interrupt sources
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 36 freescale semiconductor ? 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source ? ability to modify the isr or task priority ? modifying the priority can be used to implemen t priority ceiling protocol for accessing shared resources ? external high priority interrupt directly accessing the main core critical interrupt mechanism 2.4.4 system integration unit lite (siul) the siul features the following: ? as many as four levels of internal pin mul tiplexing, allowing exceptional flexibility in the allocation of device functions for each package ? centralized general purpose input output (gpio) control of as many as 149 input/output pins (package dependent) ? all gpio pins independently configurab le to support pull-up pull down, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit wide ports ? all peripheral pins can be alte rnatively configured as both gene ral purpose input or output pins except adc channels which suppor t alternative configuration as general purpose inputs, with selected pins able to also support outputs ? direct readback of the pin value supported on all digita l output pins through the siul ? configurable digital input filter that can be applied to as many as 16 general purpose input pins for noise elimination on external interrupts ? register configuration protected ag ainst change with soft lock for temporary guard or hard lock to prevent modification until next reset ? support for two 32-bit virtual ports via the dspi serialization 2.4.5 flash memory the on-chip flash memory on the MPC5606BK features the following: ? as much as 1.0 mb burst flash memory ?4 ? 128-bit page buffers with pr ogrammable prefetch control ? typical flash-memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss at 64 mhz ? page buffers can be allocated for code-only, fixe d partitions of code a nd data, all available for any access ? 64-bit ecc with single-bit correction, double-bit detection for data integrity ? censorship protection scheme to prev ent flash-memory content visibility ? separate dedicated data flash memo ry (dflash) for eeprom emulation ? four erase sectors, each containing 16 kb of memory ? offers read-while-write functi onality from main program space
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 37 ? small block flash-memory arra ngement in main array to suppor t features such as boot block, operating system block ? hardware managed flash memory wr ites, erase and verify sequence ? flash-memory partitioning (see table 2-3 ) ? error correction status ? configurable error-correct ing codes (ecc) reporting for sram and flash memory ? supports optional reporting of single-bit errors ? protected mechanism for reporting of corrected ecc values ? error address recorded incl uding access type and master ? flash-memory ecc reporting regi sters mirrored into ecsm address space but data comes from the flash-memory module ? flash-memory module can be interrogate d to provide ecc bit error location ? margin read for flash-memory array s upported for initial program verification table 2-3. flash memory partitioning array address mpc5605b mpc5606b 768 mb 1 mb array_a flash_base + 0x0000_0000 32 kb 32 kb flash_base + 0x0000_8000 16 kb 16 kb flash_base + 0x0000_c000 16 kb 16 kb flash_base + 0x0001_0000 32 kb 32 kb flash_base + 0x0001_8000 32 kb 32 kb flash_base + 0x0002_0000 128 kb 128 kb flash_base + 0x0004_0000 128 kb 128 kb flash_base + 0x0006_0000 128 kb 128 kb array_b flash_base + 0x0008_0000 128 kb 128 kb flash_base + 0x000a_0000 128 kb 128 kb flash_base + 0x000c_0000 ? 128 kb flash_base + 0x000e_0000 ? 128 kb array_c flash_base + 0x0010_0000 ?? flash_base + 0x0012_0000 ?? flash_base + 0x0014_0000 ?? flash_base + 0x0016_0000 ??
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 38 freescale semiconductor 2.4.6 sram the on-chip sram on the MPC5606BK features the following: ? as much as 80 kb general purpose sram ? typical sram access time: 0 wait-s tate for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block ? 32-bit ecc with single-bit correction, double-bit detection for data integrity ? supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory ? user transparent ecc encoding and decoding for byte, half word, and word accesses ? separate internal power domain applied to 32 kb sram block or 8 kb sram block during standby modes to retain c ontents during low power mode 2.4.7 memory protection unit (mpu) the mpu provides the following features ? eight region descriptors for per-master protection ? start and end address defi ned with 32-byte granularity ? overlapping regions supported ? protection attributes can optionally include process id ? protection offered for threeconcurrent read ports ? read and write attri butes for all masters ? execute and supervisor/user mode attributes for processor masters 2.4.8 boot assist module (bam) the device implements a boot assist module (bam): ? block of read-only memory cont aining vle code which is executed according to boot mode of the device ? download of code into internal sram possible via flexcan or li nflex, afterwhich code can be executed array_d data flash block + 0x0000_0000 16 kb 16 kb data flash block + 0x0000_4000 16 kb 16 kb data flash block + 0x0000_8000 16 kb 16 kb data flash block + 0x0000_c000 16 kb 16 kb table 2-3. flash memory partitioning (continued) array address mpc5605b mpc5606b 768 mb 1 mb
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 39 2.4.9 enhanced modular input output system (emios) the MPC5606BK implements a scaled- down version of the emios module: ? as many as 64 timed i/o channels with 16-bit counter resolution ? buffered updates ? support for shifted pwm outputs to mini mize occurrence of concurrent edges ? supports configurable trigger out puts for adc conversion for sync hronization to channel output waveforms ? edge-aligned output pulse width modulation ? programmable pulse pe riod and duty cycle ? supports 0% and 100% duty cycle ? shared or independent time bases ? dma transfer support available table 2-4 shows the supported emios modes. table 2-5 shows the maximum emios channel allocation. table 2-4. supported emios channel modes mode channel type description name counter / opwm / icoc o(i)pwm / opwfmb / opwmcb / icoc o(i)pwm / icoc opwm / icoc double action output compare daoc ? general purpose input / output gpio input filter ipf input period measurement ipm ? input pulse width measurement ipwm ? modulus counter mc ? ? ? modulus counter buffered (up / down) mcb ? ? output pulse width and frequency modulation buffered opwfmb ? ? output pulse width modulation buffered opwmb ? center aligned output pwm buffered with dead time opwmcb ? ? ? output pulse width modulation trigger opwmt pulse edge accumulation pea ? ? ? pulse edge counting pec ? ? ? quadrature decode qdec ? ? ? single action input capture saic single action output compare saoc
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 40 freescale semiconductor 2.4.10 deserial serial periph eral interface module (dspi) the dspi features the following: ? as many as six dspi modules supported ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from 4 to 16 bits ? as many as six chip select lines available, de pending on package and pin multiplexing, to enable 64 external devices to be selected us ing external muxing from a single dspi ? as many as eight transfer types, independently configurable for each dspi using the clock and transfer attributes registers ? chip select strobe available as alternate functi on on one of the chip select pins for deglitching ? fifos for buffering as many as four tr ansfers on the transmit and receive side ? general purpose i/o functionality on pins when not used for spi ? queueing operation possible through use of edma ? 32-bit serialization of data enabli ng virtual gpio ports on 2 dspi modules 2.4.11 controller area network module (flexcan) the enhanced flexcan module features the following: ? as many as six flexcan modules supported table 2-5. emios configuration channel type maximum number of channels total emios_0 emios_1 counter / opwm / icoc 1 1 each channel supports a range of modes including modu lus counters, pwm generation, input capture, output compare. 5510 o(i)pwm / opwfmb / opwmcb / icoc 2 2 each channel supports a range of modes including pwm generation with dead time, input capture, output compare. 707 o(i)pwm / icoc 3 3 each channel supports a range of modes including pwm generation, input capture, output compare, period and pulse width measurement. 7714 opwm / icoc 4 4 each channel supports a range of modes including pwm generation, input capture, output compare. 13 20 33
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 41 ? compliant with can protocol specification, version 2.0b active ? 64 mailboxes per flexcan module ? mailboxes configurable while modul e remains synchronized to can bus ? each mailbox configurable as transmit or receive ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort proce dure and notification ? receive features ? individual programmable filters for each mailbox ? eight mailboxes configurable as a 6-entry receive fifo ? eight programmable acceptan ce filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter ? listen only mode capabilities ? can sampler available for connection to one of available can module pads ? supports capturing of first message identi fier while in stop or standby modes 2.4.12 system clocks and clock generation the following list summarizes the system clock and clock generation on the MPC5606BK: ? system clock can be derive d from the following sources ? external crystal oscillator ?fmpll ? 16 mhz fast internal rc oscillator ? programmable output clock di vider of system clock ( ? 1, ? 2, ? 4) ? separate programmable periphe ral bus clock divider ratio ( ? 1, ? 2, ? 4) applied to system clock ? frequency modulated phase-locked loop (fmpll) ? input clock frequency from 4 mhz to 16 mhz ? clock sources: external oscillat or or internal firc oscillator ? lock detect circuitry conti nuously monitors lock status ? loss of clock (loc) detection fo r reference and feedback clocks ? on-chip loop filter ? improves electromagnetic interference performance ? reduces number of exte rnal components required ? on-chip fast external crystal os cillator supporting 4 mhz to 16 mhz
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 42 freescale semiconductor ? dedicated 16 mhz fast internal rc oscillator ? used as default clock source out of reset ? provides clock for rapid st artup from low power modes ? provides back-up clock in the event of fm pll or external oscillator clock failure ? offers independent clock source for the watchdog timer ? 5% accuracy over the operating temperature range ? trimming registers to support frequency ad justment with in-appl ication calibration ? dedicated 128 khz slow internal rc oscillator for low power mode operation and self wakeup ? 5% accuracy ? trimming registers to s upport improve accuracy with in-application calibration ? 32-khz low power external oscillat or for low power real time clock 2.4.13 system timers the system timers include: ? peripheral interrupt timer (pit ) timers (including adc trigger) ? one real-time counter (rtc) timer the pit is an array of timers that can be used to raise interrupts, trigger ctu channels and adc conversions. the rtc supports wakeup from low power modes or real-t ime clock generation. 2.4.13.1 periodic interrupt timer module (pit) the pit features the following: ? eight general purpose interrupt timers ? as many as two interrupt timers for triggering ad c injected conversions (one for 10-bit adc, one for 12-bit adc) ? as many as four interrupt time rs for triggering dma transfers ? as many as two interrupt timers for triggering ctu ? 32-bit counter resolution ? clocked by system clock frequency 2.4.13.2 real-time counter (rtc) the rtc features the following: ? configurable resolution for different timeout periods ? 1 sec resolution for > 1 hour period ? 1 ms resolution for 2 second period ? selectable clock sources ? 128 khz slow internal rc oscillator ? divided 16 mhz fast internal rc oscillator
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 43 ? external 32 khz crystal ? supports continued operation through all resets except por (power-on reset) 2.4.14 system watchdog timer the watchdog on the MPC5606BK features the following: ? activation by software or out of reset ? 32-bit modulus counter ? clock source: robust 128 khz slow internal rc oscillator (divisible by 1 to 32) ? supports normal or windowed mode ? configurable response on timeout: reset, in terrupt, or interrupt followed by reset ? reset by writing a software key to memory mapped register ? support for protected access to watchdog control registers with optional soft and hard locks ? soft lock allows temporar y locking of configuration ? once enabled, hard lock prevents any changes until after a reset ? supports halting duri ng low power modes 2.4.15 inter-integrated circuit (i 2 c) module the i 2 c module features the following: ? one i 2 c module supported ? 2-wire bidirectional serial bus for on-board communications ? compatibility with i 2 c bus standard ? multimaster operation ? software-programmable for one of 256 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus-busy detection 2.4.16 on-chip voltage regulator (vreg) the on-chip voltage regulator in cludes the following features: ? regulates 3.3 or 5 v 10% input to generate all internal supplies for internal control ? manages power gating
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 44 freescale semiconductor ? low power regulators support operation when in stop and standby modes to minimize power consumption ? fast startup on-chip regulators for rapid exit from low power modes ? low voltage reset supporte d on all internal supplies 2.4.17 analog-to-digital converter (adc) the adc features the following: ? two adc modules, one 10-bit resolution and one 12-bit resolution supporting synchronous conversions on channels ? 0?v dd common mode conversion range ? independent reference supplies for each adc ? conversions times of < 1 s available ? as many as 53 single ended inputs channels, expandable to 81 channe ls with external multiplexers ? as many as 19 shared channels, among which, 16 called anp are mapped on dedicated pins, not multiplexed with any other functionality, in orde r to improve the accur acy. all other channels, called ans or anx are multiple xed with other functionalities. ? as many as 19 channels shared between 10-bit and 12-bit adcs ? as many as five dedicated 12-bit adc channels ? as many as 29 dedicated 10-bit adc channels ? externally multiplexed channels ? internal control to support generation of external analog multiplexor selection ? four internal channels optio nally used to support externally multiplex inputs, providing transparent control for additional adc channels ? each of the three channels supports as many as eight externally muxed inputs ? individual dedicated result register also avai lable for externally muxed conversion channels ? three independently configurable sample and conversion times for hi gh occurrence channels, internally muxed channels and externally muxed channels ? configurable right-aligned or left-aligned result formats ? support for one-shot, scan and injection conversion modes ? independently configurable parameters for channels: ?offset refresh ? sampling ? conversion triggering support ? internal conversion triggering from periodic interrupt time r (pit) or timed i/o module (emios) through cross tr iggering unit (ctu) ? internal conversion triggering from periodic interrupt timer (pit) ? one input pin configurable as external conversion trigger source
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 45 ? as many as six configurable analog comparator channels offering range co mparison with triggered alarm ? greater than ?less than ? out of range ? all unused analog pins availa ble as general purpose input pins ? unused 10-bit adc analog pins, with the excepti on of the 19 dedicated high accuracy channels, available as general purpose output pins ? power-down mode ? supports dma transfer of results based on en d of conversion chain or each conversion ? separate dedicated dma request for injection mode 2.4.18 enhanced direct memory access controller (edma) the following summarizes the MPC5606BK?s implementation of th e edma controller: ? 16 channels to support independent 8-, 16-, or 32-bit single value or block transfers ? support of variable sized queues and circular queues ? source and destination address registers independent ly configured to post-increment or remain constant ? each transfer initiated by peripheral, cpu, pe riodic timer interrupt, or edma channel request ? peripheral dma request sour ces possible from spis, i 2 c, 10-bit adc, 12-bit adc, emios, and gpios ? each edma channel able to optionally send interrupt request to cpu on completion of single value or block transfer ? dma transfers possible between system memori es and all accessible me mory mapped locations including peripheral and registers ? programmable dma channel mux allows assignment of any dma source to any available dma channel with as many as 64 potential request sources 2.4.19 cross trigger unit (ctu) the ctu enables the synchronization of adc conversi ons with a timer event. its key features are: ? single cycle delayed trigger outpu t; trigger output is a combination of 64 (generic value) input flags/events connected to different timers in the system ? triggers adc conversions from any emios channel ? triggers adc conversions from as many as two dedicated pits ? maskable interrupt generation whenev er a trigger output is generated ? one event configuration register dedicated to each timer event allows to define the corresponding adc channel ? acknowledgment signal to emio s/pit for clearing the flag
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 46 freescale semiconductor ? synchronization with adc to avoid collision 2.4.20 serial communication interface module (linflex) the linflex on the MPC5606BK features the following: ? as many as eight linflex modules supported ? supports lin master mode, lin slave mode and uart mode ? dma connected on linflex_0 and linflex_1 ? linflex_0 supporting lin master and slave mode; linflex_1 to linfle x_7 modules supporting lin master mode ? lin state machine compliant to lin 1.3, 2.0 and 2.1 specifications ? handles lin frame transmission and reception without cpu intervention ? lin features ? autonomous lin frame handling ? message buffer to store iden tified and up to 8 data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back; self test; lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? 16 identifiers filters for disc arding irrelevant lin frames ? uart mode ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-bytes receive, 4-bytes transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation with four interrupt sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud rate modul us counter and 16-bit fractional
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 47 ? two receiver wakeup methods MPC5606BK devices include two f unctionally-different linflex c ontroller types. these are distinguished in the documentation by the abbreviati ons ?linflex? and ?linflexd?. the latter name represents the dma support available on this cont roller type. the MPC5606BK devices combine these two types to provide as many as eight modules supporting the linflex protocol. table 2-6 shows the module (instance) numbers and the co rresponding functional controller type. 2.4.21 jtag controller (jtagc) jtag features the following: ? jtag low pin count interface (ieee 1 149.1) test access port (tap) interface ? backward compatible to standard jtag ie ee 1149.1-2001 test access port (tap) interface ? supports boundary scan testing ? all jtag pins reusable in application as standard ios 2.5 developer support the MPC5606BK mcu tools and third-party developers are similar to those used for the freescale mpc5500 product family, offering a widespread, esta blished network of tool and software vendors. the following development support will be available: ? automotive evaluation boards (evb) feat uring can, lin interfaces, and more ? compilers ? debuggers ? jtag interface the following software support will be available: ? osek solutions will be availabl e from multiple third parties ? can and lin drivers ? autosar package table 2-6. linflex numbering and naming module numbers module version 0 and 1 linflexd 2?7 linflex
chapter 2 introduction MPC5606BK microcontroller reference manual, rev. 2 48 freescale semiconductor this page is intent ionally left blank.
chapter 3 memory map MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 49 chapter 3 memory map table 3-1 shows the memory map for th e MPC5606BK. all addresses on th e device, including those that are reserved, are identified in the table. the addresses represent the physical addresses as signed to each ip block. table 3-1. MPC5606BK memory map start address end address size (kb) region name 0x0000_0000 0x0000_7fff 32 code flash memory array 0 0x0000_8000 0x0000_bfff 16 code flash memory array 0 0x0000_c000 0x0000_ffff 16 code flash memory array 0 0x0001_0000 0x0001_7fff 32 code flash memory array 0 0x0001_8000 0x0001_ffff 32 code flash memory array 0 0x0002_0000 0x0003_ffff 128 code flash memory array 0 0x0004_0000 0x0005_ffff 128 code flash memory array 0 0x0006_0000 0x0007_ffff 128 code flash memory array 0 0x0008_0000 0x0009_ffff 128 code flash memory array 0 0x000a_0000 0x000b_ffff 128 code flash memory array 0 0x000c_0000 0x000d_ffff 128 code flash memory array 0 0x000e_0000 0x000f_ffff 128 code flash memory array 0 0x0010_0000 0x001f_ffff 1024 reserved 0x0020_0000 0x0020_3fff 16 flash memory shadow array 0x0020_4000 0x003f_ffff 2032 reserved 0x0040_0000 0x0040_3fff 16 code flash memory array 0 test sector 0x0040_4000 0x007f_ffff 4080 reserved 0x0080_0000 0x0080_3fff 16 data flash memory array 0 0x0080_4000 0x0080_7fff 16 data flash memory array 0 0x0080_8000 0x0080_bfff 16 data flash memory array 0 0x0080_c000 0x0080_ffff 16 data flash memory array 0 0x0081__0000 0x00bf_ffff 4032 reserved 0x00c0_0000 0x00c0_3fff 16 data flash memory array 0 test sector 0x00c0_4000 0x00ff_ffff 4080 reserved 0x0100_0000 0x1fff_ffff 507904 flash memory emulation mapping 0x2000_0000 0x3fff_ffff 524288 reserved 0x4000_0000 0x4001_3fff 80 sram
chapter 3 memory map MPC5606BK microcontroller reference manual, rev. 2 50 freescale semiconductor 0x4001_4000 0xbfff_ffff 2097072 reserved off-platform peripherals 0xc000_0000 0xc3f8_7fff 65056 reserved 0xc3f8_8000 0xc3f8_bfff 16 code flash memory 0 configuration 0xc3f8_c000 0xc3f8_ffff 16 data fl ash memory 0 configuration 0xc3f9_0000 0xc3f9_3fff 16 siul 0xc3f9_4000 0xc3f9_7fff 16 wkpu 0xc3f9_8000 0xc3f9_ffff 32 reserved 0xc3fa_0000 0xc3fa_3fff 16 emios_0 0xc3fa_4000 0xc3fa_7fff 16 emios_1 0xc3fa_8000 0xc3fd_7fff 192 reserved 0xc3fd_8000 0xc3fd_bfff 16 sscm 0xc3fd_c000 0xc3fd_ffff 16 mc_me 0xc3fe_0000 0xc3fe_3fff 16 mc_cgm 0xc3fe_4000 0xc3fe_7fff 16 mc_rgm 0xc3fe_8000 0xc3fe_bfff 16 mc_pcu 0xc3fe_c000 0xc3fe_ffff 16 rtc/api 0xc3ff_0000 0xc3ff_3fff 16 pit 0xc3ff_4000 0xffdf_ffff 981040 reserved 0xffe0_0000 0xffe0_3fff 16 adc_0 0xffe0_4000 0xffe0_7fff 16 adc_1 0xffe0_8000 0xffe2_ffff 160 reserved 0xffe3_0000 0xffe3_3fff 16 i2c_0 0xffe3_4000 0xffe3_ffff 48 reserved 0xffe4_0000 0xffe4_3fff 16 linflex_0 0xffe4_4000 0xffe4_7fff 16 linflex_1 0xffe4_8000 0xffe4_bfff 16 linflex_2 0xffe4_c000 0xffe4_ffff 16 linflex_3 0xffe5_0000 0xffe5_3fff 16 linflex_4 0xffe5_4000 0xffe5_7fff 16 linflex_5 0xffe5_8000 0xffe5_bfff 16 linflex_6 0xffe5_c000 0xffe5_ffff 16 linflex_7 0xffe6_0000 0xffe6_3fff 16 reserved table 3-1. MPC5606BK memory map (continued) start address end address size (kb) region name
chapter 3 memory map MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 51 0xffe6_4000 0xffe6_7fff 16 ctu 0xffe6_8000 0xffe6_ffff 32 reserved 0xffe7_0000 0xffe7_3fff 16 can sampler 0xffe7_4000 0xffe7_ffff 48 reserved 0xffe8_0000 0xffef_ffff 512 mirrored range 0x3f80000?0xc3ffffff 0xfff0_0000 0xfff0_ffff 64 reserved 0xfff1_0000 0xfff1_3fff 16 mpu 0xfff1_4000 0xfff3_7fff 144 reserved 0xfff3_8000 0xfff3_bfff 16 swt 0xfff3_c000 0xfff3_ffff 16 stm 0xfff4_0000 0xfff4_3fff 16 ecsm 0xfff4_4000 0xfff4_7fff 16 edma 0xfff4_8000 0xfff4_bfff 16 intc 0xfff4_c000 0xfff8_ffff 272 reserved 0xfff9_0000 0xfff9_3fff 16 dspi_0 0xfff9_4000 0xfff9_7fff 16 dspi_1 0xfff9_8000 0xfff9_bfff 16 dspi_2 0xfff9_c000 0xfff9_ffff 16 dspi_3 0xfffa_0000 0xfffa_3fff 16 dspi_4 0xfffa_4000 0xfffa_7fff 16 dspi_5 0xfffa_8000 0xfffb_ffff 96 reserved 0xfffc_0000 0xfffc_3fff 16 flexcan_0 0xfffc_4000 0xfffc_7fff 16 flexcan_1 0xfffc_8000 0xfffc_bfff 16 flexcan_2 0xfffc_c000 0xfffc_ffff 16 flexcan_3 0xfffd_0000 0xfffd_3fff 16 flexcan_4 0xfffd_4000 0xfffd_7fff 16 flexcan_5 0xfffd_8000 0xfffd_bfff 16 reserved 0xfffd_c000 0xfffd_ffff 16 dma_mux 0xfffe_0000 0xffff_bfff 144 reserved 0xffff_c000 0xffff_ffff 16 bam table 3-1. MPC5606BK memory map (continued) start address end address size (kb) region name
chapter 3 memory map MPC5606BK microcontroller reference manual, rev. 2 52 freescale semiconductor this page is intent ionally left blank.
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 53 chapter 4 signal description 4.1 package pinouts figure 4-1 , figure 4-2 , and figure 4-3 show the location of the signals on the available packages for this device. for more information on pin multiplexing on this chip, see table 4-1 . figure 4-1. 100-pin lqfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 pb[3] pc[9] pc[14] pc[15] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pc[11] pc[10] pb[0] pb[1] pc[6] pa [ 1 1 ] pa [ 1 0 ] pa [ 9 ] pa [ 8 ] pa [ 7 ] vdd_hv vss_hv pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] vdd_hv_adc1 vss_hv_adc1 pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pc[7] pa [ 1 5 ] pa [ 1 4 ] pa [ 4 ] pa [ 1 3 ] pa [ 1 2 ] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pe[12] 100 lqfp top view
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 54 freescale semiconductor figure 4-2. 144-pin lqfp pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 pb[3] pc[9] pc[14] pc[15] pg[5] pg[4] pg[3] pg[2] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] pa[11] pa[10] pa [ 9 ] pa [ 8 ] pa [ 7 ] pe[13] pf[14] pf[15] vdd_hv vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa [ 3 ] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] vdd_hv_adc1 vss_hv_adc1 pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pc[7] pf[10] pf[11] pa [ 1 5 ] pf[13] pa [ 1 4 ] pa [ 4 ] pa [ 1 3 ] pa [ 1 2 ] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] 144 lqfp top view
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 55 figure 4-3. 176-pin lqfp pinout 4.2 pin muxing table 4-1 defines the pin list and muxing for this device. each entry of table 4-1 shows all the possible confi gurations for each pin, via the alternate functions. the default function assigned to each pi n after reset is indicated by af0. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 pa [ 1 1 ] pa [ 1 0 ] pa [ 9 ] pa [ 8 ] pa [ 7 ] pe[13] pf[14] pf[15] vdd_hv vss_hv pg[0] pg[1] ph[3] ph[2] ph[1] ph[0] pg[12] pg[13] pa [ 3 ] pi[13] pi[12] pi[11] pi[10] pi[9] pi[8] pb[15] pd[15] pb[14] pd[14] pb[13] pd[13] pb[12] pd[12] vdd_hv_adc1 vss_hv_adc1 pb[11] pd[11] pd[10] pd[9] pb[7] pb[6] pb[5] vdd_hv_adc0 vss_hv_adc0 pb[3] pc[9] pc[14] pc[15] pj[4] vdd_hv vss_hv ph[15] ph[13] ph[14] pi[6] pi[7] pg[5] pg[4] pg[3] pg[2] pa [ 2 ] pe[0] pa [ 1 ] pe[1] pe[8] pe[9] pe[10] pa [ 0 ] pe[11] vss_hv vdd_hv vss_hv reset vss_lv vdd_lv vdd_bv pg[9] pg[8] pc[11] pc[10] pg[7] pg[6] pb[0] pb[1] pf[9] pf[8] pf[12] pc[6] pc[7] pf[10] pf[11] pa[15] pf[13] pa[14] pa [ 4 ] pa[13] pa[12] vdd_lv vss_lv xtal vss_hv extal vdd_hv pb[9] pb[8] pb[10] pf[0] pf[1] pf[2] pf[3] pf[4] pf[5] pf[6] pf[7] pj[3] pj[2] pj[1] pj[0] pi[15] pi[14] pd[0] pd[1] pd[2] pd[3] pd[4] pd[5] pd[6] pd[7] vdd_hv vss_hv pd[8] pb[4] pb[2] pc[8] pc[13] pc[12] pi[0] pi[1] pi[2] pi[3] pe[7] pe[6] ph[8] ph[7] ph[6] ph[5] ph[4] pe[5] pe[4] pc[4] pc[5] pe[3] pe[2] ph[9] pc[0] vss_lv vdd_lv vdd_hv vss_hv pc[1] ph[10] pa [ 6 ] pa [ 5 ] pc[2] pc[3] pi[4] pi[5] ph[12] ph[11] pg[11] pg[10] pe[15] pe[14] pg[15] pg[14] pe[12] 176 lqfp top view
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 56 freescale semiconductor table 4-1. functional port pins port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp port a pa[0] pcr[0] af0 af1 af2 af3 ? gpio[0] e0uc[0] clkout e0uc[13] wkup[19] 4 siul emios_0 mc_cgm emios_0 wkup i/o i/o o i/o i mtristate121624 pa[1] pcr[1] af0 af1 af2 af3 ? gpio[1] e0uc[1] nmi 5 ? wkup[2] (4) siul emios_0 wkup ? wkup i/o i/o i ? i s tristate 7 11 19 pa[2] pcr[2] af0 af1 af2 af3 ? gpio[2] e0uc[2] ? ma[2] wkup[3] (4) siul emios_0 ? adc_0 wkup i/o i/o ? o i s tristate 5 9 17 pa[3] pcr[3] af0 af1 af2 af3 ? ? gpio[3] e0uc[3] lin5tx cs4_1 eirq[0] adc1_s[0] siul emios_0 linflex_5 dspi_1 siul adc_1 i/o i/o o o i i j tristate 68 90 114 pa[4] pcr[4] af0 af1 af2 af3 ? ? gpio[4] e0uc[4] ? cs0_1 lin5rx wkup[9] (4) siul emios_0 ? dspi_1 linflex_5 wkup i/o i/o ? i/o i i stristate294351 pa[5] pcr[5] af0 af1 af2 af3 gpio[5] e0uc[5] lin4tx ? siul emios_0 linflex_4 ? i/o i/o o ? m tristate 79 118 146 pa[6] pcr[6] af0 af1 af2 af3 ? ? gpio[6] e0uc[6] ? cs1_1 eirq[1] lin4rx siul emios_0 ? dspi_1 siul linflex_4 i/o i/o ? o i i s tristate 80 119 147 pa[7] pcr[7] af0 af1 af2 af3 ? ? gpio[7] e0uc[7] lin3tx ? eirq[2] adc1_s[1] siul emios_0 linflex_3 ? siul adc_1 i/o i/o o ? i i j tristate 71 104 128
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 57 pa[8] pcr[8] af0 af1 af2 af3 ? n/a 6 ? gpio[8] e0uc[8] e0uc[14] ? eirq[3] abs[0] lin3rx siul emios_0 emios_0 ? siul bam linflex_3 i/o i/o i/o ? i i i s input, weak pull-up 72 105 129 pa[9] pcr[9] af0 af1 af2 af3 n/a 6 gpio[9] e0uc[9] ? cs2_1 fab siul emios_0 ? dspi_1 bam i/o i/o ? o i s pull- down 73 106 130 pa[10] pcr[10] af0 af1 af2 af3 ? gpio[10] e0uc[10] sda lin2tx adc1_s[2] siul emios_0 i 2 c_0 linflex_2 adc_1 i/o i/o i/o o i j tristate 74 107 131 pa[11] pcr[11] af0 af1 af2 af3 ? ? ? gpio[11] e0uc[11] scl ? eirq[16] lin2rx adc1_s[3] siul emios_0 i 2 c_0 ? siul linflex_2 adc_1 i/o i/o i/o ? i i i j tristate 75 108 132 pa[12] pcr[12] af0 af1 af2 af3 ? ? gpio[12] ? e0uc[28] cs3_1 eirq[17] sin_0 siul ? emios_0 dspi_1 siul dspi_0 i/o ? i/o o i i stristate314553 pa[13] pcr[13] af0 af1 af2 af3 gpio[13] sout_0 e0uc[29] ? siul dspi_0 emios_0 ? i/o o i/o ? mtristate304452 pa[14] pcr[14] af0 af1 af2 af3 ? gpio[14] sck_0 cs0_0 e0uc[0] eirq[4] siul dspi_0 dspi_0 emios_0 siul i/o i/o i/o i/o i mtristate284250 pa[15] pcr[15] af0 af1 af2 af3 ? gpio[15] cs0_0 sck_0 e0uc[1] wkup[10] (4) siul dspi_0 dspi_0 emios_0 wkup i/o i/o i/o i/o i mtristate274048 port b table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 58 freescale semiconductor pb[0] pcr[16] af0 af1 af2 af3 gpio[16] can0tx e0uc[30] lin0tx siul flexcan_0 emios_0 linflex_0 i/o o i/o o mtristate233139 pb[1] pcr[17] af0 af1 af2 af3 ? ? ? gpio[17] ? e0uc[31] ? wkup[4] (4) can0rx lin0rx siul ? emios_0 ? wkup flexcan_0 linflex_0 i/o ? i/o ? i i i stristate243240 pb[2] pcr[18] af0 af1 af2 af3 gpio[18] lin0tx sda e0uc[30] siul linflex_0 i 2 c_0 emios_0 i/o o i/o i/o m tristate 100 144 176 pb[3] pcr[19] af0 af1 af2 af3 ? ? gpio[19] e0uc[31] scl ? wkup[11] (4) lin0rx siul emios_0 i 2 c_0 ? wkup linflex_0 i/o i/o i/o ? i i stristate111 pb[4] pcr[20] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[0] adc1_p[0] gpio[20] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate507288 pb[5] pcr[21] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[1] adc1_p[1] gpio[21] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate537591 pb[6] pcr[22] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[2] adc1_p[2] gpio[22] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate547692 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 59 pb[7] pcr[23] af0 af1 af2 af3 ? ? ? ? ? ? ? adc0_p[3] adc1_p[3] gpio[23] ? ? ? ? adc_0 adc_1 siul ? ? ? ? i i i itristate557793 pb[8] pcr[24] af0 af1 af2 af3 ? ? ? ? gpio[24] ? ? ? osc32k_xtal 7 wkup[25] adc0_s[0] adc1_s[4] siul ? ? ? osc32k wkup adc_0 adc_1 i ? ? ? ? i i i i ? 39 53 61 pb[9] pcr[25] af0 af1 af2 af3 ? ? ? ? gpio[25] ? ? ? osc32k_extal 7 wkup[26] adc0_s[1] adc1_s[5] siul ? ? ? osc32k wkup adc_0 adc_1 i ? ? ? ? i i i i ? 38 52 60 pb[10] pcr[26] af0 af1 af2 af3 ? ? ? gpio[26] ? ? ? wkup[8] 4 adc0_s[2] adc1_s[6] siul ? ? ? wkup adc_0 adc_1 i/o ? ? ? i i i jtristate405462 pb[11] pcr[27] af0 af1 af2 af3 ? gpio[27] e0uc[3] ? cs0_0 adc0_s[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? i/o i j tristate ? ? 97 pb[12] pcr[28] af0 af1 af2 af3 ? gpio[28] e0uc[4] ? cs1_0 adc0_x[0] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 61 83 101 pb[13] pcr[29] af0 af1 af2 af3 ? gpio[29] e0uc[5] ? cs2_0 adc0_x[1] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 63 85 103 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 60 freescale semiconductor pb[14] pcr[30] af0 af1 af2 af3 ? gpio[30] e0uc[6] ? cs3_0 adc0_x[2] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 65 87 105 pb[15] pcr[31] af0 af1 af2 af3 ? gpio[31] e0uc[7] ? cs4_0 adc0_x[3] siul emios_0 ? dspi_0 adc_0 i/o i/o ? o i j tristate 67 89 107 port c pc[0] 8 pcr[32] af0 af1 af2 af3 gpio[32] ? tdi ? siul ? jtagc ? i/o ? i ? m input, weak pull-up 87 126 154 pc[1] 8 pcr[33] af0 af1 af2 af3 gpio[33] ? tdo ? siul ? jtagc ? i/o ? o ? f 9 tristate 82 121 149 pc[2] pcr[34] af0 af1 af2 af3 ? gpio[34] sck_1 can4tx debug[0] eirq[5] siul dspi_1 flexcan_4 sscm siul i/o i/o o o i m tristate 78 117 145 pc[3] pcr[35] af0 af1 af2 af3 ? ? ? gpio[35] cs0_1 ma[0] debug[1] eirq[6] can1rx can4rx siul dspi_1 adc_0 sscm siul flexcan_1 flexcan_4 i/o i/o o o i i i s tristate 77 116 144 pc[4] pcr[36] af0 af1 af2 af3 ? ? ? gpio[36] e1uc[31] ? debug[2] eirq[18] sin_1 can3rx siul emios_1 ? sscm siul dspi_1 flexcan_3 i/o i/o ? o i i i m tristate 92 131 159 pc[5] pcr[37] af0 af1 af2 af3 ? gpio[37] sout_1 can3tx debug[3] eirq[7] siul dspi_1 flexcan_3 sscm siul i/o o o o i m tristate 91 130 158 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 61 pc[6] pcr[38] af0 af1 af2 af3 gpio[38] lin1tx e1uc[28] debug[4] siul linflex_1 emios_1 sscm i/o o i/o o stristate253644 pc[7] pcr[39] af0 af1 af2 af3 ? ? gpio[39] ? e1uc[29] debug[5] lin1rx wkup[12] (4) siul ? emios_1 sscm linflex_1 wkup i/o ? i/o o i i stristate263745 pc[8] pcr[40] af0 af1 af2 af3 gpio[40] lin2tx e0uc[3] debug[6] siul linflex_2 emios_0 sscm i/o o i/o o s tristate 99 143 175 pc[9] pcr[41] af0 af1 af2 af3 ? ? gpio[41] ? e0uc[7] debug[7] wkup[13] (4) lin2rx siul ? emios_0 sscm wkup linflex_2 i/o ? i/o o i i stristate222 pc[10] pcr[42] af0 af1 af2 af3 gpio[42] can1tx can4tx ma[1] siul flexcan_1 flexcan_4 adc_0 i/o o o o mtristate222836 pc[11] pcr[43] af0 af1 af2 af3 ? ? ? gpio[43] ? ? ma[2] wkup[5] (4) can1rx can4rx siul ? ? adc_0 wkup flexcan_1 flexcan_4 i/o ? ? o i i i stristate212735 pc[12] pcr[44] af0 af1 af2 af3 ? ? gpio[44] e0uc[12] ? ? eirq[19] sin_2 siul emios_0 ? ? siul dspi_2 i/o i/o ? ? i i m tristate 97 141 173 pc[13] pcr[45] af0 af1 af2 af3 gpio[45] e0uc[13] sout_2 ? siul emios_0 dspi_2 ? i/o i/o o ? s tristate 98 142 174 pc[14] pcr[46] af0 af1 af2 af3 ? gpio[46] e0uc[14] sck_2 ? eirq[8] siul emios_0 dspi_2 ? siul i/o i/o i/o ? i stristate333 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 62 freescale semiconductor pc[15] pcr[47] af0 af1 af2 af3 ? gpio[47] e0uc[15] cs0_2 ? eirq[20] siul emios_0 dspi_2 ? siul i/o i/o i/o ? i mtristate444 port d pd[0] pcr[48] af0 af1 af2 af3 ? ? ? gpio[48] ? ? ? wkup[27] adc0_p[4] adc1_p[4] siul ? ? ? wkup adc_0 adc_1 i ? ? ? i i i itristate416377 pd[1] pcr[49] af0 af1 af2 af3 ? ? ? gpio[49] ? ? ? wkup[28] adc0_p[5] adc1_p[5] siul ? ? ? wkup adc_0 adc_1 i ? ? ? i i i itristate426478 pd[2] pcr[50] af0 af1 af2 af3 ? ? gpio[50] ? ? ? adc0_p[6] adc1_p[6] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate436579 pd[3] pcr[51] af0 af1 af2 af3 ? ? gpio[51] ? ? ? adc0_p[7] adc1_p[7] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate446680 pd[4] pcr[52] af0 af1 af2 af3 ? ? gpio[52] ? ? ? adc0_p[8] adc1_p[8] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate456781 pd[5] pcr[53] af0 af1 af2 af3 ? ? gpio[53] ? ? ? adc0_p[9] adc1_p[9] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate466882 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 63 pd[6] pcr[54] af0 af1 af2 af3 ? ? gpio[54] ? ? ? adc0_p[10] adc1_p[10] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate476983 pd[7] pcr[55] af0 af1 af2 af3 ? ? gpio[55] ? ? ? adc0_p[11] adc1_p[11] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate487084 pd[8] pcr[56] af0 af1 af2 af3 ? ? gpio[56] ? ? ? adc0_p[12] adc1_p[12] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate497187 pd[9] pcr[57] af0 af1 af2 af3 ? ? gpio[57] ? ? ? adc0_p[13] adc1_p[13] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate567894 pd[10] pcr[58] af0 af1 af2 af3 ? ? gpio[58] ? ? ? adc0_p[14] adc1_p[14] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate577995 pd[11] pcr[59] af0 af1 af2 af3 ? ? gpio[59] ? ? ? adc0_p[15] adc1_p[15] siul ? ? ? adc_0 adc_1 i ? ? ? i i itristate588096 pd[12] pcr[60] af0 af1 af2 af3 ? gpio[60] cs5_0 e0uc[24] ? adc0_s[4] siul dspi_0 emios_0 ? adc_0 i/o o i/o ? i j tristate ? ? 100 pd[13] pcr[61] af0 af1 af2 af3 ? gpio[61] cs0_1 e0uc[25] ? adc0_s[5] siul dspi_1 emios_0 ? adc_0 i/o i/o i/o ? i j tristate 62 84 102 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 64 freescale semiconductor pd[14] pcr[62] af0 af1 af2 af3 ? gpio[62] cs1_1 e0uc[26] ? adc0_s[6] siul dspi_1 emios_0 ? adc_0 i/o o i/o ? i j tristate 64 86 104 pd[15] pcr[63] af0 af1 af2 af3 ? gpio[63] cs2_1 e0uc[27] ? adc0_s[7] siul dspi_1 emios_0 ? adc_0 i/o o i/o ? i j tristate 66 88 106 port e pe[0] pcr[64] af0 af1 af2 af3 ? ? gpio[64] e0uc[16] ? ? wkup[6] (4) can5rx siul emios_0 ? ? wkup flexcan_5 i/o i/o ? ? i i s tristate 6 10 18 pe[1] pcr[65] af0 af1 af2 af3 gpio[65] e0uc[17] can5tx ? siul emios_0 flexcan_5 ? i/o i/o o ? m tristate 8 12 20 pe[2] pcr[66] af0 af1 af2 af3 ? ? gpio[66] e0uc[18] ? ? eirq[21] sin_1 siul emios_0 ? ? siul dspi_1 i/o i/o ? ? i i m tristate 89 128 156 pe[3] pcr[67] af0 af1 af2 af3 gpio[67] e0uc[19] sout_1 ? siul emios_0 dspi_1 ? i/o i/o o ? m tristate 90 129 157 pe[4] pcr[68] af0 af1 af2 af3 ? gpio[68] e0uc[20] sck_1 ? eirq[9] siul emios_0 dspi_1 ? siul i/o i/o i/o ? i m tristate 93 132 160 pe[5] pcr[69] af0 af1 af2 af3 gpio[69] e0uc[21] cs0_1 ma[2] siul emios_0 dspi_1 adc_0 i/o i/o i/o o m tristate 94 133 161 pe[6] pcr[70] af0 af1 af2 af3 ? gpio[70] e0uc[22] cs3_0 ma[1] eirq[22] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m tristate 95 139 167 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 65 pe[7] pcr[71] af0 af1 af2 af3 ? gpio[71] e0uc[23] cs2_0 ma[0] eirq[23] siul emios_0 dspi_0 adc_0 siul i/o i/o o o i m tristate 96 140 168 pe[8] pcr[72] af0 af1 af2 af3 gpio[72] can2tx e0uc[22] can3tx siul flexcan_2 emios_0 flexcan_3 i/o o i/o o m tristate 9 13 21 pe[9] pcr[73] af0 af1 af2 af3 ? ? ? gpio[73] ? e0uc[23] ? wkup[7] (4) can2rx can3rx siul ? emios_0 ? wkup flexcan_2 flexcan_3 i/o ? i/o ? i i i stristate101422 pe[10] pcr[74] af0 af1 af2 af3 ? gpio[74] lin3tx cs3_1 e1uc[30] eirq[10] siul linflex_3 dspi_1 emios_1 siul i/o o o i/o i stristate111523 pe[11] pcr[75] af0 af1 af2 af3 ? ? gpio[75] e0uc[24] cs4_1 ? lin3rx wkup[14] (4) siul emios_0 dspi_1 ? linflex_3 wkup i/o i/o o ? i i stristate131725 pe[12] pcr[76] af0 af1 af2 af3 ? ? ? gpio[76] ? e1uc[19] 10 ? eirq[11] sin_2 adc1_s[7] siul ? emios_1 ? siul dspi_2 adc_1 i/o ? i/o ? i i i j tristate 76 109 133 pe[13] pcr[77] af0 af1 af2 af3 gpio[77] sout_2 e1uc[20] ? siul dspi_2 emios_1 ? i/o o i/o ? s tristate ? 103 127 pe[14] pcr[78] af0 af1 af2 af3 ? gpio[78] sck_2 e1uc[21] ? eirq[12] siul dspi_2 emios_1 ? siul i/o i/o i/o ? i s tristate ? 112 136 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 66 freescale semiconductor pe[15] pcr[79] af0 af1 af2 af3 gpio[79] cs0_2 e1uc[22] ? siul dspi_2 emios_1 ? i/o i/o i/o ? m tristate ? 113 137 port f pf[0] pcr[80] af0 af1 af2 af3 ? gpio[80] e0uc[10] cs3_1 ? adc0_s[8] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i j tristate ? 55 63 pf[1] pcr[81] af0 af1 af2 af3 ? gpio[81] e0uc[11] cs4_1 ? adc0_s[9] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i j tristate ? 56 64 pf[2] pcr[82] af0 af1 af2 af3 ? gpio[82] e0uc[12] cs0_2 ? adc0_s[10] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 57 65 pf[3] pcr[83] af0 af1 af2 af3 ? gpio[83] e0uc[13] cs1_2 ? adc0_s[11] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 58 66 pf[4] pcr[84] af0 af1 af2 af3 ? gpio[84] e0uc[14] cs2_2 ? adc0_s[12] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 59 67 pf[5] pcr[85] af0 af1 af2 af3 ? gpio[85] e0uc[22] cs3_2 ? adc0_s[13] siul emios_0 dspi_2 ? adc_0 i/o i/o o ? i j tristate ? 60 68 pf[6] pcr[86] af0 af1 af2 af3 ? gpio[86] e0uc[23] cs1_1 ? adc0_s[14] siul emios_0 dspi_1 ? adc_0 i/o i/o o ? i j tristate ? 61 69 pf[7] pcr[87] af0 af1 af2 af3 ? gpio[87] ? cs2_1 ? adc0_s[15] siul ? dspi_1 ? adc_0 i/o ? o ? i j tristate ? 62 70 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 67 pf[8] pcr[88] af0 af1 af2 af3 gpio[88] can3tx cs4_0 can2tx siul flexcan_3 dspi_0 flexcan_2 i/o o o o m tristate ? 34 42 pf[9] pcr[89] af0 af1 af2 af3 ? ? ? gpio[89] e1uc[1] cs5_0 ? wkup[22] (4) can2rx can3rx siul emios_1 dspi_0 ? wkup flexcan_2 flexcan_3 i/o i/o o ? i i i s tristate ? 33 41 pf[10] pcr[90] af0 af1 af2 af3 gpio[90] cs1_0 lin4tx e1uc[2] siul dspi_0 linflex_4 emios_1 i/o o o i/o m tristate ? 38 46 pf[11] pcr[91] af0 af1 af2 af3 ? ? gpio[91] cs2_0 e1uc[3] ? wkup[15] (4) lin4rx siul dspi_0 emios_1 ? wkup linflex_4 i/o o i/o ? i i s tristate ? 39 47 pf[12] pcr[92] af0 af1 af2 af3 gpio[92] e1uc[25] lin5tx ? siul emios_1 linflex_5 ? i/o i/o o ? m tristate ? 35 43 pf[13] pcr[93] af0 af1 af2 af3 ? ? gpio[93] e1uc[26] ? ? wkup[16] (4) lin5rx siul emios_1 ? ? wkup linflex_5 i/o i/o ? ? i i s tristate ? 41 49 pf[14] pcr[94] af0 af1 af2 af3 gpio[94] can4tx e1uc[27] can1tx siul flexcan_4 emios_1 flexcan_1 i/o o i/o o m tristate ? 102 126 pf[15] pcr[95] af0 af1 af2 af3 ? ? ? gpio[95] e1uc[4] ? ? eirq[13] can1rx can4rx siul emios_1 ? ? siul flexcan_1 flexcan_4 i/o i/o ? ? i i i s tristate ? 101 125 port g table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 68 freescale semiconductor pg[0] pcr[96] af0 af1 af2 af3 gpio[96] can5tx e1uc[23] ? siul flexcan_5 emios_1 ? i/o o i/o ? m tristate ? 98 122 pg[1] pcr[97] af0 af1 af2 af3 ? ? gpio[97] ? e1uc[24] ? eirq[14] can5rx siul ? emios_1 ? siul flexcan_5 i/o ? i/o ? i i s tristate ? 97 121 pg[2] pcr[98] af0 af1 af2 af3 gpio[98] e1uc[11] sout_3 ? siul emios_1 dspi_3 ? i/o i/o o ? m tristate ? 8 16 pg[3] pcr[99] af0 af1 af2 af3 ? gpio[99] e1uc[12] cs0_3 ? wkup[17] (4) siul emios_1 dspi_3 ? wkup i/o i/o o ? i s tristate ? 7 15 pg[4] pcr[100] af0 af1 af2 af3 gpio[100] e1uc[13] sck_3 ? siul emios_1 dspi_3 ? i/o i/o i/o ? m tristate ? 6 14 pg[5] pcr[101] af0 af1 af2 af3 ? ? gpio[101] e1uc[14] ? ? wkup[18] (4) sin_3 siul emios_1 ? ? wkup dspi_3 i/o i/o ? ? i i s tristate ? 5 13 pg[6] pcr[102] af0 af1 af2 af3 gpio[102] e1uc[15] lin6tx ? siul emios_1 linflex_6 ? i/o i/o o ? m tristate ? 30 38 pg[7] pcr[103] af0 af1 af2 af3 ? ? gpio[103] e1uc[16] e1uc[30] ? wkup[20] (4) lin6rx siul emios_1 emios_1 ? wkup linflex_6 i/o i/o i/o ? i i s tristate ? 29 37 pg[8] pcr[104] af0 af1 af2 af3 ? gpio[104] e1uc[17] lin7tx cs0_2 eirq[15] siul emios_1 linflex_7 dspi_2 siul i/o i/o o i/o i s tristate ? 26 34 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 69 pg[9] pcr[105] af0 af1 af2 af3 ? ? gpio[105] e1uc[18] ? sck_2 wkup[21] 4 lin7rx siul emios_1 ? dspi_2 wkup linflex_7 i/o i/o ? i/o i i s tristate ? 25 33 pg[10] pcr[106] af0 af1 af2 af3 ? gpio[106] e0uc[24] e1uc[31] ? sin_4 siul emios_0 emios_1 ? dspi_4 i/o i/o i/o ? i s tristate ? 114 138 pg[11] pcr[107] af0 af1 af2 af3 gpio[107] e0uc[25] cs0_4 ? siul emios_0 dspi_4 ? i/o i/o o ? m tristate ? 115 139 pg[12] pcr[108] af0 af1 af2 af3 gpio[108] e0uc[26] sout_4 ? siul emios_0 dspi_4 ? i/o i/o o ? m tristate ? 92 116 pg[13] pcr[109] af0 af1 af2 af3 gpio[109] e0uc[27] sck_4 ? siul emios_0 dspi_4 ? i/o i/o i/o ? m tristate ? 91 115 pg[14] pcr[110] af0 af1 af2 af3 gpio[110] e1uc[0] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? 110 134 pg[15] pcr[111] af0 af1 af2 af3 ? gpio[111] e1uc[1] ? ? ? siul emios_1 ? ? ? i/o i/o ? ? ? m tristate ? 111 135 port h ph[0] pcr[112] af0 af1 af2 af3 ? gpio[112] e1uc[2] ? ? sin_1 siul emios_1 ? ? dspi_1 i/o i/o ? ? i m tristate ? 93 117 ph[1] pcr[113] af0 af1 af2 af3 gpio[113] e1uc[3] sout_1 ? siul emios_1 dspi_1 ? i/o i/o o ? m tristate ? 94 118 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 70 freescale semiconductor ph[2] pcr[114] af0 af1 af2 af3 gpio[114] e1uc[4] sck_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? 95 119 ph[3] pcr[115] af0 af1 af2 af3 gpio[115] e1uc[5] cs0_1 ? siul emios_1 dspi_1 ? i/o i/o i/o ? m tristate ? 96 120 ph[4] pcr[116] af0 af1 af2 af3 gpio[116] e1uc[6] ? ? siul emios_1 ? ? i/o i/o ? ? m tristate ? 134 162 ph[5] pcr[117] af0 af1 af2 af3 gpio[117] e1uc[7] ? ? siul emios_1 ? ? i/o i/o ? ? s tristate ? 135 163 ph[6] pcr[118] af0 af1 af2 af3 gpio[118] e1uc[8] ? ma[2] siul emios_1 ? adc_0 i/o i/o ? o m tristate ? 136 164 ph[7] pcr[119] af0 af1 af2 af3 gpio[119] e1uc[9] cs3_2 ma[1] siul emios_1 dspi_2 adc_0 i/o i/o o o m tristate ? 137 165 ph[8] pcr[120] af0 af1 af2 af3 gpio[120] e1uc[10] cs2_2 ma[0] siul emios_1 dspi_2 adc_0 i/o i/o o o m tristate ? 138 166 ph[9] 8 pcr[121] af0 af1 af2 af3 gpio[121] ? tck ? siul ? jtagc ? i/o ? i ? s input, weak pull-up 88 127 155 ph[10] 8 pcr[122] af0 af1 af2 af3 gpio[122] ? tms ? siul ? jtagc ? i/o ? i ? m input, weak pull-up 81 120 148 ph[11] pcr[123] af0 af1 af2 af3 gpio[123] sout_3 cs0_4 e1uc[5] siul dspi_3 dspi_4 emios_1 i/o o i/o i/o m tristate ? ? 140 ph[12] pcr[124] af0 af1 af2 af3 gpio[124] sck_3 cs1_4 e1uc[25] siul dspi_3 dspi_4 emios_1 i/o i/o i/o ? m tristate ? ? 141 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 71 ph[13] pcr[125] af0 af1 af2 af3 gpio[125] sout_4 cs0_3 e1uc[26] siul dspi_4 dspi_3 emios_1 i/o o i/o ? mtristate ? ? 9 ph[14] pcr[126] af0 af1 af2 af3 gpio[126] sck_4 cs1_3 e1uc[27] siul dspi_4 dspi_3 emios_1 i/o i/o i/o ? m tristate ? ? 10 ph[15] pcr[127] af0 af1 af2 af3 gpio[127] sout_5 ? e1uc[17] siul dspi_5 ? emios_1 i/o o ? ? mtristate ? ? 8 port i pi[0] pcr[128] af0 af1 af2 af3 gpio[128] e0uc[28] ? ? siul emios_0 ? ? i/o i/o ? ? s tristate ? ? 172 pi[1] pcr[129] af0 af1 af2 af3 ? ? gpio[129] e0uc[29] ? ? wkup[24] (4) ? siul emios_0 ? ? wkup ? i/o i/o ? ? i ? s tristate ? ? 171 pi[2] pcr[130] af0 af1 af2 af3 gpio[130] e0uc[30] ? ? siul emios_0 ? ? i/o i/o ? ? s tristate ? ? 170 pi[3] pcr[131] af0 af1 af2 af3 ? ? gpio[131] e0uc[31] ? ? wkup[23] (4) ? siul emios_0 ? ? wkup ? i/o i/o ? ? i ? s tristate ? ? 169 pi[4] pcr[132] af0 af1 af2 af3 gpio[132] e1uc[28] sout_4 ? siul emios_1 dspi_4 ? i/o i/o o ? s tristate ? ? 143 pi[5] pcr[133] af0 af1 af2 af3 gpio[133] e1uc[29] sck_4 ? siul emios_1 dspi_4 ? i/o i/o i/o ? s tristate ? ? 142 pi[6] pcr[134] af0 af1 af2 af3 gpio[134] e1uc[30] cs0_4 ? siul emios_1 dspi_4 ? i/o i/o i/o ? s tristate ? ? 11 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 72 freescale semiconductor pi[7] pcr[135] af0 af1 af2 af3 gpio[135] e1uc[31] cs1_4 ? siul emios_1 dspi_4 ? i/o i/o i/o ? s tristate ? ? 12 pi[8] pcr[136] af0 af1 af2 af3 ? gpio[136] ? ? ? adc0_s[16] siul ? ? ? adc_0 i/o ? ? ? i j tristate ? ? 108 pi[9] pcr[137] af0 af1 af2 af3 ? gpio[137] ? ? ? adc0_s[17] siul ? ? ? adc_0 i/o ? ? ? i j tristate ? ? 109 pi[10] pcr[138] af0 af1 af2 af3 ? gpio[138] ? ? ? adc0_s[18] siul ? ? ? adc_0 i/o ? ? ? i j tristate ? ? 110 pi[11] pcr[139] af0 af1 af2 af3 ? ? gpio[139] ? ? ? adc0_s[19] sin_3 siul ? ? ? adc_0 dspi_3 i/o ? ? ? i i j tristate ? ? 111 pi[12] pcr[140] af0 af1 af2 af3 ? gpio[140] cs0_3 ? ? adc0_s[20] siul dspi_3 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 112 pi[13] pcr[141] af0 af1 af2 af3 ? gpio[141] cs1_3 ? ? adc0_s[21] siul dspi_3 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 113 pi[14] pcr[142] af0 af1 af2 af3 ? ? gpio[142] ? ? ? adc0_s[22] sin_4 siul ? ? ? adc_0 dspi_4 i/o ? ? ? i i j tristate ? ? 76 pi[15] pcr[143] af0 af1 af2 af3 ? gpio[143] cs0_4 ? ? adc0_s[23] siul dspi_4 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 75 table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 73 port j pj[0] pcr[144] af0 af1 af2 af3 ? gpio[144] cs1_4 ? ? adc0_s[24] siul dspi_4 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 74 pj[1] pcr[145] af0 af1 af2 af3 ? ? gpio[145] ? ? ? adc0_s[25] sin_5 siul ? ? ?? adc_0 dspi_5 i/o ? ? ? i i j tristate ? ? 73 pj[2] pcr[146] af0 af1 af2 af3 ? gpio[146] cs0_5 ? ? adc0_s[26] siul dspi_5 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 72 pj[3] pcr[147] af0 af1 af2 af3 ? gpio[147] cs1_5 ? ? adc0_s[27] siul dspi_5 ? ? adc_0 i/o i/o ? ? i j tristate ? ? 71 pj[4] pcr[148] af0 af1 af2 af3 gpio[148] sck_5 e1uc[18] ? siul dspi_5 emios_1 ? i/o i/o ? ? mtristate ? ? 5 1 alternate functions are chosen by setting the values of the pcr.pa bitfields inside the siul module. pcr.pa = 00 ? af0; pcr.pa = 01 ? af1; pcr.pa = 10 ? af2; pcr.pa = 11 ? af3. this is intended to select the output functions; to use one of the input f unctions, the pcr.ibe bit must be written to ?1?, regardless of the values selected in the pcr.pa bitfields. for this reason, the value corresponding to an input only function is reported as ???. 2 see ta b l e 4 - 2 . 3 the reset configuration applies during and after reset. 4 all wkup pins also support external interrupt capability. see the wkpu chapter of the MPC5606BK microcontroller reference manual for further details. 5 nmi has higher priority than alternate function. wh en nmi is selected, the pcr.af field is ignored. 6 ?not applicable? because these functions are available on ly while the device is booting. see the bam chapter of the MPC5606BK microcontroller reference manual for details. 7 value of pcr.ibe bit must be 0. 8 out of reset all the functional pins except pc[0:1 ] and ph[9:10] are available to the user as gpio. pc[0:1] are available as jtag pins (tdi and tdo respectively). ph[9:10] are available as jtag pins (tck and tms respectively). it is up to the user to configur e these pins as gpio when needed. table 4-1. functional port pins (continued) port pin pcr register alternate function 1 function peripheral i/o direction pad type 2 reset config. 3 pin number 100 lqfp 144 lqfp 176 lqfp
chapter 4 signal description MPC5606BK microcontroller reference manual, rev. 2 74 freescale semiconductor 9 pc[1] is a fast/medium pad but is in medium configuration by default. this pad is in alternate function 2 mode after reset which has tdo functionality. the reset value of pcr.obe is 1, but this setting has no impact as long as this pad stays in af2 mode. after configuring this pad as gpio (pcr.pa = 0), output buffer is enabled as reset value of pcr.obe = 1. 10 not available in 100lqfp package. table 4-2. pad types type description ffast i input only with analog feature j input/output with analog feature mmedium sslow
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 75 chapter 5 microcontroller boot this chapter explains the process of booting the microcontroller. the following entities are involved in the boot process: ? boot assist module (bam) ? system status and conf iguration module (sscm) ? flash memory boot sectors (see chapter 30, flash memory ) ? memory management unit (mmu) 5.1 boot mechanism this section describes the configuration require d by the user, and the steps performed by the microcontroller, in order to achieve a successful boot from flash memory or serial download modes. two external pins on the microcontroller are la tched during reset, and determine whether the microcontroller boots from flash memory or attempt a serial download via flex can or linflex (rs232). these are: ? fab (force alternate boot mode) on pin pa[9] ? abs (alternate boot select) on pin pa[8] table 5-1 describes the configuration options. the microcontroller has a weak pull down on pa[9] and a weak pullup on pa [8]. this means that if nothing external is connected to these pins, the microcontroll er will enter flash memory boot mode by default. in order to change the boot behavior, you should use ex ternal pullup or pulldown resistors on pa[9] and pa[8]. if there is any external circ uitry connected to either pin, you must ensure that this does not interfere with the expected value applied to the pin at rese t. otherwise, the microcontroller may boot into an unexpected mode after reset. the sscm preforms a lot of the automated boot activ ity including reading the latched value of the fab (pa[9]) pin to determine wh ether to boot from flash memory or seri al boot mode. this is illustrated in figure 5-1 . table 5-1. boot mode selection mode fab pin (pa[9]) abs pin (pa[8]) flash memory boot (default mode) 0 x serial boot (linflex) 1 0 serial boot (flexcan) 1 1
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 76 freescale semiconductor figure 5-1. boot mode selection 5.1.1 flash memory boot in order to successfully boot from fl ash memory, you must progr am two 32-bit fields in to one of 5 possible boot blocks as detailed below. the entities to program are: ? 16-bit reset configuration half word (rchw), which contains: ? a boot_id field that must be correctly set to 0x5a in order to ?validate? the boot sector ? 32-bit reset vector (this is the start address of the user code) the location and structure of the boot se ctors in flash memory are shown in figure 5-2 . fab (pa[9]) value? fab = 0 boot from abs (pa[8]) value? serial boot (flexcan) sscm reads latched values of pa[8] and pa[9] pins flash memory serial boot (linflex) fab = 1 abs = 0 abs = 1
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 77 figure 5-2. boot sector structure the rchw fields are described in table 5-2 . the sscm performs a sequential search of each boot sector (starting at sector 0) for a valid boot_id within the rchw. if a valid boot_id is found, th e sscm reads the boot vector address. if a valid boot_id is not found, the sscm starts the process of putting the micr ocontroller into static mode. finally, the sscm sets the e200z0h core instruction pointer to the reset v ector address and starts the core running. 5.1.1.1 static mode if no valid boot_id within the rchw was found, the sscm sets the cpu core instruction pointer to the bam address and the core starts to execute the code to enter static mode as follows: ? the core executes the ?wait? instruction, which halts the core. the sequence is illustrated in figure 5-3 . table 5-2. rchw field descriptions field description boot_id boot identifier. if boot_id = 0x5a, the boot sector is considered valid and bootable. 32 kb boot sector 0 16 kb 16 kb 32 kb 0x0000_0000 0x0000_8000 0x0000_c000 0x0001_0000 code flash memory 32 kb 0x0001_8000 boot sector 1 boot sector 2 boot sector 3 boot sector 4 boot sector structure bit 0 bit 31 reserved reserved 78 1516 boot_id (0x5a) 0x0 (rchw) 0x4 32-bit reset vector (points to start address of application code) 0x8 application code (from offset 0x8 and onward)
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 78 freescale semiconductor figure 5-3. flash memory boot mode sequence 5.1.1.2 alternate boot sectors some applications require an alternate boot sector so that the main boot code can be erased and reprogrammed in the field. when an alternate boot is needed, you can creat e two bootable sectors: ? the valid boot sector located at the lo west address is the main boot sector. ? the valid boot sector located at the next av ailable address is the alternate boot sector. this scheme ensures that there is always one active boot sector even if the main boot sector is erased. 5.1.2 serial boot mode serial boot provides a mechanism to download and th en execute code into the microcontroller sram. code may be downloaded using eith er flexcan or linflex (rs232). after the sscm has detected that serial boot mode has been requested, execution is transferred to the bam, which handles all of the serial boot mode tasks. see section 5.2, boot assist module (bam) , for more details. 5.1.3 censorship censorship can be enabled to protect the contents of the flash memory from be ing read or modified. in order to achieve this, the censorship mechanism controls access to the: ? jtag debug interface ? serial boot mode (which could othe rwise be used to download and ex ecute code to query or modify the flash memory) sscm searches flash boot sectors for valid valid boot_id found? sscm reads reset vector address yes no boot_id (0x5a) sscm transfers execution to e200z0h core, which runs bam code bam code executes wait instruction system in static mode e200z0h core starts executing code at vector address (requires reset to recover)
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 79 to regain access to the flash memo ry via jtag or serial boot, a 64-bit password must be correctly entered. caution when censorship has been enabled, the onl y way to regain access is with the password. if this is forgotten or not correctly configured, then there is no way back into the device. two 64-bit values stored in the shadow flash control the censorship (see table 30-6 for a full description): ? nonvolatile private censorship passw ord registers, nvpwd0 and nvpwd1 ? nonvolatile system censorship cont rol registers, nvscc0 and nvscc1 5.1.3.1 censorship password registers (nvpwd0 and nvpwd1) the two private password registers combine to form a 64-bit password that s hould be programmed to a value known only by you. after factory test thes e registers are programmed as shown below: ? nvpwd0 = 0xfeed_face ? nvpwd1 = 0xcafe_beef this means that even if censorship was inadvertently enabled by writing to the censorship control registers, there is an opportunity to get back into the micr ocontroller using the defa ult private password of 0xfeed_face_cafe_beef. when configuring the private passwo rd, each half word (16-bit) must contain at least one 1 and one 0. some examples of legal and illegal passwords are shown in table 5-3 : in uncensored devices it is possibl e to download code via linflex or flexcan (serial boot mode) into internal sram even if the 64-bit private password stored in the flash and provided during the boot sequence is a password that does not conform to the password rules. 5.1.3.2 nonvolatile system censorship control registers (nvscc0 and nvscc1) these registers are used together to define the censorship configuration. afte r factory test these registers are programmed as sh own below, which disables censorship: ? nvscc0 = 0x55aa_55aa ? nvscc1 = 0x55aa_55aa each 32-bit register is split into an upper and lower 16-bit field. the uppe r 16 bits (the sc field) are used to control serial boot mode censorshi p. the lower 16 bits (the cw field) are used to control flash memory boot censorship. table 5-3. examples of legal and illegal passwords legal (valid) passwords illegal (invalid) passwords 0x0001_0001_0001_0001 0xfffe_fffe_fffe_fffe 0x1xxx_x2xx_xx4x_xxx8 0x0000_xxxx_xxxx_xxxx 0xffff_xxxx_xxxx_xxxx
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 80 freescale semiconductor caution if the contents of the shadow flas h memory are erased and the nvscc0,1 registers are not reprogramme d to a valid value, the microcontroller will be permanently censored with no way for you to regain access. a microcontroller in this state cannot be debugged or reflashed. 5.1.3.3 censorship configuration the steps to configuring censorship are: 1. define a valid 64-bit password that conforms to the password rules. 2. using the table and flow charts below, decide what level of censorship you require and configure the nvscc0,1 values. 3. reprogram the shadow flash memory and nvpwd0,1 and nvscc0,1 registers with your new values. a por is required before these will take effect. caution if (nvscc0 and nvscc1 do not match) or (either nvscc0 or nvscc1 is not set to 0x55aa) then the microcontroller will be perman ently censored with no way to get back in. table 5-4 shows all the possible m odes of censorship. the red shaded areas are to be avoided as these show the configuration for a device that is permanently locked out. if you wi sh to enable censorship with a private password there is only one valid configurat ion ? to modify the cw field in both nvscc0,1 registers so they match but do not equal 0x55aa. this will allow you to enter the private password in both serial and flash boot modes.
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 81 the flow charts in figure 5-4 and figure 5-5 provide a way to quickly check what will happen with different configurations of the nvscc 0,1 registers as well as detailing th e correct way to enter the serial password. in the password examples , assume the 64-bit password has been programmed into the shadow flash memory in the order {nvpwd0, nw pwd1} and has a value of 0x01234567_89abcdef. table 5-4. censorship configuration and truth table boot configuration serial censorship control word (nvscc n [sc]) censorship control word (nvscc n [cw]) internal flash memory state serial password jtag password fab pin state control options 0 (flash memory boot) uncensored 0xxxxx and nvscc0 == nvscc1 0x55aa and nvscc0 == nvscc1 enabled n/a private flash memory password and censored 0x55aa and nvscc0 == nvscc1 !0x55aa and nvscc0 == nvscc1 enabled nvpwd 1,0 (sscm reads flash memory 1 ) 1 when the sscm reads the passwords from flash memory, th e nvpwd0 and nvpwd1 password order is swapped, so you have to submit the 64-bit password as {nvpwd1, nvpwd0}. censored with no password access (lockout) !0x55aa !0x55aa enabled n/a or nvscc0 != nvscc1 1 (serial boot) private flash memory password and uncensored 0x55aa and nvscc0 == nvscc1 enabled nvpwd 0,1 (bam reads flash memory 1 ) private flash memory password and censored 0x55aa and nvscc0 == nvscc1 !0x55aa and nvscc0 == nvscc1 enabled nvpwd 1,0 (sscm reads flash memory 1 ) public password and uncensored !0x55aa and nvscc0 != nvscc1 0x55aa and nvscc0 != nvscc1 enabled public (0xfeed_fac e_cafe_bee f) public password and censored (lockout) !0x55aa disabled public (0xfeed_fac e_cafe_bee f) or nvscc0 != nvscc1 = microcontroller permanently locked out = not applicable
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 82 freescale semiconductor figure 5-4. censorship control in flash memory boot mode fab = 0 (flash boot mode) nvscc0 != nvscc1 ? true censored with no password access (locked out) jtag password details: enter password as {nvpwd 1 , nvpwd 0 } false false false both sc and cw != 0x55aa cw != 0x55aa ? ? true censored with no password access (locked out) true censored with private password over jtag uncensored example ? 0x89abcdef_01234567 note: sc = 0x55aa
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 83 figure 5-5. censorship control in serial boot mode 5.2 boot assist module (bam) the bam consists of a block of rom at address 0xffff_c000 containing v le firmware. the bam provides 2 main functions: ? manages the serial download (f lexcan or linflex protocols s upported) including support for a serial password if censorship is enabled ? places the microcontroller into static mode if flash memory boot mode is selected and a valid boot_id is not located in one of the boot sectors by the sscm 5.2.1 bam software flow figure 5-6 illustrates the bam logic flow. fab = 1 (serial boot mode) nvscc0 != nvscc1 ? true censored with no password access (locked out) serial password details: enter public password 0xfeedface_cafebeef false false false both sc and cw != 0x55aa sc != 0x55aa ? ? true censored with no password access (locked out) true note: cw = 0x55aa false cw != 0x55aa ? true note: sc = 0x55aa public password, uncensored flash (private) password, censored flash (private) password, uncensored enter password as {nvpwd 1 , nvpwd 0 } example ? 0x89abcdef_01234567 enter password as {nvpwd 0 , nvpwd 1 } example ? 0x01234567_89abcdef
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 84 freescale semiconductor figure 5-6. bam logic flow the initial (reset) device configur ation is saved including the mode a nd clock configuration. this means that the serial download software running in the bam can make cha nges to the modes and clocking, and then restore these to the default values before r unning the newly downloaded application code from the sram. the sscm_status[bmode] field indicates wh ich boot mode is to be executed (see table 5-5 ). this field is only updated during reset. there are two conditions where the boot mode is not considered valid and the bam pushes the microcontroller into static mode afte r restoring the defa ult configuration: ? bmode = 011 (flash memory boot mode). this means that the sscm has been unable to find a valid boot_id in the boot s ectors so has called the bam ? bmode = reserved in static mode a wait instruction is executed to halt the core. for the flexcan and linflex serial boot modes, th e respective area of bam code is executed to download the code to sram. no restore default configuration configuration save default bam entry 0xffff_c000 boot mode valid? download new code and save in sram restore default configuration execute new code static mode ye s check boot mode at sscm_status[bmode]
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 85 after the code has been downloaded to sram, the ba m code restores the initi al device configuration, and then transfers execution to the start address of the downloaded code. 5.2.1.1 bam resources the bam uses/initializes th e following mcu resources: ? mc_me and mc_cgm to initia lize mode and clock sources ? flexcan_0, linflex _0 and the respective i/ o pins when performing serial boot mode ? sscm during password check ? sscm to check the boot mode (see table 5-5 ) ? 4?16 mhz fast external crystal oscillator the system clock is selected direct ly from the 4?16 mhz fast external cr ystal oscillator. thus, the external oscillator frequency defines the baud rates used for serial download (see table 5-6 ). 5.2.1.2 download and execute the new code from a high level perspective, the dow nload protocol follows these steps: 1. send the 64-bit password. 2. send the start address, size of code to be downloaded (in bytes), and the vle bit 1 . 3. download the code. each step must be completed before the next step starts. after the download is complete (the specified number of bytes is downloaded), the c ode executes from the start address. table 5-5. sscm_status[bmode] values as used by bam bmode value corresponding boot mode 000 reserved 001 flexcan_0 serial boot loader 010 linflex_0 (rs232 /uart) serial boot loader 011 flash memory boot mode 100?111 reserved table 5-6. serial boot mode ? baud rates fxosc frequency (mhz) linflex baud rate (baud) can bit rate (bit/s) f fxosc f fxosc /833 f fxosc /40 8 9600 200k 12 14400 300k 16 19200 400k 1. since the device supports only vle code and not book e code, this flag is used only for backward compatibility.
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 86 freescale semiconductor the communication is done in half duplex manner, whereby the transmi ssion from the host is followed by the microcontroller transmission mirror ing the transmission back to the host: ? host sends data to the microc ontroller and waits for a response. ? mcu echoes to host the data received. ? host verifies if echo is correct: ? if data is correct, the host can continue to send data. ? if data is not correct, the host stops transmission and the microc ontroller enters static mode. all multi-byte data structures are sent with msb first. a more detailed descripti on of these steps follows. 5.2.1.3 censorship mode detection and serial password validation before the serial download can commence, the bam code must determine which censorship mode the microcontroller is in and which passw ord to use. it does this by reading the pub and sec fields in the sscm status register (see section 5.3.4.1, system status register (sscm_status) ) as shown in table 5-7 . when censorship is enabled, the flash memory cannot be read by application c ode running in the bam or in the sram. this means that the private password in the shadow flash memo ry cannot be read by the bam code. in this case the sscm is used to obtain the private password from the flash memory of the censored device. when the sscm reads the priv ate password it inverts the order of {nvpwd 0 , nwpwd 1 } so the password entered over the serial download needs to be {nvpwd 1 , nvpwd 0 }. table 5-7. bam censorship mode detection sscm_status register fields mode password comparison pub sec 1 0 uncensored, public password 0xfeed_face_cafe_beef 0 0 uncensored, private password nvpwd 0,1 from flash memory via bam 0 1 censored, private password nvpwd 1,0 from flash memory via sscm
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 87 figure 5-7. bam censorship mode detection the first thing to be downloaded is the 64-bit pass word. if the password does not match the stored password, then the bam c ode pushes the microcontro ller into static mode. the way the password is compared with either the public or private pass word (depending on mode) varies depending on whether censorship is enabled as described in the following subsections. 5.2.1.3.1 censorship disabled (p rivate or public passwords): 1. if the public password is used, the bam code does a direct compar ison between the se rial password and 0xfeed_face_cafe_beef. 2. if the private password is used, the bam c ode does a direct comparison between the serial password and the private password in flash memory, {nvpwd 0 , nvpwd 1 }. 3. if the password does not matc h, the bam code immediately term inates the download and pushes the microcontroller into static mode. yes bam code is being executed (serial boot mode) no no pub = 1 ? yes start serial download with password sscm_status register pub and sec bits are read sec = 1 ? public password, uncensored, bam can directly check password private password, censored, sscm needed to check password private password, uncensored, bam can directly check password public password mode is censorship enabled bam tasks applicable password ? ?
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 88 freescale semiconductor 5.2.1.3.2 censorship enabled (private password) 1. since the flash is secured, the sscm is required to read the private password. 2. the bam code writes the serial passwo rd to the sscm_pwcmph and sscm_pwcmpl registers. 3. the bam code then continues with the serial download (s tart address, data size, and data) until all the data has been copied to the sram. 4. in the meantime the sscm has compared the priv ate password in flash with the serial download password the bam code wrote in to sscm_pwcmph and sscm_pwcmpl. 5. if the sscm obtains a match in the passwords, th e censorship is temporar ily disabled (until the next reset). 6. the sscm updates the status of the security (sec ) bit to reflect whethe r the passwords matched (sec = 0) or not (sec = 1) 7. finally, the bam code reads se c. if sec = 0, execution is transfer red to the code in the sram. if sec = 1, the bam code forces the microcontroller into static mode. figure 5-8 shows this in more detail.
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 89 figure 5-8. bam serial boot mode flow for censorship enabled and private password with linflex, any receive error will result in static m ode. with flexcan, the host will retransmit data if there has been no acknowledgment from the microcontro ller. however, there could be a situation where the receiver configuration ha s an error, which would result in static mode entry. censorship enabled, private password, bam running yes bam reads sscm_status[sec] serial password received is sec bit cleared bam tasks sscm tasks serial boot mode bam writes received password to sscm registers upper 32-bits to sscm_pwcmph lower 32-bits to sscm_pwcmpl start address and data data download received and copied to sram ? bam code pushes microcontroller into static mode if any frame is received incorrectly, bam code pushes device into static mode if passwords match, un-censor device until next por update sscm_status[sec] bit with censorship state sscm compares registers to private password in flash sscm_pwcmph to nvpwd1 sscm_pwcmpl to nvpwd0 no bam code transfers execution to user code in sram length received
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 90 freescale semiconductor note in a censored device booting with serial boot mode, it is po ssible to read the content of the four 32-bit flash memory locations that make up the boot sector. for example, if the rchw is stored at address 0x0000_0000, the reads at address 0x0000_0000, 0x0000_0004, 0x0000_0008, and 0x0000_000c will return a correct value. no other flash memory locations can be read. 5.2.1.4 download start addre ss, vle bit and code size the next 8 bytes received by the micr ocontroller contain a 32-bit start address, the vle mode bit, and a 31-bit code length, as shown in figure 5-9 . the vle bit (variable length instruction) is used to indicate whet her the code to be downloaded is book vle or book iii-e. th is device family s upports only vle = 1; the bit is us ed for backward compatibility. the start address defines wh ere the received data will be stored and where the mcu will branch after the download is finished. the start addre ss is 32-bit word aligned and the 2 least significant bits are ignored by the bam code. note the start address is c onfigurable, but most not lie within the 0x4000_0000 to 0x4000_00ff address range. the length defines how many data bytes have to be loaded. 5.2.1.5 download data each byte of data received is stored in the microcont roller?s sram, starting from the address specified in the previous protocol step. the address increments until the num ber of bytes of data received matches the numbe r of bytes specified by the code length. since the sram is protected by 32-b it wide error correction code (ecc ), the bam code always writes bytes into sram grouped into 32-bit words. if the last byte received does not fall onto a 32-bit boundary, the bam code fills any additional bytes with 0x0. start_address[31:16] start_address[15:0] vle code_length[30:16] code_length[15:0] figure 5-9. start address, vle bit, and download size in bytes
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 91 since the ecc on the sram has not b een initialized (except for the bytes of data that have just been downloaded), an additional dummy word of 0x0000_0000 is written at the end of the downloaded data block to avoid any ecc errors during core prefetch. 5.2.1.6 execute code the bam code waits for the last data byte to be received. if the operati ng mode is censored with a private password, then the bam reads the sscm status register to determine whet her the serial pa ssword matched the private password. if there was a password match, then the bam code restores the initial configuration and transfers execution to the downloaded code star t address in sram. if the passwords did not match, the bam code forces a static mode entry. note the watchdog is disabled at the start of bam code execution. in the case of an unexpected issue during bam code execution, the microcontroller may be stalled and an external reset re quired to recover the microcontroller. 5.2.2 linflex (rs232) boot 5.2.2.1 configuration boot according to the linflex boot mode download protocol (see section 5.2.2.2, protocol ) is performed by the linflex_0 module in uart (rs232) mode. pins used are: ? lin0tx mapped on pb[2] ? lin0rx mapped on pb[3] boot from linflex uses the system clock driven by the 4?16 mhz external crystal oscillator (fxosc). the linflex controller is configured to operate at a baud ra te = system clock freq uency/833, using an 8-bit data frame without parity bit and 1 stop bit. figure 5-10. linflex bit timing in uart mode 5.2.2.2 protocol table 5-8 summarizes the protocol and bam action during this boot mode. d1 d2 d3 d4 d5 d6 d7 d0 byte field start bit stop bit
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 92 freescale semiconductor 5.2.3 flexcan boot 5.2.3.1 configuration boot according to the flexcan boot mode download protocol (see section 5.2.3.2, protocol ) is performed by the flexcan_0 module. pins used are: ? can0tx mapped on pb[0] ? can0rx mapped on pb[1] note when the serial download via flexcan is selected and the device is part of a can network, the serial download may stop unexpect edly if there is any other traffic on the network. to avoid this situation, ensure that no other can device on the network is active during the serial download process. boot from flexcan uses the system clock driven by the 4?16 mhz fast extern al crystal oscillator. the flexcan controller is confi gured to operate at a baud rate = system clock fr equency/40 (see table 5-6 for examples of baud rate). it uses the standard 11-bit identifier format detailed in fl excan 2.0a specification. flexcan controller bit timing is pr ogrammed with 10 time quanta, and th e sample point is 2 time quanta before the end, as shown in figure 5-11 . table 5-8. uart boot mode download protocol protocol step host sent message bam response message action 1 64-bit password (msb first) 64-bit password password checked for validity and compared against stored password. 2 32-bit store address 32-bit store address load address is stored for future use. 3 vle bit + 31-bit number of bytes (msb first) vle bit + 31-bit number of bytes (msb first) size of download are stored for future use. verify if vle bit is set to 1 4 8 bits of raw binary data 8 bits of raw binary data 8-bit data are packed into a 32-bit word. this word is saved into sram starting from the ?load address?. ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 5 none none branch to downloaded code
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 93 figure 5-11. flexcan bit timing 5.2.3.2 protocol table 5-9 summarizes the protocol and bam action during this boot mode. all data are transmitted byte wise. table 5-9. flexcan boot mode download protocol protoco l step host sent message bam response message action 1 can id 0x011 + 64-bit password can id 0x001 + 64-bit password password checked for validity and compared against stored password 2 can id 0x012 + 32-bit store address + vle bit + 31-bit number of bytes can id 0x002 + 32-bit store address + vle bit + 31-bit number of bytes load address is stored for future use. size of download are stored for future use. verify if vle bit is set to 1 3 can id 0x013 + 8 to 64 bits of raw binary data can id 0x003 + 8 to 64 bits of raw binary data 8-bit data are packed into 32-bit words. these words are saved into sram starting from the ?load address?. ?load address? increments until the number of data received and stored matches the size as specified in the previous step. 5 none none branch to downloaded code sync_seg time segment 1 time segment 2 sample point nrz signal transmit point 1 time quantum time quanta time quanta 7 2 1 bit time 1 time quantum = 4 system clock periods
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 94 freescale semiconductor 5.3 system status and co nfiguration module (sscm) 5.3.1 introduction the primary purpose of the sscm is to provide information about the cu rrent state and configuration of the system that may be useful for configuring application softwa re and for debug of the system. on microcontrollers with a separate standby power domain, the system status block is part of that domain. figure 5-12. sscm block diagram 5.3.2 features the sscm includes these features: ? system configuration and status ? memory sizes/status ? microcontroller mode and security status (i ncluding censorship and serial boot information) ? search code flash for bootable sector ? determine boot vector ? device identification inform ation (mcu id registers) ? debug status port enable and selection ? bus and peripheral abort enable/disable bus system status and configuration module interface password comparator revid hardmacro core logic system status peripheral interface bus
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 95 5.3.3 modes of operation the sscm operates identically in all system modes. 5.3.4 memory map and register description table 5-10 shows the memory map for the sscm. note that all addresses are offsets; the absolute address may be calculated by adding the specified offset to the base address of the sscm. all registers are accessible via 8-bit, 16-bit, or 32-b it accesses. however, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses must be al igned to 32-bit boundaries. as an example, the sscm_status register is accessibl e by a 16-bit read/write to address base + 0x0002, but performing a 16-bit access to base + 0x0003 is illegal. 5.3.4.1 system status re gister (sscm_status) the system status register is a read-only register that reflects the current state of the system. table 5-10. sscm memory map address offset register location 0x00 system status register (sscm_status) on page 95 0x02 system memory configuration register (sscm_memconfig) on page 96 0x04 reserved 0x06 error configuration (sscm_error) on page 97 0x08 debug status port register (sscm_debugport) on page 98 0x0a reserved 0x0c password comparison register high word (sscm_pwcmph) on page 99 0x10 password comparison register low word (sscm_pwcmpl) on page 99 offset:0x00 access: read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 pub sec 0 bmode 0 0 0 0 0 w reset000000000/10/10/10 0000 figure 5-13. system status register (sscm_status) table 5-11. sscm_status allowed register accesses access type 8-bit 16-bit 32-bit 1 read allowed allowed allowed write not allowed not allowed not allowed
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 96 freescale semiconductor 5.3.4.2 system memory configurat ion register (sscm_memconfig) the system memory configur ation register is a read-o nly register that reflects the memory configuration of the system. 1 all 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xc). table 5-12. sscm_status field descriptions field description pub public serial access status. this bit indicates whether serial boot mode with public password is allowed. 1 serial boot mode with public password is allowed 0 serial boot mode with private flash memory password is allowed sec security status. this bit reflects the cu rrent security state of the flash memory. 1 the flash memory is secured. 0 the flash memory is not secured. bmode device boot mode 000 reserved 001 flexcan_0 serial boot loader 010 linflex_0 serial boot loader 011 single chip 100 reserved 101 reserved 110 reserved 111 reserved this field is only updated during reset. offset: 0x02 access: read 0123456789101112131415 r 0 0 0 0 0 prsz pvlb dtsz dvld w resetxxxxxxxxxx1xxxx1 figure 5-14. system memory config uration register (sscm_memconfig)
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 97 5.3.4.3 error configuration (sscm_error) the error configuration register is a read-write register that controls the error handling of the system. table 5-13. sscm_memconfig field descriptions field description prsz code flash size 10000 128 kb 10001 256 kb 10010 384 kb 10011 512 kb 10101 768 kb 10111 1 mb 11011 1.5 mb pvlb code flash available this bit identifies whether or not the on-chip code flash is available in the system memory map. the flash may not be accessible due to security limitations, or because there is no flash in the system. 1 code flash is available 0 code flash is not available dtsz data flash size 0000 no data flash 0011 64 kb dvld data flash valid this bit identifies w hether or not the on-chip data flash is visible in the syst em memory map. the flash may not be accessible due to security limitations, or because there is no flash in the system. 1 data flash is visible 0 data flash is not visible table 5-14. sscm_memconfig allowed register accesses access type 8-bit 16-bit 32-bit read allowed allowed allowed (also reads sscm_status register) write not allowed not allowed not allowed offset: 0x06 access: read/write 0123456789101112131415 r00000000000000 pa e r a e w reset0000000000000000 figure 5-15. error conf iguration (sscm_error)
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 98 freescale semiconductor 5.3.4.4 debug status port register (sscm_debugport) the debug status port register is used to (optionally) provide debug data on a set of pins. table 5-15. sscm_error field descriptions field description pae peripheral bus abort enable this bit enables bus aborts on any access to a peripheral slot that is not used on the device. this feature is intended to aid in debugging when developing application code. 1 illegal accesses to non-existing peripherals pr oduce a prefetch or data abort exception 0 illegal accesses to non-existing peripherals do no t produce a prefetch or data abort exception rae register bus abort enable this bit enables bus aborts on illegal accesses to off-platform peripherals. illegal accesses are defined as reads or writes to reserved addresses within the address space for a particular peripheral. this feature is intended to aid in debugging when developing application code. 1 illegal accesses to peripherals produce a prefetch or data abort exception 0 illegal accesses to peripherals do not produce a prefetch or data abort exception transfers to peripheral bus resources may be aborted even before they reach the peripheral bus (that is, at the pbridge level). in this case, bits pae and rae will have no effect on the abort. table 5-16. sscm_error allowed register accesses access type 8-bit 16-bit 32-bit read allowed allowed allowed write allowed allowed not allowed offset: 0x08 access: read/write 0123456789101112131415 r0000000000000 debug_mode w reset0000000000000000 figure 5-16. debug status port register (sscm_debugport) table 5-17. sscm_debugport field descriptions field description debug_mode debug status port mode this field selects the alternate debug fu nctionality for the debug status port. 000 no alternate functionality selected 001 mode 1 selected 010 mode 2 selected 011 mode 3 selected 100 mode 4 selected 101 mode 5 selected 110 mode 6 selected 111 mode 7 selected ta b l e 5 - 1 8 describes the functionality of th e debug status port in each mode.
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 99 pin[0..7] referred to in table 5-18 equates to pc[2..9] (pad 34..41). 5.3.4.5 password comparison registers these registers provide a means for the bam code to unsecure the devi ce via the sscm if the password has been provided via serial download. table 5-18. debug status port modes pin 1 1 all signals are active high, unless otherwise noted mode 1 mode 2 mode 3 mode 4 mode 5 mode 6 mode 7 0 sscm_status [0] sscm_status [8] sscm_memconfi g[0] sscm_memconfi g[8] reserved reserved reserved 1 sscm_status [1] sscm_status [9] sscm_memconfi g[1] sscm_memconfi g[9] reserved reserved reserved 2 sscm_status [2] sscm_status [10] sscm_memconfi g[2] sscm_memconfi g[10] reserved reserved reserved 3 sscm_status [3] sscm_status [11] sscm_memconfi g[3] sscm_memconfi g[11] reserved reserved reserved 4 sscm_status [4] sscm_status [12] sscm_memconfi g[4] sscm_memconfi g[12] reserved reserved reserved 5 sscm_status [5] sscm_status [13] sscm_memconfi g[5] sscm_memconfi g[13] reserved reserved reserved 6 sscm_status [6] sscm_status [14] sscm_memconfi g[6] sscm_memconfi g[14] reserved reserved reserved 7 sscm_status [7] sscm_status [15] sscm_memconfi g[7] sscm_memconfi g[15] reserved reserved reserved table 5-19. sscm_debugport allowed register accesses access type 8-bit 16-bit 32-bit 1 1 all 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xc). read allowed allowed not allowed write allowed allowed not allowed
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 100 freescale semiconductor offset: 0x0c access: read/write 0123456789101112131415 r0000000000000000 w pwd_hi[31:16] reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w pwd_hi[15:0] reset0000000000000000 figure 5-17. password comparison register high word (sscm_pwcmph) offset: 0x10 access: read/write 0123456789101112131415 r0000000000000000 w pwd_lo[31:16] reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w pwd_lo[15:0] reset0000000000000000 figure 5-18. password comparison register low word (sscm_pwcmpl) table 5-20. password comparison register field descriptions field description pwd_hi upper 32 bits of the password pwd_lo lower 32 bits of the password table 5-21. sscm_pwcmph/l allowed register accesses access type 8-bit 16-bit 32-bit 1 1 all 32-bit accesses must be aligned to 32-bit addresses (i.e., 0x0, 0x4, 0x8 or 0xc). read allowed allowed allowed write not allowed not allowed allowed
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 101 in order to unsecure the device, the password needs to be written as follows: first the upper word to the sscm_pwcmph register, then the lower word to the sscm_pwcmpl register. the sscm compares the 64-bit password entered into the sscm_pw cmph / sscm_pwcmpl registers with the nvpwm[1,0] private password stored in the sha dow flash. if the passwords match then the sscm temporarily uncensors the microcontroller.
chapter 5 microcontroller boot MPC5606BK microcontroller reference manual, rev. 2 102 freescale semiconductor this page is intent ionally left blank.
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 103 ??? clocks and power ???
MPC5606BK microcontroller reference manual, rev. 2 104 freescale semiconductor this page is intent ionally left blank.
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 105 chapter 6 clock description this chapter describes the clock arch itectural implementa tion for MPC5606BK. 6.1 clock architecture system clocks are generated from three sources: ? fast external crystal oscillator 4?16 mhz (fxosc) ? fast internal rc oscillator 16 mhz (firc) ? frequency modulated phase locked loop (fmpll) additionally, there are tw o low power oscillators: ? slow internal rc oscillator 128 khz (sirc) ? slow external crystal oscillator 32 khz (sxosc) the clock architecture is shown in figure 6-1 .
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 106 freescale semiconductor figure 6-1. MPC5606BK system clock generation 6.2 clock gating the MPC5606BK provides the user with the possib ility of gating the clock to the peripherals. table 6-1 describes for each peripheral the associated gating re gister address. see the me_pctln section in this reference manual. additionally, peripheral set (1, 2 or 3) frequency can be configured to be an integer (1 to 16) divided version of the main system cloc k. see the cgm_sc_dc0 section in this reference manual for details. table 6-1. MPC5606BK ? peripheral clock sources peripheral register gating address offset (base = 0xc3fd_c0c0) 1 peripheral set 2 rpp_z0h platform none (managed through me mode) ? dspi_ n 4+ n ( n = 0..5) 2 fxosc firc clock monitor unit sirc reset system clock selector fmpll fxosc_clk_div firc_clk_div fmpll_clk (e.g. 64 mhz) (e.g. 8 mhz) (e.g. 16 mhz) sys_clk core platform peripheral set 1 peripheral set 2 watchdog api/rtc sxosc sxosc_clk (32 khz) /1 to /16 /1 to /16 sxosc_clk_div sirc_clk_div sirc_clk sirc_clk firc_clk fxosc_clk clkout /1, /2, /4, /8 fmpll_clk (e.g. 64 mhz) firc_clk fxosc_clk clkout selector peripheral set 3 /1 to /16 /1 to /32 /1 to /32 firc_div /1 to /32 /1 to /32 sirc_clk_div sxosc_clk_div (128 khz) dma sys_clk rtc_clk rtc_clk (4?16 mhz) (16 mhz) safe interrupt periph_set1_clk periph_set2_clk periph_set3_clk cgm_ac0_sc
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 107 6.3 fast external crystal oscill ator (fxosc) digital interface the fxosc digital interface controls the operation of the 4?16 mhz fast external crystal oscillator (fxosc). it holds control and status registers accessible for application. 6.3.1 main features ? oscillator power-down control and st atus reporting through mc_me block ? oscillator clock available interrupt ? oscillator bypass mode ? output clock division factors ranging from 1, 2, 3....32 6.3.2 functional description the fxosc circuit includes an internal oscillator driver and an external crystal circuitry. it provides an output clock that can be provided to the fmpll or used as a reference clock to specific modules depending on system needs. the fxosc can be controlled by the mc_me m odule. the me_xxx_mc[fxoscon] bit controls the powerdown of the oscillator based on the current de vice mode while me_gs[s_ xosc] register provides the oscillator clock available status. flexcan_ n 16 + n ( n =0..5) 2 adc_0 32 3 adc_1 33 3 i 2 c441 linflex_ n 48 + n ( n =0..7) 1 ctu 57 3 cans 60 ? siul 68 ? wkup 69 ? emios_ n 72 + n ( n =0..1) 3 rtc/api 91 ? pit 92 ? cmu 104 ? 1 see the me_pctl section in this reference manual for details. 2 ??? means undivided system clock. table 6-1. MPC5606BK ? peripheral clock sources (continued) peripheral register gating address offset (base = 0xc3fd_c0c0) 1 peripheral set 2
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 108 freescale semiconductor after system reset, the oscillator is put into powerdown state, and softwa re has to switch on when required. whenever the crystal oscillator is switched on from the off state, the osccnt counter starts. when it reaches the value eocv[7:0] 512, the os cillator clock is made available to the system. also, an interrupt pending fxosc_ctl[i_osc] bit is set. an interrupt is generated if th e interrupt mask bit m_osc is set. the oscillator circuit can be bypassed by setting fxosc_ctl[oscbyp]. this bit can only be set by software. a system reset is needed to reset this bi t. in this bypass mode, the output clock has the same polarity as the external clock applie d on the extal pin and the oscillator status is forced to 1. the bypass configuration is independent of th e powerdown mode of the oscillator. table 6-2 shows the truth table of differ ent oscillator configurations. the fxosc clock can be further divi ded by a configurable factor in th e range 1 to 32 to generate the divided clock to match system re quirements. this division factor is specified by fxosc_ctl[oscdiv] field. 6.3.3 register description table 6-2. truth table of crystal oscillator me_xxx_mc[fxoscon] fxosc_ctl[oscb yp] xtal extal fxosc oscillator mode 0 0 no crystal, high z no crystal, high z 0power down, iddq x 1 x ext clock extal bypass, osc disabled 1 0 crystal crystal extal normal, osc enabled gnd ext clock extal normal, osc enabled address: 0xc3fe_0000 access: special read/write 0123456789101112131415 r oscbyp 1 0000000 eocv w reset: 0000000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m_osc 00 oscdiv i_osc 2 0000000 w reset: 0000000000000000 figure 6-2. fast external crystal oscillator control register (fxosc_ctl)
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 109 6.4 slow external crystal oscillator (sxosc) digital interface 6.4.1 introduction the sxosc digital interface controls the operation of the 32 khz slow extern al crystal oscillator (sxosc). it holds control and status registers accessible for application. 6.4.2 main features ? oscillator powerdown control and status ? oscillator clock available interrupt ? oscillator bypass mode ? output clock division factors ranging from 1 to 32 6.4.3 functional description the sxosc circuit includes an internal oscillator driver and an external cr ystal circuitry. it can be used as a reference clock to specific mo dules depending on system needs. 1 you can read this field, and you can write a value of 1 to i t. writing a 0 has no effect. a reset will also clear this bit. 2 you can write a value of ?0? or ?1? to this field. however, writing a ?1? will clear this field, and writing ?0? will have no effect on the field value. table 6-3. fxosc_ctl field descriptions field description oscbyp crystal oscillator bypass. this bit specifies whether the oscillator should be bypassed or not. 0 oscillator output is used as root clock 1 extal is used as root clock eocv end of count value. these bits specify the end of count value to be us ed for comparison by the oscillator stabilization counter osccnt after reset or whenever it is swit ched on from the off state (osccnt runs on the fxosc). this counting period ensures that external oscillator clock signal is stable before it can be selected by the system. when oscillator count er reaches the value eocv 512, the crystal oscillator clock interrupt (i_osc) request is generated. the osccnt counter will be kept under reset if oscillator bypa ss mode is selected. m_osc crystal oscillator clock interrupt mask. 0 crystal oscillator clock interrupt is masked. 1 crystal oscillator clock interrupt is enabled. oscdiv crystal oscillator clock division factor. this field specifies the crystal oscillator output clock division factor. the output clock is divided by the factor oscdiv+1. i_osc crystal oscillator clock interrupt. this bit is set by hardware when osccnt counter reaches the count value eocv 512. 0 no oscillator clock interrupt occurred. 1 oscillator clock interrupt pending.
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 110 freescale semiconductor the sxosc can be controlled via the sxosc_ctl register. the oscon bit controls the powerdown while bit s_osc provides the osci llator clock available status. after system reset, the oscillator is put to powerdown state, and softwa re has to switch on when required. whenever the sxosc is switched on fr om off state, the osccnt counter starts. when it reaches the value eocv[7:0] 512, the oscillator clock is made avai lable to the system. also, an interrupt pending sxosc_ctl[i_osc] bit is set. an interrupt will be generated if th e interrupt mask bit m_osc is set. the oscillator circuit can be bypassed by writing s xosc_ctl[oscbyp] bit to 1. this bit can only be set by software. a system reset is needed to reset th is bit. in this bypass mode, the output clock has the same polarity as the external clock applied on the osc32k_extal pin and the oscillator status is forced to 1. the bypass configuration is independent of the powerdown mode of the oscillator. table 6-4 shows the truth table of different configurations of the oscillator. the sxosc clock can be further divi ded by a configurable factor in th e range 1 to 32 to generate the divided clock to match system re quirements. this division factor is specified by sxosc_ctl[oscdiv] field. 6.4.4 register description table 6-4. sxosc truth table sxosc_ctl fields osc32k_xtal osc32k_extal sxosc oscillator mode oscon oscbyp 0 0 no crystal, high z no crystal, high z 0 powerdown, iddq x 1 x external clock osc32k_extal bypass, osc disabled 1 0 crystal crystal osc32k_extal normal, osc enabled ground external clock osc32k_extal normal, osc enabled address: 0xc3fe_0040 access: special read/write 0123456789101112131415 r oscbyp 1 0000000 eocv w reset: 0000000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m_osc 00 oscdiv i_osc 2 00000 s_osc oscon w reset: 0000000000000000 figure 6-3. slow external crystal oscillator control register (sxosc_ctl)
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 111 note the 32 khz slow external crystal oscill ator is by default always on, but can be configured off in st andby by setting the oscon bit. 6.5 slow internal rc oscillat or (sirc) digital interface 6.5.1 introduction the sirc digital interface controls the 128 khz slow in ternal rc oscillator (sirc). it holds control and status registers accessi ble for application. 1 you can read this field, and you can write a value of 1 to i t. writing a 0 has no effect. a reset will also clear this bit. 2 you can write a value of ?0? or ?1? to this field. however, writing a ?1? will clear this field, and writing ?0? will have no effect on the field value. table 6-5. sxosc_ctl field descriptions field description oscbyp crystal oscillator bypass. this bit specifies whether the oscillator should be bypassed or not. 0 oscillator output is used as root clock. 1 osc32k_extal is used as root clock. eocv end of count value. this field specifies the end of count value to be us ed for comparison by the oscillator stabilization counter osccnt after reset or whenever it is switch ed on from the off state. this counting period ensures that external oscillator cl ock signal is stable before it can be selected by the system. when oscillator counter reaches the value eocv 512, the crystal oscillator clock interrupt (i_osc) request is generated. the osccnt counter will be kept under reset if oscillator bypass mode is selected. m_osc crystal oscillator clock interrupt mask. 0 crystal oscillator clock interrupt is masked. 1 crystal oscillator clock interrupt is enabled. oscdiv crystal oscillator clock division factor. this field specifies the crystal oscillator output cl ock division factor. the output clock is divided by the factor oscdiv + 1. i_osc crystal oscillator clock interrupt. this field is set by hardware when osccnt counter reaches the count value eocv 512. 0 no oscillator clock interrupt occurred. 1 oscillator clock interrupt pending. s_osc crystal oscillator status. 0 crystal oscillator output clock is not stable. 1 crystal oscillator is providing a stable clock. oscon crystal oscillator enable. 0 crystal oscillator is switched off. 1 crystal oscillator is switched on.
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 112 freescale semiconductor 6.5.2 functional description the sirc provides a low frequency (f sirc ) clock of 128 khz requiring ve ry low current consumption. this clock can be used as the reference clock when a fixed base time is required for specific modules. sirc is always on in all device modes except standby mode. in standby mode, it is controlled by sirc_ctl[sircon_stdby] bit. the clock source status is updated in sirc_ctl[s_sirc] bit. the sirc clock can be further divide d by a configurable di vision factor in the range from 1 to 32 to generate the divided clock to match system requi rements. this division factor is specified by sirc_ctl[sircdiv] bits. the sirc output frequency can be trimmed using sirc_ctl[sirctri m]. after a power-on reset, the sirc is trimmed using a factory test value stored in test flash memo ry. however, after a power-on reset the test flash memory value is not visible at sirc_ctl[sirctrim], and this field shows a value of zero. therefore, be aware that the sirc_ctl[sirctrim] doe s not reflect the current trim value until you have written to this field. pay particular attention to this feature when you initiate a read-modify-write operation on sirc_ctl, because a sirctrim value of 0 may be unintentionally written back, and this may alter the sirc frequency. in this case, you should calibrate the sirc using the cmu or be sure that you only write to the upper 16 bits of this sirc_ctl. in this oscillator, two's comple ment trimming method is implemente d. so the trimming code increases from ?16 to 15. as the trimming code increases, the internal time constant increases and frequency reduces. please refer to the device datasheet for average frequency variation of the trimming step. 6.5.3 register description address: 0xc3fe_0080 access: read/write 0123456789101112131415 r00000000000 sirctrim w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 sircdiv 000 s_sirc 000 sircon_stdby w reset: 0000001100000000 figure 6-4. low power rc control register (sirc_ctl)
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 113 6.6 fast internal rc oscillat or (firc) digital interface 6.6.1 introduction the firc digital interface controls the 16 mhz fast internal rc oscill ator (firc). it holds control and status registers accessi ble for application. 6.6.2 functional description the firc provides a high frequency (f firc ) clock of 16 mhz. this clock can be used to accelerate the exit from reset and wakeup sequence from low power mode s of the system. it is controlled by the mc_me module based on the current device mode. the clock s ource status is updated in me_gs[s_rc]. please see chapter 8, mode entry module (mc_me) , for further details. the firc can be further divided by a configurable division factor in the range from 1 to 32 to generate the divided clock to match system re quirements. this division factor is specified by rc_ctl[rcdiv] bits. the firc output frequency can be trimmed using firc_ctl[firctri m]. after a power-on reset, the firc is trimmed using a factory test value stored in test flash memo ry. however, after a power-on reset the test flash memory value is not visible at firc_ctl[firctrim], and this field will show a value of 0. therefore, be aware that the firc _ctl[firctrim] field does not reflec t the current trim value until you have written to it. pay pa rticular attention to this feature when you initiate a read-m odify-write operation on firc_ctl, because a firc trim value of zero may be unintentionally written ba ck and this may alter the firc frequency. in this case, you should calibrate the firc using the cmu or ensure that you write only to the upper 16 bits of this firc_ctl. in this oscillator, two's comple ment trimming method is implemente d. so the trimming code increases from ?32 to 31. as the trimming code increases, the internal time constant increases and frequency reduces. please refer to the device datasheet for average frequency variation of the trimming step. table 6-6. sirc_ctl field descriptions field description sirctrim sirc trimming bits. this field corresponds (via twos complement) to a trim factor of ?16 to +15. a +1 change in sirctrim decreases the current frequency by ? sirctrim (see the device data sheet). a ?1 change in sirctrim increas es the current frequency by ? sirctrim (see the device data sheet). sircdiv sirc clock division factor. this field specifies the sirc oscillator output cl ock division factor. the output clock is divided by the factor sircdiv+1. s_sirc sirc clock status. 0 sirc is not providing a stable clock. 1 sirc is providing a stable clock. sircon_stdby sirc contro l in standby mode. 0 sirc is switched off in standby mode. 1 sirc is switched on in standby mode.
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 114 freescale semiconductor during standby mode entry process, the firc is controlled based on me_standby_mc[rcon] bit. this is the last step in the standby entry seque nce. on any system wakeup event, the device exits standby mode and switches on the firc. the actual powerdown status of the firc when the device is in standby is provided by rc_ctl[fircon_stdby] bit. 6.6.3 register description address: 0xc3fe_0060 access: read/write 0123456789101112131415 r0000000000 firctrim w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 fircdiv 00 fircon_stdby 00000 w reset: 0000000000000000 figure 6-5. firc oscillator control register (firc_ctl) table 6-7. firc_ctl field descriptions field description firctrim firc trimming bits. this field corresponds (via twos complement) to a trim factor of ?16 to +15. a +1 change in firctrim decreases the current frequency by ? firctrim (see the device data sheet). a ?1 change in sirctrim increases the current frequency by ? firctrim (see the device data sheet). fircdiv firc clock division factor. this field specifies the firc oscillator output cl ock division factor. the output clock is divided by the factor fircdiv+1. fircon_stdb y firc control in standby mode. 0 firc is switched off in standby mode. 1 firc is in standby mode.
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 115 6.7 frequency-modulated ph ase-locked loop (fmpll) 6.7.1 introduction this section describes the features and functions of the fmpll module implemented in the device. 6.7.2 overview the fmpll enables the generation of high speed sy stem clocks from a co mmon 4?16 mhz input clock. further, the fmpll supports progr ammable frequency modulation of the system clock. the fmpll multiplication factor and out put clock divider ratio are all software configurable. MPC5606BK has one fmpll that can generate the syst em clock and takes advantage of the fm mode. note the user must take care not to program the device with a frequency higher than allowed (no hardware check). the fmpll block diagram is shown in figure 6-6 . figure 6-6. fmpll block diagram 6.7.3 features the fmpll has the following major features: ? input clock frequency 4 mhz ? 16 mhz ? voltage controlled oscillator (vco) range from 256 mhz to 512 mhz ? frequency divider (fd) for re duced frequency operation without forcing the fmpll to relock ? frequency modulated fmpll ? modulation enabled/disabled through software ? triangle wave modulation ? programmable modulation depth ? 0.25% to 4% deviation fr om center spread frequency 1 ? ? 0.5% to +8% deviation fr om down spread frequency ? programmable modulation frequency dependent on reference frequency ? self-clocked mode (scm) operation 1. spread spectrum should be programmed in line with maximum datasheet frequency figures. buffer charge pump low pass filter vco idf ndiv loop frequency divider odf phi fxosc cgm_ac0_sc firc
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 116 freescale semiconductor ? 4 available modes ? normal mode ? progressive clock switching ? normal mode with frequency modulation ? powerdown mode 6.7.4 memory map 1 table 6-8 shows the memory map of the fmpll. 6.7.5 register description the fmpll operation is controlled by two registers. those registers can be accessed and written in supervisor mode only. 6.7.5.1 control register (cr) 1. fmpll_x are mapped through the me_cgm register slot table 6-8. fmpll memory map base address: 0xc3fe_00a0 address offset register location 0x0 control register (cr) on page 116 0x4 modulation register (mr) on page 119 offset: 0x0 access: supervisor read/write 0123456789101112131415 r 0 0 idf odf 0 ndiv w reset0000001001000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 en_pll_sw 0 unlock_once 0 i_lock s_lock pll_fail_mask pll_fail_flag 1 w w1c w1c reset0000000000000001 figure 6-7. control register (cr)
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 117 table 6-9. cr field descriptions field description idf the value of this field sets the fmpll input division factor as described in ta b l e 6 - 1 0 . odf the value of this field sets the fmpll output division factor as described in ta b l e 6 - 1 1 . ndiv the value of this field sets the fm pll loop division factor as described in ta bl e 6 - 1 2 . en_pll_sw this bit is used to enable progressive clock s witching. after the pll locks, the pll output initially is divided by 8, and then progressivel y decreases until it reaches divide-by-1. 0 progressive clock switching disabled. 1 progressive clock switching enabled. note: progressive clock switching should not be used if a non-changing clock is needed, such as for serial communications, until the division has finished. unlock_once this bit is a sticking indication of fmpll loss of lock condition. unlock_once is set when the fmpll loses lock. whenever the fmpll reacquires lock, unlock_once remains set. only a power-on reset clears this bit. i_lock this bit is set by hardware whenever there is a lock/unlock event. s_lock this bit is an indication of whether the fmpll has acquired lock. 0: fmpll unlocked 1: fmpll locked note: pll_fail_mask this bit is used to mask the pll_fail output. 0 pll_fail not masked. 1 pll_fail masked. pll_fail_flag this bit is asynchronously set by hardware whenever a loss of lock event occurs while fmpll is switched on. it is cleared by software writing 1. table 6-10. input divide ratios idf[3:0] input divide ratios 0000 divide by 1 0001 divide by 2 0010 divide by 3 0011 divide by 4 0100 divide by 5 0101 divide by 6 0110 divide by 7 0111 divide by 8 1000 divide by 9 1001 divide by 10 1010 divide by 11 1011 divide by 12 1100 divide by 13
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 118 freescale semiconductor 1101 divide by 14 1110 divide by 15 1111 clock inhibit table 6-11. output divide ratios odf[1:0] output divide ratios 00 divide by 2 01 divide by 4 10 divide by 8 11 divide by 16 table 6-12. loop divide ratios ndiv[6:0] loop divide ratios 0000000?0011111 ? 0100000 divide by 32 0100001 divide by 33 0100010 divide by 34 ... ... 1011111 divide by 95 1100000 divide by 96 1100001?1111111 ? table 6-10. input divide ratios (continued) idf[3:0] input divide ratios
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 119 6.7.5.2 modulation register (mr) offset: 0x4 access: supervisor read/write 0123456789101112131415 r strb_bypass 0 sprd_sel mod_period w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fm_en inc_step w reset: 0000000000000000 figure 6-8. modulation register (mr) table 6-13. mr field descriptions field description strb_bypass strobe bypass. the strb_bypass signal is used to bypass the str obe signal used inside fmpll to latch the correct values for control bits (inc_step, mod_period, and sprd_sel). 0 strobe is used to latch fmpll modulation control bits 1 strobe is bypassed. in this case control bits n eed to be static. the control bits must be changed only when fmpll is in powerdown mode. sprd_sel spread type selection. the sprd_sel controls the spread type in frequency modulation mode. 0 center spread 1 down spread mod_period modulation period. the mod_period field is the binary equivalent of the value modperiod derived from following formula: where: f ref : represents the frequency of the feedback divider f mod : represents the modulation frequency modperiod f ref 4f mod ? -------------------- =
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 120 freescale semiconductor 6.7.6 functional description 6.7.6.1 normal mode in normal mode the fmpll inputs are driven by the cr. this means that, when the fmpll is in lock state, the fmpll output clock (phi) is derived by the reference clock (clkin) through this relation: where the value of idf, ndiv, and odf are set in the cr and can be derived from table 6-10 , table 6-11 , and table 6-12 . fm_en frequency modulation enable. the fm_en enables the frequency modulation. 0 frequency modulation disabled 1 frequency modulation enabled inc_step increment step. the inc_step field is the binary equivalent of the value incstep derived from following formula: where: md : represents the peak modulation depth in percentage (center spread ? pk-pk = md, downspread ? pk-pk = ?2 md) mdf : represents the nominal value of loop divider (cr[ndiv]) table 6-14. fmpll lookup table crystal frequency (mhz) fmpll output frequency (mhz) cr field values vco frequency (mhz) idf odf ndiv 8320232256 64 0 2 64 512 80 0 1 40 320 16 32 1 2 32 256 64 1 2 64 512 80 1 1 40 320 40 32 4 2 32 256 64 4 2 64 512 80 3 1 32 320 table 6-13. mr field descriptions (continued) field description incstep round 2 15 1 ? ?? md ? mdf ? 100 5 ? modperiod ? -------------------------------------------------------------- - ?? ?? = phi clkin ndiv ? idf odf ? --------------------------------- - =
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 121 6.7.6.2 progressive clock switching progressive clock switchi ng allows to switch the system cloc k to fmpll output clock stepping through different division factors. this mean s that the current consumption gradua lly increases and, in turn, voltage regulator response is improved. this feature can be enabled by programming cr[en_p ll_sw] bit. when enabled, the system clock is switched to divided phi. the fmpll_clk divider is th en progressively decreased to the target divider as shown in table 6-15 . figure 6-9. fmpll output clock division flow during progressive switching 6.7.6.3 normal mode with frequency modulation the fmpll default mode is wit hout frequency modulation enabled. when frequency modulation is enabled, however, two parameters must be set to ge nerate the desired level of modulation: the period and the step. the modulation waveform is always a triangle wave and its sh ape is not programmable. fm mode is activated in two steps: 1. configure the fm mode characte ristics: mod_period, inc_step. 2. enable the fm mode by programming bit fm_en of the mr to 1. fm mode can only be enabled when fmpll is in lock state. there are two ways to latch these values inside the fmpll, dependi ng on the value of bit strb_bypass in the mr. if strb_bypass is low, the modulation parameters are latched in the fmpll only when the strobe signal goes high for at least two cycles of clkin cloc k. the strobe signal is automatically generated in the fmpll digital interface when the modulation is en abled (fm_en goes high) if the fmpll is locked (s_lock = 1), or when the modulation has been en abled (fm_en = 1) and fmpll enters lock state (s_lock goes high). table 6-15. progressive clock switching on pll_select rising edge number of fmpll output clock cycles fmpll_clk frequency (fmpll output clock frequency) 8 (fmpll output clock frequency)/8 16 (fmpll output clock frequency)/4 32 (fmpll output clock frequency)/2 onward fmpll output clock frequency fmpll output clock fmpll_clk division factors of 8, 4, 2 or 1
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 122 freescale semiconductor if strb_bypass is high, the strobe signal is bypassed. in this case, control bi ts (mod_period[12:0], inc_step[14:0], spread_cont rol) need to be static or hardwi red to constant values. the control bits must be changed only when the fmpll is in powerdown mode. the modulation depth in % is note the user must ensure that the produc t of inctep and modperiod is less than (2 15 ?1). figure 6-10. frequency modulation 6.7.6.4 powerdown mode to reduce consumption, the fmpll can be switched off when not required by programming the registers me_x_mc on the mc_me module. 6.7.7 recommendations to avoid any unpredictable behavior of the fmpll cl ock, it is recommended to follow these guidelines: ? the fmpll vco frequency should reside in th e range 256 mhz to 512 mhz. care is required when programming the multiplication and divisi on factors to respect this requirement. ? once the pll has been locked, only the output divider can be changed. ? use pll progressive clock switchi ng to ramp system clock (/8, /4, / 2, /1) automatically for the case when pll is enabled and selected as system clock. modulationdepth 100 5 ? incstepxmodperiod ? 2 15 1 ? ?? mdf ? -------------------------------------------------------------------------------------------- - ?? ?? =
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 123 ? mod_period, inc_step, spread_sel bits shoul d be modified before activating the fm mode. then strobe has to be generated to enable the new settings. if strb_byp is set to 1 then mod_period, inc_step, and spread_sel can be modified only when fmpll is in powerdown mode. 6.8 clock monitor unit (cmu) 6.8.1 introduction the clock monitor unit (cmu), also referred to as clock quality checker or cl ock fault detector, serves two purposes. the main task is to permanently superv ise the integrity of the various clock sources, for example a crystal osci llator or fmpll. in case the fmpll leaves an upper or lower frequency boundary or the crystal oscillator fails it can detect and forward these kind of events to the mc_me and the mc_cgm. the clock management unit in turn can then switch to a safe mode where it uses the default safe clock source (firc), resets the device, or gene rates the interrupt according to the system needs. it can also monitor the external crys tal oscillator clock, whic h must be greater than the internal rc clock divided by a division factor given by cmu_csr[rcdiv], and generate s a system clock transition request or an interrupt when enabled. the second task of the cmu is to provide a frequenc y meter, which allows to measure the frequency of one clock source vs. a reference clock. this is us eful to allow the calibration of the on-chip rc oscillator(s), as well as being able to correct/calculate the time deviati on of a counter that is clocked by the rc oscillator. 6.8.2 main features ? firc, sirc, sxosc oscillator frequency measurement usi ng fxosc as reference clock ? external oscillator clock monitoring with respect to firc_clk/n clock ? fmpll clock frequency monitoring for a high and low frequency range wi th firc as reference clock ? event generation for various failur es detected insi de monitoring unit
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 124 freescale semiconductor 6.8.3 block diagram figure 6-11. clock monitor unit diagram 6.8.4 functional description the clock and frequency names referenced in this block are defined as follows: ? fxosc_clk: clock coming from the fa st external crystal oscillator ? sxosc_clk: clock coming from the sl ow external crystal oscillator ? sirc_clk: clock coming from the slow (low frequency) inte rnal rc oscillator cmu_mdr xosc supervisor fxosc < firc / n cmu_hfrefr cmu_lfrefr frequency meter cmu_fdr fmpll supervisor olr_evt fhh_fll_or_evt_a xxosc on/off from mc_me fmpll on/off from mc_me mux1 cksel1[1:0] 00 01 10 11 firc_clk firc_clk sirc_clk sxosc_clk fxosc_clk fmpll fmpll > hfref or fmpll < lfref olr_evt : it is the event signalling xosc failure when asserted. when this signal is asserted, rgm may generate reset, interrupt or safe request based on the rgm configuration. fhh_fll_or_evt_a : it is the event signalling fmpll failure when a sserted. based on the cmu_hfrefr and cmu_lfrefr configuration, if the fmpll is greater than hign frequency ra nge or less than the low frequency range configuration, this signa l is generated. when this signal is asserted, rgm may generate reset, interrupt or safe request based on the rgm configuration .
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 125 ? firc_clk: clock coming from the fast (h igh frequency) internal rc oscillator ? fmpll_clk: clock coming from the fmpll ?f fxosc_clk: frequency of fast external crystal oscillator clock ?f sxosc_clk : frequency of slow external crystal oscillator clock ?f sirc_clk : frequency of slow (low freq uency) internal rc oscillator ?f firc_clk : frequency of fast (high fre quency) internal rc oscillator ?f fmpll_clk : frequency of fmpll clock 6.8.4.1 crystal clock monitor if f fxosc_clk is less than f firc_clk divided by 2 rcdiv bits of the cmu_csr a nd the fxosc_clk is on as signaled by the mc_me, then: ? an event pending bit olri in cmu_isr is set. ? a failure event olr is signaled to the mc_rgm, which in turn can automatically switch to a safe fallback clock and generate an interrupt or reset. note functional fxosc monitoring can onl y be guaranteed when the fxosc frequency is greater than (firc / 2 rcdiv ) + 0.5 mhz. 6.8.4.2 fmpll clock monitor the f fmpll_clk can be monitored by programming bit cm e of the cmu_csr register to 1. the fmpll_clk monitor starts as soon as bit cme is set. this monitor can be disabled at a ny time by writing bit cme to 0. if f fmpll_clk is greater than a reference value determined by bits hfref[11:0] of the cmu_hfrefr and the fmpll_clk is on, as signaled by the mc_me, then: ? an event pending bit fhhi in cmu_isr is set. ? a failure event is signaled to the mc_rgm, which in turn can gene rate an interrupt or safe mode request or functional reset, depending on the programming model. if f fmpll_clk is less than a reference value determined by bits lfref[11:0] of the cmu_lfrefr and the fmpll_clk is on, as signaled by the mc_me, then: ? an event pending bit flli in cmu_isr is set. ? a failure event fll is signaled to the mc_rgm, wh ich in turn can generate an interrupt or safe mode request or functional reset, depending on the programming model. note functional fmpll monitoring can onl y be guaranteed when the fmpll frequency is greater than (firc / 4) + 0.5 mhz.
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 126 freescale semiconductor note the internal rc oscillator is used as reliable refe rence clock for the clock supervision. in order to avoid fals e events, proper programming of the dividers is required. these have to take into account the accuracy and frequency deviation of the internal rc oscillator. note if pll frequency goes out of range, th e cmu shall generate fmpll fll/fhh event. it takes approximately 5 ? s to generate this event. 6.8.4.3 frequency meter the purpose of the frequency meter is twofold: ? to measure the frequency of the oscillators sirc, firc or sxosc ? to calibrate an internal rc oscillat or (sirc or firc) using a known frequency hint: this value can then be stored into the flash so that application software can reuse it later on. the reference clock is always the fxosc_clk. the frequency meter retu rns a precise value of frequencies f sxosc_clk , f firc_clk or f sirc_clk according to cksel1 bit value. the measure starts when bit sfm (start frequency measure) in the cmu_cs r is set to 1. the measurement duration is given by the cmu_mdr in numbers of clock cycles of the selected clock s ource with a width of 20 bits. bit sfm is reset to 0 by hardware once the frequency meas urement is done, and the count is loaded in the cmu_fdr. the frequency f x 1 can be derived from the value lo aded in the cmu_fdr as follows: f x = (f fxosc md) / n eqn. 6-1 where n is the value in the cmu_fdr and md is the value in the cmu_mdr. the frequency meter by default evaluates f firc_clk , but software can swap to f sirc_clk or f sxosc_clk by programming the cksel bits in the cmu_csr. 6.8.5 memory map and register description the memory map of the cmu is shown in table 6-16 . 1. x = firc,sirc or sxosc table 6-16. cmu memory map base address: 0xc3fe_0100 register name address offset reset value location control status register (cmu_csr) 0x00 0x00000006 on page 127 frequency display register (cmu_fdr) 0x04 0x00000000 on page 128 high frequency reference register fmpll (cmu_hfrefr) 0x08 0x00000fff on page 128 low frequency reference register fmpll (cmu_lfrefr) 0x0c 0x00000000 on page 129 interrupt status register (cmu_isr) 0x10 0x00000000 on page 129
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 127 6.8.5.1 control status register (cmu_csr) reserved 0x14 0x00000000 ? measurement duration register (cmu_mdr) 0x18 0x00000000 on page 130 offset: 0x00 access: read/write 0123456789101112131415 r0000000 0 sfm 1 1 you can read this field, and you can write a value of ?1? to it . writing a ?0? has no effect. a reset will also clear this bit. 000 0 000 w reset000000000 0000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 cksel1 00000 rcdiv cme_a w reset000000000 0000110 figure 6-12. control status register (cmu_csr) table 6-17. cmu_csr field descriptions field description sfm start frequency measure. the software can only set this bit to start a clock frequency measure. it is reset by hardware when the measure is ready in the cmu_fdr register. 0 frequency measurement completed or not yet started. 1 frequency measurement not completed. cksel1 clock oscillator selection bit. cksel1 selects the clock to be measured by the frequency meter. 00 firc_clk selected. 01 sirc_clk selected. 10 sxosc_clk selected. 11 firc_clk selected. rcdiv rc clock division factor. these bits specify the rc clock division factor. t he output clock is firc_clk divided by the factor 2 rcdiv . this output clock is used to compare with fxosc_clk for crystal clock monitor feature.the clock division coding is as follows. 00 clock divided by 1 (no division) 01 clock divided by 2 10 clock divided by 4 11 clock divided by 8 cme_a fmpll_0 clock monitor enable. 0 fmpll_0 monitor disabled. 1 fmpll_0 monitor enabled. table 6-16. cmu memory map (continued) base address: 0xc3fe_0100 register name address offset reset value location
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 128 freescale semiconductor 6.8.5.2 frequency display register (cmu_fdr) . 6.8.5.3 high frequency referenc e register fmpll (cmu_hfrefr) offset: 0x04 access: read-only 0123456789101112131415 r0000000 0 0 0 0 0 fd[19:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fd[15:0] w reset0000000000000000 figure 6-13. frequency display register (cmu_fdr) table 6-18. cmu_fdr field descriptions field description fd measured frequency bits. this register shows the measured frequency f x with respect to f fxosc . the measured value is given by the following formula: f x = (f fxosc md) / n, where n is the value in cmu_fdr register. note: x = firc, sirc or sxosc. offset: 0x08 access: read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 hfref w reset00001111 11111111 figure 6-14. high frequency refere nce register fmpll (cmu_hfrefr) table 6-19. cmu_hfrefr field descriptions field description hfref high frequency reference value. this field determines the high reference value for the fmpll clock. the reference value is given by: (hfref ? 16) (f firc ? 4).
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 129 6.8.5.4 low frequency reference register fmpll (cmu_lfrefr) 6.8.5.5 interrupt status register (cmu_isr) offset: 0x0c access: read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 lfref w reset00000000 00000000 figure 6-15. low frequency reference register fmpll (cmu_lfrefr) table 6-20. cmu_lfrefr field descriptions field description lfref low frequency reference value. this field determines the low reference value for the fmpll. the reference value is given by: (lfref ? 16) (f firc ? 4). offset: 0x10 access: read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 0 00000 fhhi flli olri w w1c w1c w1c reset00000000 00000000 figure 6-16. interrupt status register (cmu_isr)
chapter 6 clock description MPC5606BK microcontroller reference manual, rev. 2 130 freescale semiconductor 6.8.5.6 measurement duration register (cmu_mdr) table 6-21. cmu_isr field descriptions field description fhhi fmpll clock frequency higher than high reference interrupt. this bit is set by hardware when f fmpll_clk becomes higher than hfref value and fmpll_clk is on as signaled by the mc_me. it can be cleared by software by writing 1. 0 no fhh event. 1 fhh event is pending. flli fmpll clock frequency lower than low reference event. this bit is set by hardware when f fmpll_clk becomes lower than lfref value and fmpll_clk is on as signaled by the mc_me. it can be cleared by software by writing 1. 0 no fll event. 1 fll event is pending. olri oscillator frequency lower than rc frequency event. this bit is set by hardware when f fxosc_clk is lower than firc_clk/2 rcdiv frequency and fxosc_clk is on as signaled by the mc_me. it can be cleared by software by writing 1. 0 no olr event. 1 olr event is pending. offset: 0x18 access: read/write 0123456789101112131415 r0000000 0 0000 md[19:16] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r md[15:0] w reset00000000 00000000 figure 6-17. measurement duration register (cmu_mdr) table 6-22. cmu_mdr field descriptions field description md measurement duration bits. this field shows the measurement duration in number s of clock cycles of the selected clock source. this value is loaded in the frequency meter downcounter. when cmu_csr[sfm] = 1, the downcounter starts counting.
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 131 chapter 7 clock generation module (mc_cgm) 7.1 overview the clock generation module (mc_cg m) generates reference clocks for all soc blocks. the mc_cgm selects one of the system clock sour ces to supply the system clock. th e mc_me controls the system clock selection (see chapter 8, mode entry module (mc_me) , for more details). a set of mc_cgm registers controls the clock dividers, which are utilized fo r divided system and peripheral clock generation. the memory spaces of system and peripheral clock sources that have addressable me mory spaces are accessed through the mc_cgm memory space . the mc_cgm also selects a nd generates an output clock. figure 7-1 shows the mc_cgm block diagram.
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 132 freescale semiconductor figure 7-1. mc_cgm block diagram 7.2 features the mc_cgm includes th e following features: ? generates system and peripheral clocks ? selects and enables/disables th e system clock supply from system clock sources according to mc_me control output clock selector/divider registers platform interface core mc_cgm mc_me system clock multiplexer/divider fxosc fmpll firc mapped modules interface mapped peripherals peripherals pa [ 0 ] mc_rgm
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 133 ? contains a set of registers to control cl ock dividers for divided clock generation ? supports multiple clock sources and maps their address spaces to its memory map ? generates an output clock ? guarantees glitchless clock transitions when changing th e system clock selection ? supports 8-, 16-, and 32-bit wide read/write accesses 7.3 modes of operation this section describes the basic functional modes of the mc_cgm. 7.3.1 normal and reset modes of operation during normal and reset modes of operation, the clock se lection for the system clock is controlled by the mc_me. 7.4 external signal description the mc_cgm delivers an output clock to the pa [0] pin for off-chip use and/or observation. 7.5 memory map and register definition note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content table 7-1. mc_cgm register description address name description size access location normal supervisor test 0xc3fe_0370 cgm_oc_en output clock enable word read read/write read/write on page 138 0xc3fe_0374 cgm_ocds_sc output clock division select byte read read/w rite read/write on page 138 0xc3fe_0378 cgm_sc_ss system clock select status byte read read read on page 139 0xc3fe_037c cgm_sc_dc0 system clock divider configuration 0 byte read read/w rite read/write on page 140 0xc3fe_037d cgm_sc_dc1 system clock divider configuration 1 byte read read/w rite read/write on page 140 0xc3fe_037e cgm_sc_dc2 system clock divider configuration 2 byte read read/w rite read/write on page 140 0xc3fe_0380 cgm_ac0_sc aux clock 0 select control word read read/w rite read/write on page 141
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 134 freescale semiconductor ? cause a transfer error table 7-2. mc_cgm memory map address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0xc3fe _0000 ? 0xc3fe _001c fxosc registers 0xc3fe _0020 ? 0xc3fe _003c reserved 0xc3fe _0040 ? 0xc3fe _005c sxosc registers 0xc3fe _0060 ? 0xc3fe _007c firc registers 0xc3fe _0080 ? 0xc3fe _009c sirc registers 0xc3fe _00a0 ? 0xc3fe _00bc fmpll registers 0xc3fe _00c0 ? 0xc3fe _00dc reserved 0xc3fe _00e0 ? 0xc3fe _00fc reserved 0xc3fe _0100 ? 0xc3fe _011c cmu registers
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 135 0xc3fe _0120 ? 0xc3fe _013c reserved 0xc3fe _0140 ? 0xc3fe _015c reserved 0xc3fe _0160 ? 0xc3fe _017c reserved 0xc3fe _0180 ? 0xc3fe _019c reserved 0xc3fe _01a0 ? 0xc3fe _01bc reserved 0xc3fe _01c0 ? 0xc3fe _01dc reserved 0xc3fe _01e0 ? 0xc3fe _01fc reserved 0xc3fe _0200 ? 0xc3fe _021c reserved 0xc3fe _0220 ? 0xc3fe _023c reserved table 7-2. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 136 freescale semiconductor 0xc3fe _0240 ? 0xc3fe _025c reserved 0xc3fe _0260 ? 0xc3fd _c27c reserved 0xc3fe _0280 ? 0xc3fe _029c reserved 0xc3fe _02a0 ? 0xc3fe _02bc reserved 0xc3fe _02c0 ? 0xc3fe _02dc reserved 0xc3fe _02e0 ? 0xc3fe _02fc reserved 0xc3fe _0300 ? 0xc3fe _031c reserved 0xc3fe _0320 ? 0xc3fe _033c reserved 0xc3fe _0340 ? 0xc3fe _035c reserved table 7-2. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 137 7.5.1 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for example, the cgm_oc_en register may be accessed as a word at address 0xc3fe_0370, as a half-word at address 0xc3fe_0372, or as a byte at address 0xc3fe_0373. 0xc3fe _0360 ? 0xc3fe _036c reserved 0xc3fe _0370 cgm_oc_enr0000000000000000 w r000000000000000 en w 0xc3fe _0374 cgm_ocds_ sc r0 0 seldiv selctl 00000000 w r0000000000000000 w 0xc3fe _0378 cgm_sc_ssr0000 selstat 00000000 w r0000000000000000 w 0xc3fe _037c cgm_sc_dc 0?2 r de0 000 div0 de1 000 div1 w r de2 000 div2 00000000 w 0xc3fe _0380 cgm_ac0_s c r0000 selctl 00000000 w r0000000000000000 w 0xc3fe _0400 ? 0xc3fe _3ffc reserved table 7-2. mc_cgm memory map (continued) address name 01232756789101112131415 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 138 freescale semiconductor 7.5.1.1 output clock enable register (cgm_oc_en) this register is used to enab le and disable the output clock. 7.5.2 output clock division select register (cgm_ocds_sc) this register is used to select th e current output clock source and its di vision factor before being delivered at the output clock. address 0xc3fe_0370 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 en w reset0000000000000000 figure 7-2. output clock enable register (cgm_oc_en) table 7-3. output clock enable register (cgm_oc_en) field descriptions field description en output clock enable control 0 output clock is disabled 1 output clock is enabled address 0xc3fe_0374 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0 0 seldiv selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 7-3. output clock division select register (cgm_ocds_sc)
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 139 7.5.3 system clock select status register (cgm_sc_ss) this register provides the current clock s ource selection for the following clocks: ? undivided: system clock ? divided by system clock divide r 0: peripheral set 1 clock ? divided by system clock divide r 1: peripheral set 2 clock ? divided by system clock divide r 2: peripheral set 3 clock see figure 7-7 for details. table 7-4. output clock division select re gister (cgm_ocds_sc) field descriptions field description seldiv output clock division select 00 output selected output clock without division 01 output selected output clock divided by 2 10 output selected output clock divided by 4 11 output selected output clock divided by 8 selctl output clock source selection control ? this value selects the current source for the output clock. 0000 4-16 mhz ext. xtal osc. 0001 16 mhz int. rc osc. 0010 freq. mod. pll 0011 system clock 0100 rtc clock 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved address 0xc3fe_0378 access: user read, supervisor read, test read 0123456789101112131415 r0000 selstat 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 7-4. system clock select status register (cgm_sc_ss)
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 140 freescale semiconductor 7.5.3.1 system clock divider configuration registers (cgm_sc_dc0 ? 2) these registers control th e system clock dividers. table 7-5. system clock select status register (cgm_sc_ss) field descriptions field description selstat system clock source selection status ? this value indicates the curr ent source for the system clock. 0000 16 mhz int. rc osc. 0001 div. 16 mhz int. rc osc. 0010 4-16 mhz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. pll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled address 0xc3fe_037c access: user read, supervisor read/write, test read/write 0123456789101112131415 r de0 000 div0 de1 000 div1 w reset1000000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r de2 000 div2 00000000 w reset1000000000000000 figure 7-5. system clock divider configuration registers (cgm_sc_dc0?2) table 7-6. system clock divider configurati on registers (cgm_sc_dc0 ?2) field descriptions field description de0 divider 0 enable 0 disable system clock divider 0 1 enable system clock divider 0 div0 divider 0 division value ? the resultant peripheral set 1 clock will have a period div0 + 1 times that of the system clock. if the de0 is set to 0 (divider 0 is disabled), any write access to the div0 field is ignored and the peripheral set 1 clock remains disabled. de1 divider 1 enable 0 disable system clock divider 1 1 enable system clock divider 1
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 141 7.5.3.2 auxiliary clock 0 select control register (cgm_ac0_sc) this register is used to select the curr ent clock source for the fmpll reference clock. div1 divider 1 division value ? the resultant peripheral set 2 clock will have a period div1 + 1 times that of the system clock. if the de1 is set to 0 (divider 1 is disabled), any write access to the div1 field is ignored and the peripheral set 2 clock remains disabled. de2 divider 2 enable 0 disable system clock divider 2 1 enable system clock divider 2 div2 divider 2 division value ? the resultant peripheral set 3 clock will have a period div2 + 1 times that of the system clock. if the de2 is set to 0 (divider 2 is disabled), any write access to the div2 field is ignored and the peripheral set 3 clock remains disabled. address 0xc3fe_0380 access: user read, supervisor read/write, test read/write 0123456789101112131415 r0000 selctl 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 7-6. auxiliary clock 0 select control register (cgm_ac0_sc) table 7-7. auxiliary clock 0 select control register (cgm_ac0_sc) field descriptions field description selctl auxiliary clock 0 source selection control ? this value selects the curre nt source for auxiliary clock 0. 0000 fxosc 0001 firc 0010 reserved 0011 reserved 0100 reserved 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved table 7-6. system clock divider configuration regi sters (cgm_sc_dc0?2) field descriptions (continued) field description
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 142 freescale semiconductor 7.6 functional description 7.6.1 system clock generation figure 7-7 shows the block diagram of the system cl ock generation logic. the mc_me provides the system clock select and switch mask (see chapter 8, mode entry module (mc_me) , for more details), and the mc_rgm provides th e safe clock request (see chapter 9, reset generation module (mc_rgm) , for more details). the safe clock reque st forces the selector to select th e 16 mhz int. rc osc. as the system clock and to ignore the system clock select. figure 7-7. mc_cgm system clock generation overview 16 mhz int. rc osc. 4-16 mhz ext. xtal osc. 2 div. ext. xtal osc. 3 freq. mod. pll 4 div. 16 mhz int. rc osc. 1 0 system clock 0 system clock is disabled if me_ _mc.sysclk = 1111 cgm_sc_ss register mc_rgm safe clock request mc_me clock select 1 0 cgm_sc_dc0 register clock divider peripheral set 1 clock cgm_sc_dc1 register clock divider peripheral set 2 clock cgm_sc_dc2 register clock divider peripheral set 3 clock
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 143 7.6.1.1 system clock source selection during normal operation, the system clock selection is controlled: ? on a safe mode or reset event, by the mc_rgm ? otherwise, by the mc_me 7.6.1.2 system clock disable during normal operation, the system cl ock can be disabled by the mc_me. 7.6.1.3 system clock dividers the mc_cgm generates three derive d clocks from the system clock. 7.6.1.4 dividers functional description dividers are utilized for the gene ration of divided system and peri pheral clocks. the mc_cgm has the following control register s for built-in dividers: ? section 7.5.3.1, system clock divider conf iguration registers (cgm_sc_dc0?2) the reset value of all counters is 1. if a divider has its de bit in the resp ective configuration register set to 0 (the divider is disabled), any va lue in its divn field is ignored. 7.6.2 output clock multiplexing the mc_cgm contains a multiplexing function for a number of clock sources that can then be utilized as output clock sources. the selection is done via the cgm_ocds_sc register. figure 7-8. mc_cgm output clock multiplexer and pa[0] generation cgm_ocds_sc.selctl cgm_ocds_sc.seldiv 0 1 2 3 register register 4-16 mhz ext. xtal osc. 0 16 mhz int. rc osc. 1 freq. mod. pll 2 system clock 3 rtc clock 4 pa [ 0 ] 0 cgm_oc_en register
chapter 7 clock generation module (mc_cgm) MPC5606BK microcontroller reference manual, rev. 2 144 freescale semiconductor 7.6.3 output clock division selection the mc_cgm provides the following output signals for the output clock generation: ? pa[0] (see figure 7-8 ). this signal is generated by utiliz ing one of the 3-stage ripple counter outputs or the selected signal wi thout division. the non-divided signa l is not guaranteed to be 50% duty cycle by the mc_cgm. ? the mc_cgm also has an output clock enable register (see section 7.5.1.1, output clock enable register (cgm_oc_en) ), which contains the output cl ock enable/disable control bit.
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 145 chapter 8 mode entry module (mc_me) 8.1 overview the mc_me controls the soc modex and mode transi tion sequences in all functional states. it also contains configuration, control, and stat us registers accessible for the application. figure 8-1 shows the mc_me block diagram. figure 8-1. mc_me block diagram 8.1.1 features the mc_me includes the following features: ? control of the available modes by the me_me register ? definition of various device mode configurations by the me_ _mc registers ? control of the actual device mode by the me_mctl register registers platform interface core mc_me mc_rgm firc mc_cgm peripherals flashes vreg device mode state machine wkpu mc_pcu fmpll fxosc
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 146 freescale semiconductor ? capture of the current mode and various resource status within the conten ts of the me_gs register ? optional generation of variou s mode transi tion interrupts ? status bits for each cause of invalid mode transitions 8.1.2 modes of operation the mc_me is based on several device modes corres ponding to different usage models of the device. each mode is configurable and ca n define a policy for energy and pr ocessing power management to fit particular system requirements. an application can easily switch fr om one mode to another depending on the current needs of the system. the operating modes controlled by the mc_me are divided into system and user modes. the system modes are modes such as reset, drun, safe, and test. these modes aim to ease the configurat ion and monitoring of the system. the user modes ar e modes such as run0?3, halt, stop which can be configured to meet the application requirements in terms of energy management and available proc essing power. the modes drun, safe, test, and run0?3 are the device software running modes. table 8-1 describes the mc_me modes. table 8-1. mc_me mode descriptions name description entry exit reset this is a chip-wide virtual mode during whic h the application is not active. the system re mains in this mode until all resources are available for the embedded software to take control of the device. it manages hardware initialization of chip configuration, voltage regulators, oscillators, plls, and flash modules. system reset assertion from mc_rgm system reset deassertion from mc_rgm drun this is the entry mode for the embedded software. it provides full accessibility to the system and enables the configuration of the system at startup. it provides the unique gate to enter user modes. bam when present is executed in drun mode. system reset deassertion from mc_rgm, software request from safe, test, and run0?3 system reset assertion, run0?3, test via software, safe via software or hardware failure. safe this chip-wide service mode may be entered on the detection of a recoverable error. it forces the system into a predefined safe configuration from which the system may try to recover. hardware failure, software request from drun, test, and run0?3 system reset assertion, drun via software test this chip-wide service mode provides a control environment for device self-test. it may enable the application to run its own self-test like flash checksum, memory bist, etc. software request from drun system reset assertion, drun via software run0 ? 3 these are software running modes where most processing activity is done. these various run modes allow to enable different clock & power config urations of the system with respect to each other. software request from drun, interrupt event from halt, interrupt or wakeup event from stop system reset assertion, safe via software or hardware failure, other run0?3 modes, halt, stop via software
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 147 8.2 external signal description the mc_me has no connectio ns to any external pins . 8.3 memory map and register definition the mc_me contains registers for: ? mode selection and status reporting ? mode configuration ? mode transition interrupts status and mask control halt this is a reduced-activity low-power mode during which the clock to the core is disabled. it can be configured to switch off analog peripherals like pll, flash, main regulator, etc. for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event stop this is an advanced low-power mode during which the clock to the core is disabled. it may be configured to switch off most of the peripherals including oscillator for efficient power management at the cost of higher wakeup latency. software request from run0?3 system reset assertion, safe on hardware failure, run0?3 on interrupt event or wakeup event table 8-2. mc_me register description address name description size access location normal supervisor test 0xc3fd _c000 me_gs global status word read read read on page 151 0xc3fd _c004 me_mctl mode control word read read/write read/write on page 152 0xc3fd _c008 me_me mode enable word read read/write read/write on page 153 0xc3fd _c00c me_is interrupt status word read read/write read/write on page 154 0xc3fd _c010 me_im interrupt mask word read read/write read/write on page 155 0xc3fd _c014 me_imts invalid mode transition status word read read/write read/write on page 156 0xc3fd _c018 me_dmts debug mode transition status word read read read on page 157 table 8-1. mc_me mode descriptions (continued) name description entry exit
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 148 freescale semiconductor note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error 0xc3fd _c020 me_reset_mc reset mode configuration word read read read on page 159 0xc3fd _c024 me_test_mc test mode configuration word read read/write read/write on page 159 0xc3fd _c028 me_safe_mc safe mode configuration word read read/write read/write on page 160 0xc3fd _c02c me_drun_mc drun mode configuration word read read/write read/write on page 160 0xc3fd _c030 me_run0_mc run0 mode configuration word read read/write read/write on page 161 0xc3fd _c034 me_run1_mc run1 mode configuration word read read/write read/write on page 161 0xc3fd _c038 me_run2_mc run2 mode configuration word read read/write read/write on page 161 0xc3fd _c03c me_run3_mc run3 mode configuration word read read/write read/write on page 161 0xc3fd _c040 me_halt_mc halt mode configuration word read read/write read/write on page 161 0xc3fd _c048 me_stop_mc stop mode configuration word read read/write read/write on page 161 table 8-3. mc_me memory map w r0 0 0 0 00000 s_firc s_sysclk w 0xc3fd _c004 me_mctl r ta r g e t _ m o d e 0000000 00000 w r1 0 1 0 0101000 01111 w key table 8-2. mc_me register description (continued) address name description size access location normal supervisor test
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 149 0xc3fd _c008 me_me r0 0 0 0 0000000 00000 w 0xc3fd _c00c me_is r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c 0xc3fd _c010 me_im r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 0 m_iconf m_imode m_safe m_mtc w 0xc3fd _c014 me_imts r0 0 0 0 0000000 00000 w r0 0 0 0 0000000 s_mti s_mri s_dma s_nma s_sea w w1c w1c w1c w1c w1c 0xc3fd _c018 me_dmts r0 0 0 0 0000 mph_busy 00 pmc_prog core_dbg 00 smr w r0 0 sysclk_sw dflash_sc cflash_sc 00 0 w 0xc3fd _c01c reserved 0xc3fd _c020 me_reset_ mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 00000 fircon sysclk w table 8-3. mc_me memory map (continued)
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 150 freescale semiconductor 8.3.1 register descriptions unless otherwise noted, all registers may be accessed as 32-bit word s, 16-bit half-words, or 8-bit bytes. the bytes are ordered accor ding to big endian. for example, the me_run_pc0 register may be accessed 0xc3fd _c024 me_test_m c r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w 0xc3fd _c028 me_safe_m c r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w r0 0 0 0 00000 fircon sysclk w 0xc3fd _c02c me_drun_m c r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w 0xc3fd _c030 ? 0xc3fd _c03c me_run0?3 _mc r0 0 0 0 0000 pdo 00 mvron dflaon cflaon w 0xc3fd _c044 reserved 0xc3fd _c0 ? 0xc3fd _c reserved 0xc3fd _c080 ? 0xc3fd _c09c me_run_pc 0?7 r0 0 0 0 0000000 00000 w r0 0 0 0 0000 run3 run2 run1 run0 drun safe test reset w 0xc3fd _c150 ? 0xc3fd _fffc reserved table 8-3. mc_me memory map (continued)
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 151 as a word at address 0xc3fd_c080, as a half-word at address 0xc3f d_c082, or as a byte at address 0xc3fd_c083. 8.3.1.1 global status register (me_gs) this register contains global mode status. address 0xc3fd_c000 access: user read, supervisor read, test read w reset00001 0000011111 r 000000000 s_firc s_sysclk w reset0000000000010000 figure 8-2. global status register (me_gs) table 8-4. global status register (me_gs) field descriptions field description s_curren t_mode current device mode status 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt 1001 reserved 1010 stop 1011 reserved 1100 reserved 1101 1110 reserved 1111 reserved s_mtrans mode transition status 0 mode transition process is not active 1 mode transition is ongoing s_pdo output power-down status ? this bit specifies output power-down status of i/os. this bit is asserted whenever outputs of pads are forced to high impedance state or the pads power sequence driver is switched off. 0 no automatic safe gating of i/os used and pads power sequence driver is enabled 1 in safe/test modes, outputs of pads are fo rced to high impedance state and pads power sequence driver is disabled. the inputs are level unchanged. in stop mode, only pad power sequence driver is disabled but the state of the output is kept. s_mvr main voltage regulator status 0 main voltage regulator is not ready 1 main voltage regulator is ready for use
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 152 freescale semiconductor 8.3.1.2 mode control register (me_mctl) this register is used to trigger software-controlle d mode changes. depending on the modes as enabled by me_me register bits, configurati ons corresponding to unavailable mo des are reserved and access to me_ _mc registers must respect this for successful mode requests. s_dfla data flash availability status 00 data flash is not available 01 data flash is in power-down mode 10 data flash is in low-power mode 11 data flash is in normal mode and available for use s_cfla code flash availability status 00 code flash is not available 01 code flash is in power-down mode 10 code flash is in low-power mode 11 code flash is in normal mode and available for use s_firc fast internal rc oscillator (16 mhz) status 0 fast internal rc oscillator (16 mhz) is not stable 1 fast internal rc oscillator (16 mhz) is providing a stable clock s_sysclk system clock switch status ? these bits specify the system clock currently used by the system. 0000 16 mhz int. rc osc. 0001 div. 16 mhz int. rc osc. 0010 4?16 mhz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. pll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled address 0xc3fd_c004 access: user read, super visor read/write, test read/write r ta r g e t _ m o d e 000000000000 w reset0011000000000000 r1010010100001111 w key reset1010010100001111 figure 8-3. mode control register (me_mctl) table 8-4. global status register (me_gs) field descriptions (continued) field description
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 153 note byte and half-word write accesses are not allowed fo r this register as a predefined key is required to change its value. 8.3.1.3 mode enable register (me_me) this register allows a way to disable the device mo des that are not required for a given device. reset, safe, drun, and run0 m odes are always enabled. table 8-5. mode control register (me_mctl) field descriptions field description ta r g e t _ m ode t arget device mode ? these bits provide the target device mode to be entered by software programming. the mechanism to ente r into any mode by software requires the write operation twice: first time with key, and second time with inverted key. these bits are automatically updated by hardware while entering safe on hardware request. also, while exiting from the halt and stop modes on hardware exit events, these are updated with the appropriate run0?3 mode value. 0000 reset 0001 test 0010 safe 0011 drun 0100 run0 0101 run1 0110 run2 0111 run3 1000 halt 1001 reserved 1010 stop 1011 reserved 1100 reserved 1101 1110 reserved 1111 reserved key control key ? these bits enable write access to this regi ster. any write access to the register with a value different from the keys is ignored. read access will always return inverted key. key: 0101101011110000 (0x5af0) inverted key: 1010010100001111 (0xa50f) address 0xc3fd_c008 access: user read, super visor read/write, test read/write r0000000000000000 w reset0000000000000000 reset00000 1111 figure 8-4. mode enable register (me_me)
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 154 freescale semiconductor 8.3.1.4 interrupt status register (me_is) table 8-6. mode enable register (me_me) field descriptions field description stop stop mode enable 0 stop mode is disabled 1 stop mode is enabled halt halt mode enable 0 halt mode is disabled 1 halt mode is enabled run3 run3 mode enable 0 run3 mode is disabled 1 run3 mode is enabled run2 run2 mode enable 0 run2 mode is disabled 1 run2 mode is enabled run1 run1 mode enable 0 run1 mode is disabled 1 run1 mode is enabled run0 run0 mode enable 0 run0 mode is disabled 1 run0 mode is enabled drun drun mode enable 0 drun mode is disabled 1 drun mode is enabled safe safe mode enable 0 safe mode is disabled 1 safe mode is enabled test test mode enable 0 test mode is disabled 1 test mode is enabled reset reset mode enable 0 reset mode is disabled 1 reset mode is enabled address 0xc3fd_c00c access: user read, super visor read/write, test read/write r0000000000000000 w reset0000000000000000 r 000000000000 i_iconf i_imode i_safe i_mtc w w1c w1c w1c w1c reset0000000000000000 figure 8-5. interrupt status register (me_is)
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 155 this register provides the current interrupt status. 8.3.1.5 interrupt mask register (me_im) this register controls whether an event generates an interrupt or not. table 8-7. interrupt status register (me_is) field descriptions field description i_iconf invalid mode configuration interrupt ? this bit is set whenever a write operation to me_< mode >_mc registers with invalid mode configuration is attempted. it is cleared by writing a 1 to this bit. 0 no invalid mode configuration interrupt occurred 1 invalid mode configuration interrupt is pending i_imode invalid mode interrupt ? this bit is set whenever an invalid mode transition is requested. it is cleared by writing a 1 to this bit. 0 no invalid mode interrupt occurred 1 invalid mode interrupt is pending i_safe safe mode interrupt ? this bit is set whenever the device enters safe mode on hardware requests generated in the system. it is cleared by writing a 1 to this bit. 0 no safe mode interrupt occurred 1 safe mode interrupt is pending i_mtc mode transition complete interrupt ? this bit is set whenever the mode transition process completes (s_mtrans transits from 1 to 0). it is cleared by writing a 1 to this bit. this mode transition interrupt bit will not be set while entering low-power modes halt, stop. 0 no mode transition complete interrupt occurred 1 mode transition complete interrupt is pending address 0xc3fd_c010 access: user read, super visor read/write, test read/write r0000000000000000 w reset0000000000000000 r000000000000 m_iconf m_imode m_safe m_mtc w reset0000000000000000 figure 8-6. interrupt mask register (me_im) table 8-8. interrupt mask register (me_im) field descriptions field description m_iconf invalid mode configuration interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled m_imode invalid mode interrupt mask 0 invalid mode interrupt is masked 1 invalid mode interrupt is enabled
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 156 freescale semiconductor 8.3.1.6 invalid mode transition status register (me_imts) this register provides the st atus bits for each cause of invalid mode interrupt. m_safe safe mode interrupt mask 0 safe mode interrupt is masked 1 safe mode interrupt is enabled m_mtc mode transition comp lete interrupt mask 0 mode transition complete interrupt is masked 1 mode transition complete interrupt is enabled address 0xc3fd_c014 access: user read, super visor read/write, test read/write r0000000000000000 w reset0000000000000000 r 00000000000 s_mti s_mri s_dma s_nma s_sea w w1c w1c w1c w1c w1c reset0000000000000000 figure 8-7. invalid mode transition status register (me_imts) table 8-9. invalid mode transition status register (me_imts) field descriptions field description s_mti mode transition illegal status ? this bit is set whenever a new mode is requested while some other mode transition process is active (s_mtrans is 1). please see section 8.4.5, mode transition interrupts , for the exceptions to this behavior. it is cleared by writing a 1 to this bit. 0 mode transition requested is not illegal 1 mode transition requested is illegal s_mri mode request illegal status ? this bit is set whenever the target mode requested is not a valid mode with respect to current mode. it is cleared by writing a 1 to this bit. 0 target mode requested is not ille gal with respect to current mode 1 target mode requested is illegal with respect to current mode s_dma disabled mode access status ? this bit is set whenever the target mode requested is one of those disabled modes determined by me_me register. it is cleared by writing a 1 to this bit. 0 target mode requested is not a disabled mode 1 target mode requested is a disabled mode table 8-8. interrupt mask register (me_im) field descriptions (continued) field description
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 157 8.3.1.7 debug mode transition status register (me_dmts) this register provides the status of different factors that influence mode transitions. it is used to give an indication of why a mode tran sition indicated by me_gs.s_mtra ns may be taking longer than expected. note the me_dmts register does not indi cate whether a mode transition is ongoing. therefore, some me_dmts bits may still be asserted after the mode transition has completed. s_nma non-existing mode access status ? this bit is set whenever the target mode requested is one of those non existing modes determined by me_me regist er. it is cleared by writing a 1 to this bit. 0 target mode request ed is an existing mode 1 target mode requested is a non-existing mode s_sea safe event active status ? this bit is set whenever the device is in safe mode, safe event bit is pending and a new mode requested other than reset/safe modes. it is cleared by writing a 1 to this bit. 0 no new mode requested other than reset/safe while safe event is pending 1 new mode requested other than reset/safe while safe event is pending address 0xc3fd_c018 access: user read, super visor read/write, test read/write r 00000000 mph_busy 00 pmc_prog core_dbg 00 smr w reset0000000000000000 r 00 sysclk_sw dflash_sc cflash_sc 000 w reset0000000000000000 figure 8-8. debug mode transition status register (me_dmts) table 8-9. invalid mode transition status register (me_imts) field descriptions (continued) field description
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 158 freescale semiconductor table 8-10. debug mode transition status register (me_dmts) field descriptions field description mph_busy mc_me/mc_pcu handshake busy indicator ? this bit is set if the mc_me has requested a mode change from the mc_pcu and the mc_pcu has not yet responded. it is cleared when the mc_pcu has responded. 0 handshake is not busy 1 handshake is busy pmc_prog mc_pcu mode change in progress indicator ? this bit is set if the mc_pcu is in the process of powering up or down power domains. it is cleared when all power-up/down processes have completed. 0 power-up/down transition is not in progress 1 power-up/down transition is in progress core_dbg processor is in debug mode indicator ? this bit is set while the processor is in debug mode. 0 the processor is not in debug mode 1 the processor is in debug mode smr safe mode request from mc_rgm is active indica tor ? this bit is set if a hardware safe mode request has been triggered. it is cleared when the hardware safe mode request has been cleared. 0 a safe mode request is not active 1 a safe mode request is active firc_sc firc state change during mode transition indicator ? this bit is set when the fast internal rc oscillator (16 mhz) is requested to change its power up/down state. it is clear ed when the fast internal rc oscillator (16 mhz) has completed its state change. 0 no state change is taking place 1 a state change is taking place sysclk_s w system clock switching pending status ? 0 no system clock source switching is pending 1 a system clock source switching is pending dflash_sc dflash state change during mode transition indicator ? this bit is set when the dflash is requested to change its power up/down state. it is cleared when the dflash has completed its state change. 0 no state change is taking place 1 a state change is taking place cflash_sc cflash state change during mode transition indicator ? this bit is set when the cflash is requested to change its power up/down state. it is cleared when the dflash has completed its state change. 0 no state change is taking place 1 a state change is taking place
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 159 8.3.1.8 reset mode configur ation register (me_reset_mc) this register configures system be havior during reset mode. please see table 8-11 for details. 8.3.1.9 test mode configurat ion register (me_test_mc) this register configures system behavior during test mode. please see table 8-11 for details. note byte and half-word write accesses ar e not allowed to this register. address 0xc3fd_c020 access: user read, super visor read/write, test read/write r 00000000pdo00 mvron dflaon cflaon w reset0000000000011111 r 000000000 fircon sysclk w reset0000000000010000 figure 8-9. invalid mode transition status register (me_imts) address 0xc3fd_c024 access: user read, super visor read/write, test read/write r 00000000 pdo 00 mvron dflaon cflaon w reset0000000000011111 reset0000000000010000 figure 8-10. test mode configuration register (me_test_mc)
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 160 freescale semiconductor 8.3.1.10 safe mode configur ation register (me_safe_mc) this register configures system be havior during safe mode. please see table 8-11 for details. note byte and half-word write accesses ar e not allowed to this register. 8.3.1.11 drun mode configuration register (me_drun_mc) this register configures system behavior during drun mode. please see table 8-11 for details. note byte and half-word write accesses ar e not allowed to this register. note the values of cflaon, and dflaon are retained through standby mode. address 0xc3fd_c028 access: user read, super visor read/write, test read/write r 00000000 pdo 00 mvron dflaon cflaon w reset0000000010011111 r 000000000 fircon sysclk w reset0000000000010000 figure 8-11. safe mode configuration register (me_safe_mc) address 0xc3fd_c02c access: user read, super visor read/write, test read/write r 00000000pdo00 mvron dflaon cflaon w reset0000000000011111 reset0000000000010000 figure 8-12. drun mode configuration register (me_drun_mc)
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 161 8.3.1.12 run0?3 mode configuration registers (me_run0 ? 3_mc) this register configures system be havior during run0?3 modes. please see table 8-11 for details. note byte and half-word write accesses ar e not allowed to this register. 8.3.1.13 halt mode configurat ion register (me_halt_mc) this register configures system be havior during halt mode. please see table 8-11 for details. note byte and half-word write accesses ar e not allowed to this register. 8.3.1.14 stop mode configuration register (me_stop_mc) this register configures system be havior during stop mode. please see table 8-11 for details. note byte and half-word write accesses ar e not allowed to this register. address 0xc3fd_c030?0xc3fd_c03c access: user read, supervisor read/write, test read/write r 00000000pdo00 mvron dflaon cflaon w reset0000000000011111 reset0000000000010000 figure 8-13. run0?3 mode configuration registers (me_run0?3_mc) address 0xc3fd_c040 access: user read, super visor read/write, test read/write reset0000000000011010 reset0000000000010000 figure 8-14. halt mode configuration register (me_halt_mc)
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 162 freescale semiconductor table 8-11. mode confutation registers (me_< mode >_mc) field descriptions field description pdo i/o output power-down control ? this bit controls the output power-down of i/os. 0 no automatic safe gating of i/os used and pads power sequence driver is enabled 1 in safe/test modes, outputs of pads are fo rced to high impedance state and pads power sequence driver is disabled. the inputs are level unchanged. in stop mode, only pad power sequence driver is disabled but the state of the output is kept. mvron main voltage regulator control ? this bit specifies whether main voltage regulator is switched off or not while entering this mode. 0 main voltage regulator is switched off 1 main voltage regulator is switched on dflaon data flash power-down control ? this bit specifies the operat ing mode of the data flash after entering this mode. 00 reserved 01 data flash is in power-down mode 10 data flash is in low-power mode 11 data flash is in normal mode note: if the flash memory is to be powered down in any mode, then your software must ensure that reset sources are configured as long resets in the rgm_fess register (see section 9.3.1.7, functional event short sequence register (rgm_fess) ). cflaon code flash power-down control ? this bit specifies the operating mode of the program flash after entering this mode. 00 reserved 01 code flash is in power-down mode 10 code flash is in low-power mode 11 code flash is in normal mode fircon fast internal rc oscillator (16 mhz) control 0 fast internal rc oscillator (16 mhz) is switched off 1 fast internal rc oscillator (16 mhz) is switched on sysclk system clock switch control ? these bits specify the system clock to be used by the system. 0000 16 mhz int. rc osc. 0001 div. 16 mhz int. rc osc. 0010 4?16 mhz ext. xtal osc. 0011 div. ext. xtal osc. 0100 freq. mod. pll 0101 reserved 0110 reserved 0111 reserved 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 system clock is disabled
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 163 8.4 functional description 8.4.1 mode transition request the transition from one mode to another mode is normally handled by software by accessing the mode control me_mctl register. but in cas e of special events, mode transi tion can be automa tically managed by hardware. in order to switch from one mode to another, the application should access me_mctl register twice by writing ? the first time with the value of the key (0x5af 0) into the key bit field and the required target mode into the target _mode bit field, and ? the second time with the inverted value of the key (0xa50f) into the key bit field and the required target mode into the target_mode bit field. once a valid mode transition request is detected, the ta rget mode configuration in formation is loaded from the corresponding me_ _mc register. the mode transition reque st may require a number of cycles depending on the programmed configuration, and so ftware should check the s_current_mode bit field and the s_mtrans bit of the global status re gister me_gs to verify when the mode has been correctly entered and the tr ansition process has complete d. for a description of vali d mode requests, please see section 8.4.5, mode tr ansition interrupts . any modification of the mode configur ation register of the currently sel ected mode will not be taken into account immediately but on th e next request to enter this mode. th is means that transition requests such as run0?3 ? run0?3, drun ? drun, safe ? safe, and test ? test are considered valid mode transition requests. as soon as the mode request is accepted as valid, the s_mtrans bit is set till the status in the me_gs register matches th e configuration programmed in the respective me_ _mc register. note it is recommended that software poll the s_mtrans bit in the me_gs register after requesting a transiti on to halt, stop, or standby modes.
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 164 freescale semiconductor figure 8-15. mc_me mode diagram 8.4.2 modes details 8.4.2.1 reset mode the device enters this m ode on the following events: ? from safe, drun, run0?3, or test mode wh en the target_mode bit field of the me_mctl register is written with 0000 ? from any mode due to a system reset by the mc _rgm because of some non-recoverable hardware failure in the system (see chapter 9, reset generation module (mc_rgm) , for details) transition to this mode is instantaneous, and the syst em remains in this mode until the reset sequence is finished. the mode configuration information for th is mode is provided by the me_reset_mc register. this mode has a predefined configuration, and the 16 mhz int. rc osc. is selected as the system clock. 8.4.2.2 drun mode the device enters this m ode on the following events. ? automatically from reset mode after completion of the reset sequence safe drun test reset run0 run1 halt stop system modes user modes software request non-recoverable failure run2 run3 recoverable hardware failure
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 165 ? from run0?3, safe, or test mode when th e target_mode bit field of the me_mctl register is written with 0011 as soon as any of the above events has occurred, a drun mode transi tion request is generated. the mode configuration information for this mode is provid ed by the me_drun_mc register. in this mode, the flashes, all clock sources, and the system clock configuration can be controlled by software as required. after system reset, the software ex ecution starts with the default conf iguration selecting the 16 mhz int. rc osc. as the system clock. this mode is intended to be used by software to: ? initialize all registers as per the system needs note as flashes can be configured in lo w-power or power-down state in this mode, software must ensure that th e code executes from ram before changing to this mode. 8.4.2.3 safe mode the device enters this m ode on the following events: ? from drun, run0?3, or test mode when th e target_mode bit field of the me_mctl register is written with 0010 ? from any mode except reset due to a safe mode request ge nerated by the mc_rgm because of some potentially rec overable hardware failur e in the system (see chapter 9, reset generation module (mc_rgm) , for details) as soon as any of the above events has occurred, a safe m ode transition request is generated. the mode configuration information for this mode is provid ed by the me_safe_mc register. this mode has a predefined configuration, and the 16 mhz int. rc osc. is selected as the system clock. if the safe mode is requested by software while some other mode transitio n process is ongoing, the new target mode becomes the safe mode regardless of other pending requests. in this case, the new mode request is not interpreted as an invalid request. note if software requests to change to th e safe mode and then requests to change back to the parent mode before the mode tr ansition is completed, the device?s final mode after mode transiti on will be the pare nt mode. however, this is not recommended so ftware behavior. it is recommended for software to wait until the s_mtrans bit is cl eared after requesting a change to safe before requesting another mode change. as long as a safe event is active, the system rema ins in the safe mode an d no write access is allowed to the me_mctl register. this mode is intended to be used by software to: ? assess the severity of the cause of failure and then to either ? reinitialize the device via the drun mode, or
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 166 freescale semiconductor ? completely reset the devi ce via the reset mode. if the outputs of the system i/os n eed to be forced to a high impeda nce state upon entering this mode, the pdo bit of the me_safe_mc register should be set. the input levels remain unchanged. 8.4.2.4 test mode the device enters this m ode on the following events: ? from the drun mode when the target_mode bi t field of the me_mctl register is written with 0001 as soon as any of the above events has occurred, a test mode transition request is generated. the mode configuration information for this mode is provided by the me_test_mc register. except for the main voltage regulator, all resource s of the system are configurable in th is mode. the system clock to the whole system can be stopped by programming the sysclk bit field to 111 1, and in this case, the only way to exit this mode is via a device reset. this mode is intended to be used by soft ware to execute on-chip test routines. note as flash modules can be configured to a low-power or power-down state in these modes, software must ensure th at the code will execute from ram before it changes to this mode. 8.4.2.5 run0?3 modes the device enters one of thes e modes on the following events: ? from the drun another run 0?3 mode when the target_mode bit field of the me_mctl register is written with 0100?0111 ? from the halt mode by an interrupt event ? from the stop mode by an interrupt or wakeup event as soon as any of the above events occur, a ru n0?3 mode transition request is generated. the mode configuration information for these modes is pr ovided by me_run0?3_mc regist ers. in these modes, the flashes, all clock sources, and the system clock c onfiguration can be controll ed by software as required. these modes are intended to be used by so ftware to execute application routines. note as flash modules can be configured to a low-power or power-down state in these modes, software must ensure th at the code will execute from ram before it changes to this mode. 8.4.2.6 halt mode the device enters this m ode on the following events: ? from one of the run0?3 modes when the targ et_mode bit field of the me_mctl register is written with 1000.
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 167 as soon as any of the above events occur, a ha lt mode transition request is generated. the mode configuration information for this mode is provid ed by me_halt_mc register. this mode is quite configurable, and the me_halt_mc re gister should be programmed acco rding to the system needs. the flashes can be put in power-down mode as needed. if there is a halt mode request while an interrupt request is active, the device mode does not change, and an invalid mode inte rrupt is not generated. this mode is intended as a fi rst level low-power mode with ? the core clock frozen ? only a few peripherals running and to be used by software to wait until it is requi red to do something and then to react quickly (that is, within a few system clock cycles of an interrupt event). 8.4.2.7 stop mode the device enters this m ode on the following events: ? from one of the run0?3 modes when the targ et_mode bit field of the me_mctl register is written with 1010. as soon as any of the above events occur, a st op mode transition request is generated. the mode configuration information for this mode is provided by the me_stop_mc register. this mode is fully configurable, and the me_stop_mc register should be progr ammed according to th e system needs. the flashes can be put in power-down mode as needed. if there is a stop m ode request while any interrupt or wakeup event is active, the device mode does not cha nge, and an invalid mode in terrupt is not generated. this can be used as an advanced low-power mode wi th the core clock frozen and almost all peripherals stopped. this mode is intended as an advanced low-power mode with ? the core clock frozen ? almost all peripherals stopped and to be used by software to wait until it is requi red to do something with no need to react quickly (e.g. allow for system clock s ource to be restarted). this mode can be used to stop all clock sources, thus preser ving the device status. when exiting the stop mode, the fast internal rc oscillator (16 mhz) clock is selected as the system clock until the target clock is available. 8.4.3 mode transition process the process of mode transition follows the follow ing steps in a predefined manner depending on the current device mode and the requested target mode. in many cases of m ode transition, not all steps need to be executed based on the mode control informat ion, and some steps may not be valid according to the mode definition itself.
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 168 freescale semiconductor 8.4.3.1 target mode request the target mode is requested by accessing the me_m ctl register with the required keys. this mode transition request by software must be a valid request satisfying a set of predefined rules to initiate the process. if the request fails to satisfy these rules, it is ignored, and the ta rget_mode bit field is not updated. an optional interrupt can be gene rated for invalid mode requests. see section 8.4.5, mode transition interrupts , for details. in the case of mode transitions occurring because of ha rdware events such as a reset, a safe mode request, or interrupt requests and wakeup ev ents to exit from low-power modes, the target_mode bit field of the me_mctl register is automatically updated with the appropriate target mode. the mode change process start is indicated by the setting of the mode transition status bi t s_mtrans of the me_gs register. a reset mode requested via the me_mctl register is passed to the mc_rgm, which generates a global system reset and initiates th e reset sequence. the reset mode re quest has the highest priority, and the mc_me is kept in the reset mode during the entire reset sequence. the safe mode request has the next highest priority after reset whic h can be generated by software via the me_mctl register from all software r unning modes including drun, run0?3, and test or by the mc_rgm after the detection of system hardware failures, which may occur in any mode. 8.4.3.2 target mode c onfiguration loading on completion of the target mode request , the target mode co nfiguration from the me_ _mc register is loaded to st art the resources (voltage sour ces, clock sources, flashes, pads, etc.) co ntrol process. an overview of resource control possibi lities for each mode is shown in table 8-12 . a ?? indicates that a given resource is configurable for a given mode. table 8-12. mc_me resource control overview resource mode reset test safe drun run0 halt stop standby firc ? ?? ? on on on on on on on on cflash ? ???? normal normal normal normal normal low-power power- down power- down dflash ? ???? normal normal normal normal normal low-power power- down power- down mvreg ?? on on on on on on on off
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 169 8.4.3.3 peripheral clocks disable on completion of the target mode request , the mc_me requests each peripheral to enter its stop mode when: the mc_me does not automatically reque st peripherals to enter their stop modes if the power domains in which th ey are residing are to be turned off due to a mode change. therefore, it is software?s responsibility to ensure that those peripherals that are to be powered down are configured in the mc_me to be frozen. each peripheral that may block or disrupt a communication bus to which it is connected ensures that these outputs are forced to a safe or recessive st ate when the device enters the safe mode. 8.4.3.4 processor low-power mode entry if, on completion of the peripheral clocks disable , the mode transition is to the halt mode, the mc_me requests the processor to enter its halted state. th e processor acknowledges its halt state request after completing all outstandi ng bus transactions. if, on completion of the peripheral clocks disable , the mode transition is to the stop mode, the mc_me requests the processor to enter its stopped state. th e processor acknowledges its stop state request after completing all outstandi ng bus transactions. 8.4.3.5 processor and syst em memory clock disable if, on completion of the processor low-power mode entry , the mode transition is to the halt stop mode and the processor is in its approp riate halted or stopped state, the mc_me disables the processor and system memory clocks to achieve further power saving. the clocks to the processor and system memories are unaffected for all transitions between software running modes including drun, run0?3, and safe. caution clocks to the whole device including the processor and system memories can be disabled in test mode. pdo ?? ? off off on off off off off on table 8-12. mc_me resource control overview (continued) resource mode reset test safe drun run0 halt stop standby
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 170 freescale semiconductor 8.4.3.6 clock sources switch-on on completion of the processor low-power mode entry , the mc_me controls all cl ock sources that affect the system clock based on the on bits of the me_ _mc and me_ _mc registers. the following system cloc k sources are controlled at this step: ? the fast internal rc oscillator (16 mhz) the clock sources that are required by the target mode are switched on. the duration required for the output clocks to be stable depends on the type of source, a nd all further steps of mode transition depending on one or more of these clocks waits for the stable st atus of the respective clocks . the availability status of these system clocks is updated in the s_ bits of me_gs register. the clock sources that need to be switched off are unaffected during th is process in order to not disturb the system clock, which might require one of these clocks befo re switching to a di fferent target clock. it is also possible to automatically switch-on th e fxosc after exiting standby mode, by programming me_drun_mc[fxosc] = 1 prior to standby entry. after the ch ip exits standby mode, your software should wait for fxosc to be switched-on befo re any mode transition request in order to avoid a mode request illegal event. 8.4.3.7 main voltage regulator switch-on on completion of the target mode request , if the main voltage regulator ne eds to be switched on from its off state based on the mvron bit of the me_ _mc and me_ _mc registers, the mc_me requests the mc_pcu to power -up the regulator and waits for the output voltage stable status in order to update th e s_mvr bit of the me_gs register. this step is required only during the exit of the lo w-power modes halt and stop. in this step, the fast internal rc oscillator (16 mhz) is switched on regard less of the target mode c onfiguration, as the main voltage regulator requires the 16 mhz in t. rc osc. during power-up in orde r to generate the voltage status. 8.4.3.8 flash modules switch-on on completion of the main voltage regulator switch-on , if a flash module needs to be switched to normal mode from its low-power or power-down mode ba sed on the cflaon and df laon bit fields of the me_ _mc and me_ _mc registers, the mc_me requests the flash to exit from its low-power/power-down mode . when the flash modules are avai lable for access, the s_cfla and s_dfla bit fields of the me_gs regi ster are updated to 11 by hardware. if the main regulator is also off in device low-power modes, then during the exit sequence, the flash is kept in its low-power state and is switched on only when the main voltage regulator switch-on process has completed. caution it is illegal to switch the flashes from low-power mode to power-down mode and from power-down mode to low- power mode. the mc_me, however, does not prevent this nor does it flag it.
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 171 8.4.3.9 pad outputs-on on completion of the main voltage regulator switch-on , if the pdo bit of the me_ _mc register is cleared, then ? all pad outputs are enabled to return to their previous state ? the i/o pads power sequence driver is switched on 8.4.3.10 processor and memory clock enable if the mode transition is from any of the low-power modes halt or st op to run0?3, the clocks to the processor and system memories are enabled. the pro cess of enabling these clocks is executed only after the flash modules switch-on process is completed. 8.4.3.11 processor low-power mode exit if the mode transition is from any of the low-power modes haltstop to run0?3, the mc_me requests the processor to exit from its halted or stopped state. this step is executed only after the processor and memory clock enable process is completed. 8.4.3.12 system clock switching based on the sysclk bit field of the me_ _mc and me_ _mc registers, if the target and current system cl ock configurations differ, the follow ing method is implemented for clock switching. ? the target clock configuration for the 16 mhz int. rc osc. is effective only when the s_firc bit of the me_gs register is set by hardware (i.e. the fast internal rc oscillator (16 mhz) has stabilized). ? if the clock is to be disabled, the sysclk b it field should be programmed with 1111. this is possible only in the test mode. the current system clock configurat ion can be observed by reading the s_sysclk bit field of the me_gs register, which is updated afte r every system clock switch ing. until the target clock is available, the system uses the previous clock configuration. system clock switchi ng starts only after ? the clock sources switch-on process has completed if the target system clock sour ce needs to be switched on an overview of system clock source select ion possibilities for each mode is shown in table 8-13 . a ?? indicates that a given clock source is selectable for a given mode.
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 172 freescale semiconductor 8.4.3.13 pad switch-off if the pdo bit of the me_ _mc register is 1 then ? the outputs of the pads are forced to the high impedance state if the target mode is safe or test this step is executed only after the peripheral clocks disable process is completed. 8.4.3.14 clock sources switch-off if a given clock source . this step is executed only after ? system clock switching process is completed in order not to lose the current system clock during mode transition. 8.4.3.15 flash switch-off based on the cflaon and dflaon bit fields of the me_ _mc and me_ _mc registers, if any of the flash modules is to be put in a low-power state, the mc_me requests the flash to enter the corresponding low-power state and waits for the deassertion of flash ready status signal. the exact low-power mode status of the flash modules is updated in the s_cfla and s_dfla bit fields of the me_gs regi ster. this step is executed only when processor and system memory clock disable process is completed. 8.4.3.16 main voltage regulator switch-off based on the mvron bit of the me_ _mc and me_ _mc registers, if the main voltage regulator is to be switched off, the mc_me requests it to power down and clears the availability status bit s_mvr of the me_gs register. this step is required only during the entry of low-power modes like halt and stop. this step is executed only after completing the following processes: ? flash switch-off table 8-13. mc_me system clock selection overview system clock source mode reset test safe drun run0 halt stop standby 16 mhz int. rc osc. ? (default) ? (default) ? (default) ? (default) ? (default) ? (default) ? (default) system clock is disabled ? ? 1 disabling the system clock during test mode will require a reset in order to exit test mode ?? (default)
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 173 ? the device consumption is less than the predefined threshold value (i.e. the s_dc bit of the me_gs register is 0). 8.4.3.17 current mode update the current mode status bit fiel d s_current_mode of the me_gs regi ster is updated with the target mode bit field target_mode of the me_mctl register when: ? all the updated status bits in the me_gs regi ster match the configuration specified in the me_ _mc register ? power sequences are done ? clock disable/enable process is finished ? processor low-power mode (halt/stop) entry and exit processes are finished software can monitor the mode transition status by reading the s_mtrans bit of the me_gs register. the mode transition latency can diff er from one mode to a nother depending on the re sources? availability before the new mode request and the target mode?s requirements.
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 174 freescale semiconductor figure 8-16. mc_me transition diagram power domain switch-on power domain switch-off pll switch-on pll switch-off target standby standby request ny main vreg switch-off end target mode request write me_mctl register safe mode request interrupt/wakeup event peripheral clocks disable clock sources switch-on system clock switching main vreg switch-on flash switch-on pad processor low-power processor & pad peripheral clocks enable flash switch-off clock sources switch-off s_mtrans = 1 analog on digital control analog off current mode update start s_mtrans = 0 outputs -on outputs -off entry processor low-power exit clock disable memory processor & clock enable memory
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 175 8.4.4 protection of mode configuration registers while programming the mode c onfiguration registers me_ _mc, the following rules must be respected. otherwise, the write opera tion is ignored and an invalid mode configuration interrupt may be generated. ? firc must be on if the system clock is one of the following: ? the 16 mhz int. rc osc. ? the configuration 00 for the cflaon and dflaon bit fields are reserved. ? mvreg must be on if any of the following is active: ?cflash ?dflash ? system clock configurations marked as reserved may not be selected. ? configuration 1111 for the sysclk bit field is allowed only for th e test mode, and only in this case may all system clock sources be turned off. caution if the system clock is stopped duri ng test mode, the device can exit only via a system reset. 8.4.5 mode transition interrupts the following are the three interrupts related to mode transition impl emented in the mc_me. 8.4.5.1 invalid mode configuration interrupt whenever a write operation is attempted to the me_ _mc registers violating the protection rules mentioned in the section 8.4.4, protection of mode configuration registers , the interrupt pending bit i_iconf of the me_is regist er is set, and an interr upt request is generated if the mask bit m_iconf of me_im register is 1. 8.4.5.2 invalid mode transition interrupt the mode transition request is consider ed invalid under the following conditions: ? if the system is in the safe mode and the sa fe mode request from mc_r gm is active, and if the target mode requested is other than reset or safe, then this new mode request is considered to be invalid, and the s_sea bit of the me_imts register is set. ? if the target_mode bit field of the me_mctl re gister is written with a value different from the specified mode values (i.e. a non existing mode), an invalid mode transitio n event is generated. when such a non existing mode is requested, the s_ nma bit of the me_imts re gister is set. this condition is detected regardless of whether the proper key mechan ism is followed while writing the me_mctl register. ? if some of the device modes ar e disabled as programmed in th e me_me register, their respective configurations are considered reserved, and a ny access to the me_mctl register with those values results in an invalid mode transition reques t. when such a disabled mode is requested, the
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 176 freescale semiconductor s_dma bit of the me_imts register is set. this condition is detected re gardless of whether the proper key mechanism is followed while writing the me_mctl register. ? if the target mode is not a valid mode with respect to current mode , the mode request illegal status bit s_mri of the me_imts register is set. this condition is detected only when the proper key mechanism is followed while writing the me_mc tl register. otherwise, the write operation is ignored. ? if further new mode requests occu r while a mode transition is in progress (the s_mtrans bit of the me_gs register is 1), the mode transition illegal stat us bit s_mti of the me_imts register is set. this condition is detected only when the proper key mechanis m is followed while writing the me_mctl register. otherwise, the write operation is ignored. note as the causes of invalid mode transiti ons may overlap at the same time, the priority implemented for invalid m ode transition status bits of the me_imts register in the order from hi ghest to lowest is s_sea, s_nma, s_dma, s_mri, and s_mti. as an exception, the mode transition request is not considered as invalid under the following conditions: ? a new request is allowed to enter the reset or safe mode irrespective of the mode transition status. ? as the exit of halt and stop modes depends on the interrupts of the system, which can occur at any instant, these requests to return to run0?3 modes are always valid. ? in order to avoid any unwanted lockup of the devi ce modes, software can abort a mode transition by requesting the parent mode if , for example, the mode transi tion has not completed after a software determined reasonable am ount of time for whatever reason. the parent mode is the device mode before a valid m ode request was made. ? self-transition requests (e.g. run0 ? run0) are not considered as invalid even when the mode transition process is active (i.e. s_mtrans is 1). during the low-po wer mode exit process, if the system is not able to enter the respective run0?3 mode properly (i.e . all status bits of the me_gs register match with confi guration bits in the me_ _mc register), then software can only request the safe or reset mode. it is not possible to request any ot her mode or to go back to the low-power mode again. whenever an invalid mode request is detected, the interrupt pending bi t i_imode of the me_is register is set, and an interrupt request is generated if the mask bit m_imode is me_im register is 1. 8.4.5.3 safe mode transition interrupt whenever the system enters the safe mode as a re sult of a safe mode reque st from the mc_rgm due to a hardware failure, the interrupt pending bit i_safe of the me_is register is set, and an interrupt is generated if the mask bit m_sa fe of me_im register is 1. the safe mode interrupt pending bit can be cleared only when the safe mode request is deasserted by the mc_rgm (see chapter 9, reset genera tion module (mc_rgm) , for details on how to clear a safe mode request). if the system is already in safe mode, any new safe mode request by the mc_rgm
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 177 also sets the interrupt pending bit i_ safe. however, the safe mode inte rrupt pending bit is not set when the safe mode is entered by a software re quest (i.e. programming of me_mctl register). 8.4.5.4 mode transition complete interrupt whenever the system completes a mode transition fully (i.e. the s_mtrans bit of me_gs register transits from 1 to 0), the interrupt pending bit i_mtc of the me_is register is set, and interrupt request is generated if the mask bit m_mtc of the me_im regist er is 1. the interrupt bit i_mtc is not set when entering low-power modes halt and stop in order to avoid the same event requesting the exit of these low-power modes. 8.4.6 application example figure 8-17 shows an example application flow for requesting a mode chan ge and then waiting until the mode transition has completed.
chapter 8 mode entry module (mc_me) MPC5606BK microcontroller reference manual, rev. 2 178 freescale semiconductor figure 8-17. mc_me application example flow diagram start of mode change config for target mode okay? write me_ _mc register n y write me_mctl with target mode and key write me_mctl with target mode and inverted key start timer s_mtrans cleared? y timer expired? n y n write me_mctl with current or safe mode and key write me_mctl with current or safe mode and inverted key stop timer mode change done
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 179 chapter 9 reset generation module (mc_rgm) 9.1 introduction 9.1.1 overview the reset generation module (mc_rgm) centralizes the different rese t sources and manages the reset sequence of the device. it provides a register interface and the reset sequencer . the different registers are available to monitor and control the device reset seque nce. the reset sequencer is a state machine that controls the different phases (phase0, phase1, ph ase2, phase3, and idle) of the reset sequence and control the reset signals generated in the system. figure 9-1 shows the mc_rgm block diagram.
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 180 freescale semiconductor figure 9-1. mc_rgmblock diagram 9.1.2 features the mc_rgm contains the functiona lity for the following features: ? destructive resets management ? functional resets management ? signalling of reset events after each reset sequence (reset status flags) ? conversion of reset events to safe mode or interrupt request events chapter 8, mode entry module (mc_me) ? short reset sequence configuration pa[8] and pa[9] reset registers platform interface core mc_rgm mc_me power-on functional reset filter boot mode capture destructive reset filter reset state machine sscm peripherals mc_cgm
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 181 ? bidirectional reset be havior configuration ? chapter 8, mode entry module (mc_me) boot mode capture on reset deassertion 9.1.3 modes of operation the different reset sources are organized in to two families: destructive and functional. ? a destructive reset source is asso ciated with an event related to a critical?usually hardware?error or dysfunction. when a destructive reset event occu rs, the full reset sequence is applied to the device starting from phase0. this resets the fu ll device ensuring a safe start-up state for both digital and analog modules. destructive resets are ? power-on reset ? a functional reset source is associated with an event related to a less-critical?usually non-hardware?error or dysfunction. wh en a functional reset event oc curs, a partial reset sequence is applied to the device starti ng from phase1. in this case, most digital modules are reset normally, while analog modules or specific di gital modules? (e.g. debug modules, flash modules) state is preserved. functional resets are ? external reset when a reset is triggered, the mc_rgm state mach ine is activated and proceeds through the different phases (i.e. phase n states). each phase is associated with a particular device reset being provided to the system. a phase is completed when all corresponding phase completion ga tes from either the system or internal to the mc_rgm are acknowledged. the device re set associated with the phase is then released, and the state machine proceeds to the next phase up to entering the idle phase. du ring this entire process, the mc_me state machine is held in reset mode. only at the end of the reset sequence, when the idle phase is reached, does the mc_me enter the drun mode. alternatively, it is possibl e for software to configure some reset source events to be converted from a reset to either a safe mode request issued to the mc _me or to an interrupt issued to the core (see section 9.3.1.4, destructive event rese t disable register (rgm_derd) , and section 9.3.1.6, destructive event alternate request register (rgm_dear) , for destructive resets, and section 9.3.1.3, functional event reset disable register (rgm_ferd) , and section 9.3.1.5, functional event alternate request register (rgm_fear) , for functional resets). 9.2 external signal description the mc_rgm interfaces to the reset pin re set and the boot mode pins pa[8] and pa[9].
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 182 freescale semiconductor 9.3 memory map and register definition note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content ? cause a transfer error table 9-1. mc_rgm register description address name description size access location normal supervisor test 0xc3fe _4000 rgm_fes functional event status half-word read read/write 1 read/write 1 on page 207 0xc3fe _4002 rgm_des destructive event status half-word read read/write 1 1 individual bits cleared on writing 1 read/write 1 on page 208 0xc3fe _4004 rgm_ferd functional event reset disable half-word read read read on page 209 0xc3fe _4006 rgm_derd destructive event reset disable half-word read read read on page 211 0xc3fe _4010 rgm_fear functional event alternate request half-word read read read on page 212 0xc3fe _4012 rgm_dear destructive event alternate request half-word read read read on page 213 0xc3fe _4018 rgm_fess functional event short sequence half-word read read read on page 214 0xc3fe _401c rgm_fbre functional bidirectional reset enable half-word read read/write read/write on page 216 table 9-2. mc_rgm memory map 0xc3fe _4000 rgm_ fes / rgm_ des r f_exr 000000 chkstop ww1c r f_por 0000000000 ww1c
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 183 9.3.1 register descriptions unless otherwise noted, all registers may be accessed as 32-bit word s, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. for ex ample, the rgm_stdby regi ster may be accessed as a word at address 0xc3fe_4018, as a half-word at address 0xc3fe_401a, or as a byte at address 0xc3fe_401b. 0xc3fe _4004 rgm_ ferd / rgm_ derd r d_exr 000000 chkstop w r00000000000 w 0xc3fe _4008 ? 0xc3fe _400c reserved 0xc3fe _4010 rgm_ fear / rgm_ dear r ar_exr 000000 chkstop w r00000000000 w 0xc3fe _4014 reserved 0xc3fe _4018 rgm_ fess r ss_exr 000000 chkstop w 0xc3fe _401c rgm_ fbre r be_exr 000000 chkstop w 0xc3fe _4020 ? 0xc3fe _7ffc reserved table 9-2. mc_rgm memory map (continued)
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 184 freescale semiconductor 9.3.1.1 functional event status register (rgm_fes) this register contains the st atus of the last asserted f unctional reset sources . it can be accessed in read/write on either supervisor mode or test mode . register bits are cleared on write 1. 9.3.1.2 destructive event status register (rgm_des) this register contains the status of the last asserted destructive re set sources. it can be accessed in read/write on either supervisor mode or test mode. register bits are cleared on write 1. note the f_por flag is also set when a low-voltage is detected on the 1.2 v supply, even if the low voltage is detected after power-on has completed. address 0xc3fe_4000 access: user read, supervisor read/write, test read/write r f_exr 000000 chkstop ww1c por0000000000000000 figure 9-2. functional event status register (rgm_fes) table 9-3. functional event status register (rgm_fes) field descriptions field description f_exr flag for external reset 0 no external reset event has occurred since either the last clear or the last destructive reset assertion 1 an external reset event has occurred address 0xc3fe_4002 access: user read, supervisor read/write, test read/write r f_por 0000000000 ww1c por1000000000000000 figure 9-3. destructive event status register (rgm_des) table 9-4. destructive event status register (rgm_des) field descriptions field description f_por flag for power-on reset 0 no power-on event has occurred since the last clear (due to either a software clear or a low-voltage detection) 1 a power-on event has occurred
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 185 the f_lvd27 flag may still have the va lue 0 after a dip has occurred on the 2.7 v supply during a n on-monotonic power-on sequence. the f_por flag will, however, still be set in this case as expected after each power-on sequence. in contrast to all other reset sources, the 1.2 v low- voltage detected (power domain #0) event is captured on its deas sertion. therefore, the status bit f_lvd12_pd0 is also asserted on the reset?s deassertion. in case an alternate event is selecte d, the safe mode or interr upt request are similarly asserted on the reset?s deassertion. 9.3.1.3 functional event reset disable register (rgm_ferd) this register provides dedicated bits to disable functional reset source s.when a functional reset source is disabled, the associated functional ev ent will trigger either a safe mode request or an interrupt request (see section 9.3.1.5, functional event altern ate request regi ster (rgm_fear) ). it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read only in user mode. each byte can be written only on ce after power-on reset. 9.3.1.4 destructive event reset disable register (rgm_derd) address 0xc3fe_4004 access: user read, supervisor read, test read r d_exr 000000 chkstop w por0000000000000000 figure 9-4. functional event reset disable register (rgm_ferd) table 9-5. functional event reset disable register (rgm_ferd) field descriptions field description d_exr disable external reset 0 an external reset event triggers a reset sequence 1 an external reset event generates a safe mode request address 0xc3fe_4006 access: read r00000000000 w por0000000000000000 figure 9-5. destructive event reset disable register (rgm_derd)
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 186 freescale semiconductor this register provides dedicated bits to disable particular destructiv e reset sources. when a destructive reset source is disabled, the associated destructive ev ent will trigger either a safe mode request or an interrupt request (see section 9.3.1.6, destructive event altern ate request regi ster (rgm_dear) ). 9.3.1.5 functional event alternate request register (rgm_fear) this register defines an alternat e request to be generated when a reset on a functional event has been disabled. the alternate reque st can be either a safe mode request to mc_me or an interrupt request to the system. it can be accessed in read /write in either supervisor mode or test mode. it can be accessed in read only in user mode. 9.3.1.6 destructive event alternate request register (rgm_dear) this register defines an alternate request to be generated when a re set on a destructive event has been disabled. the alternate reque st can be either a safe mode request to mc_me or an interrupt request to the system. address 0xc3fe_4010 access: user read, supervisor read, test read r ar_exr 000000 chkstop w por0000000000000000 figure 9-6. functional event alternate request register (rgm_fear) table 9-7. functional event alternate request register (rgm_fear) field descriptions field description ar_exr alternate request for external reset 0 generate a safe mode request on an external reset event if the reset is disabled 1 generate an interrupt request on an external reset event if the reset is disabled address: 0xc3fe_4012 access: read r00000000000 w por0000000000000000 figure 9-7. destructive event alternate request register (rgm_dear)
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 187 9.3.1.7 functional event short sequence register (rgm_fess) this register defines whic h reset sequence will be do ne when a functional reset sequence is triggered. the functional reset sequence can either start from phase1 or from phase3, skipping phase1 and phase2. note this could be useful for fast reset se quence, for example to skip flash reset. it can be accessed in read/write in ei ther supervisor mode or test mode. it can be accessed in read in user mode. note this register is reset on any enabled destructive or functional reset event. 9.3.1.8 functional bidirectional reset enable register (rgm_fbre) this register enables the ge neration of an external rese t on functional reset. it can be accessed in read/write in either supervisor mode or test mode. it can be accessed in read in user mode. address 0xc3fe_4018 access: user read, supervisor read, test read r ss_exr 000000 chkstop w por0000000000000000 figure 9-8. functional event shor t sequence register (rgm_fess) table 9-9. functional event short sequence register (rgm_fess) field descriptions field description ss_exr short sequence for external reset 0 the reset sequence triggered by an external reset event will start from phase1 1 the reset sequence triggered by an external reset event will start from phase3, skipping phase1 and phase2 address 0xc3fe_401c access: user read, supervisor read/write, test read/write r be_exr 000000 chkstop w por0000000000000000 figure 9-9. functional bidirectional reset enable register (rgm_fbre)
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 188 freescale semiconductor 9.4 functional description 9.4.1 reset state machine the main role of mc_rgm is the ge neration of the reset sequence, which ensures that the correct parts of the device are reset based on the reset source event. this is summarized in table 9-11 note jtag logic has its own independent rese t control and is not controlled by the mc_rgm in any way. the reset sequence is comprised of five phases managed by a state machin e, which ensures that all phases are correctly processed thr ough waiting for a minimum dur ation and until al l processes that need to occur during that phase have been completed before proceeding to the next phase. the state machine used to produce the reset sequence is shown in figure 9-10 . table 9-10. functional bidirectional reset enable register (rgm_fbre) field descriptions field description be_exr bidirectional reset enable for external reset 0 reset is asserted on an external reset event if the reset is enabled 1 reset is not asserted on an external reset event table 9-11. mc_rgm reset implications source what gets reset external reset assertion boot mode capture power-on reset all yes yes destructive reset all except some clock/reset management yes yes external reset all except some clock/reset management and debug ye s ye s functional resets all except some clock/reset management and debug programmable 1 1 the assertion of the external reset is controlled via the rgm_fbre register programmable 2 2 the boot mode is captured if the external reset is asserted shortened functional resets 3 3 the short sequence is enabled via the rgm_fess register flip-flops except some clock/reset management programmable 1 programmable 2
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 189 x figure 9-10. mc_rgm state machine figure 9-11 describes how the device behaves during the startup. phase0 phase1 phase2 phase3 idle duration ? 3 fast internal rc osc illator (16 mhz) clock cycles firc stable, vreg voltage okay done duration ? 10 fast internal rc osci llator (16 mhz) clock cycles duration ????? fast internal rc oscillator (16 mhz) clock cycles code and data flash initialization done duration ?? 40 ? fast internal rc oscilla tor (16 mhz) clock cycles code and data flash initialization done fast internal rc oscillator (16 mhz) clock is running power-up has completed power-on reset enabled non-shortened externalreset 1 enabled shortened externalfunctio nal reset code and data flash initialization done reset released
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 190 freescale semiconductor figure 9-11. reset c onfiguration timing 9.4.1.1 phase0 phase this phase is entered immediately from any phase on a power-on or enab led destructive reset event. the reset state machine exits phase0 and enters phase1 on verification of the following: ? power-up has completed ? fast internal rc oscillator (16 mhz) clock is running ? all enabled destructive resets have been processed ? all processes that need to be done in phase0 are completed ? a minimum of 3 fast internal rc oscillator (16 mhz) clock cycles have elapsed since power-up completion and the last enabled destructive reset event 9.4.1.2 phase1 phase this phase is entered either on exit from phase0 or immediately from phase2, phase3, or idle on a non-masked external or functional reset event if it has not been conf igured to trigger a short sequence. the reset state machine exits phase1 and ente rs phase2 on verificat ion of the following: ? all enabled, non-shortened functiona l resets have been processed ? a minimum of 10 fast internal rc oscillator (16 mhz) clock cycles have elapsed since the last enabled external or non-shor tened functional reset event
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 191 9.4.1.3 phase2 phase this phase is entered on exit from phase1. the rese t state machine exits phase2 and enters phase3 on verification of the following: ? all processes that need to be done in phase2 are completed ? a minimum of 8 fast internal rc oscillator (16 mhz) clock cy cles have elapsed since entering phase2 9.4.1.4 phase3 phase this phase is a entered either on exit from phase2 or immediately from idle on an enabled, shortened functional reset event. the reset state machine ex its phase3 and enters id le on verification of the following: ? all processes that need to be done in phase3 are completed ? a minimum of 40 fast internal rc oscillator (16 mhz) clock cycles have elapsed since the last enabled, shortened functional reset event 9.4.1.5 idle p hase this is the final phase, and is entered on exit from phase3. when this phase is reached, the mc_rgm releases control of the system to the platform and waits for new reset events that can trigger a reset sequence. 9.4.2 destructive resets a destructive reset indicates that an event has occurred, after which critical regist er or memory content can no longer be guaranteed. the status flag associated with a gi ven destructive reset event (rgm_des.f_ bit) is set when the destructive reset is asserted and the power -on reset is not asserted. it is possible for multiple status bits to be set simultaneously , and it is software?s responsibility to determine which reset source is the most critical for the application. the destructive reset can be optionall y disabled by writing bit rgm_derd.d_ . note the rgm_derd register can be wr itten only once between two power-on reset events. the device?s low-voltage detector threshold ensures that, when 1.2 v lo w-voltage detected (power domain #0) is enabled, the supply is sufficie nt to have the destruct ive event correctly propagated through the digital logic. therefore, if a gi ven destructive reset is enabled, the mc_rgm ensures that the associated reset event will be correctly triggered to the full system. ho wever, if the given destruct ive reset is disabled and the voltage goes below the digital functional thres hold, functionality can no l onger be ensured, and the reset may or may not be asserted. an enabled destructive reset will trigger a reset sequence starting from the beginning of phase0 .
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 192 freescale semiconductor 9.4.3 external reset the mc_rgm manages the external reset coming from reset. the det ection of a falling edge on reset will start the reset sequence from the beginning of phase1. the status flag associated with the external reset falling edge event (rgm_fes .f_exr bit) is set when the external reset is asserted and the power-on reset is not asserted. the external reset can optionally be di sabled by writing bit rgm_ferd.d_exr. note the rgm_ferd register can be wr itten only once between two power-on reset events. an enabled external reset will normally trigger a reset sequence starting from the beginning of phase1. nevertheless, the rgm_fess register enables the furt her configuring of the re set sequence triggered by the external reset. when rgm_fess.ss_exr is set, the external reset will trigger a reset sequence starting directly from the beginning of phase3, sk ipping phase1 and phase2. this can be useful especially when an external reset should not reset the flash. 9.4.4 functional resets a functional reset indicates th at an event has occurred, af ter which it can be guaranteed that critical register and memory content is still intact. the status flag associated with a gi ven functional reset event (rgm_fes.f_ bit) is set when the functional reset is asserted and the power-on reset is not asserted. it is possible for multiple status bits to be set simultaneously , and it is software?s responsibility to determine which reset source is the most critical for the application. the functional reset can be optionall y disabled by software writing bit rgm_ferd.d_ . note the rgm_ferd register can be wr itten only once between two power-on reset events. an enabled functional reset will nor mally trigger a reset sequence star ting from the beginning of phase1. nevertheless, the rgm_fess register enables the furt her configuring of the re set sequence triggered by a functional reset. when rgm_fess.ss_ is set, the associated functional reset will trigger a reset sequence starting di rectly from the beginning of phas e3, skipping phase1 and phase2. this can be useful especially in case a f unctional reset should not reset the flash module. see chapter 8, mode entry module (mc_me) , for details on the st andby and drun modes. 9.4.5 alternate event generation the mc_rgm provides alternative events to be genera ted on reset source asserti on. when a reset source is asserted, the mc_rgm normally enters the reset seque nce. alternatively, it is possible for each reset
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 193 source event (except the power-on reset event) to be converted from a rese t to either a safe mode request issued to the mc_me or to an interrupt request issued to the core. alternate event selection for a given reset source is made via the rgm_f/derd and rgm_f/dear registers, as shown in table 9-12 . the alternate event is cleared by deasse rting the source of the re quest (that is, at the re set source that caused the alternate request) and also cleari ng the appropriate rgm_f/des status bit. note alternate requests (safe m ode as well as interrupt requests) are generated asynchronously. note if a masked destructive reset event that is configured to generate a safe mode/interrupt request occurs duri ng phase0, it is ignored, and the mc_rgm will not send any safe mode /interrupt request to the mc_me. the same is true for masked functional reset events during phase1. 9.4.6 boot mode capturing the mc_rgm samples pa[9:8] whenever reset is asserted until five fi rc (16 mhz internal rc oscillator) clock cycles before its deassertion edge. the resu lt of the sampling is us ed at the beginning of reset phase3 for boot mode selectio n and is retained after reset has been deasserted for subsequent boots after reset sequences during which reset is not asserted. note in order to ensure that the boot mode is correctly captured, the application needs to apply the valid boot mode va lue the entire time that reset is asserted. reset can be asserted as a conseque nce of the internal reset generation. this will force re-sampling of the boot mode pins. (see table 9-11 for details.) table 9-12. mc_rgm alternate event selection rgm_f/derd bit value rgm_f/dear bit value generated event 0 x reset 1 0 safe mode request 1 1 interrupt request
chapter 9 reset generation module (mc_rgm) MPC5606BK microcontroller reference manual, rev. 2 194 freescale semiconductor this page is intent ionally left blank.
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 195 chapter 10 power control unit (mc_pcu) 10.1 introduction 10.1.1 overview the power control unit (mc_pcu) is used to reduc e the overall soc power consumption. power can be saved by disconnecting parts of the soc from the pow er supply via a power switc hing device. the soc is grouped into multiple parts having this ca pability, which are called power domains. when a power domain is disconnected from the supply, the power consumpt ion is reduced to zero in that domain. any status informat ion of such a power domai n is lost. when reconnec ting a power domain to the supply voltage, the domain draws an increased current until the power domain reaches its operational voltage. power domains are controlled on a device mode basi s. for each mode, software can configure whether a power domain is connected to the supply voltage (power-up state) or disconnected (power-down state). maximum power saving is reache d by entering the standby mode. on each mode change request, the mc_pcu evalua tes the power domain settings in the power domain configuration registers and initia tes a power-down or a power-up sequence for each individual power domain. the power-up/down sequences are handled by fini te state machines to ensure a smooth and safe transition from one power state to the other. exiting the standby mode can only be done via a system wakeup event as all power domains other than power domain #0 are in the power-down state. in addition, the mc_pcu acts as a bridge for mapping the vreg pe ripheral to the mc_pcu address space. figure 10-1 shows the mc_pcu block diagram.
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 196 freescale semiconductor figure 10-1. mc_pcu block diagram 10.1.2 features the mc_pcu includes the following features: ? support for 1012345789 power domains ? support for device modes reset, drun, safe, test, run0?3, halt, stop, and standby (for further m ode details, please see) ? power states updating on each mode change and on system wakeup ? a handshake mechanism for power state changes thus guarant eeing operable voltage 10.1.3 modes of operation the mc_pcu is available in all device modes. mc_me firc vreg wkpu power domains power domain state machines registers platform interface mc_pcu core
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 197 10.2 external signal description the mc_pcu has no connections to any external pins . 10.3 memory map and register definition note any access to unused registers as we ll as write accesses to read-only registers will: ? not change register content table 10-1. mc_pcu register description address name description size access location normal supervisor test 0xc3fe _8000 pcu_pconf0 power domain #0 configuration word read read read on page 199 0xc3fe _8004 pcu_pconf1 power domain #1 configuration word read read read on page 200 0xc3fe _8008 pcu_pconf2 power domain #2 configuration word read read/write read/write on page 201on page 201 0xc3fe _800c pcu_pconf3 power domain #3 configuration word read read/write read/write on page 201 0xc3fe _8010 pcu_pconf4 power domain #4 configuration word read read/write read/write on page 201 0xc3fe _8014 pcu_pconf5 power domain #5 configuration word read read/write read/write on page 201 0xc3fe _8018 pcu_pconf6 power domain #6 configuration word read read/write read/write on page 201 0xc3fe _801c pcu_pconf7 power domain #7 configuration word read read/write read/write on page 201 0xc3fe _8020 pcu_pconf8 power domain #8 configuration word read read/write read/write on page 201 0xc3fe _8024 pcu_pconf9 power domain #9 configuration word read read/write read/write on page 201 0xc3fe _8028 pcu_pconf10 power domain #10 configuration word read read/write read/write on page 201 0xc3fe _802c pcu_pconf11 power domain #11 configuration word read read/write read/write on page 201 0xc3fe _8030 pcu_pconf12 power domain #12 configuration word read read/write read/write on page 201 0xc3fe _8040 pcu_pstat power domain status register word read read read on page 202
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 198 freescale semiconductor ? cause a transfer error table 10-2. mc_pcu memory map 0xc3fe _8000 pcu_pconf0 r0000000000000000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe _8004 pcu_pconf1 r0000000000000000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe _8008 pcu_pconf2101 2456789 r0000000000000000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe _800c pcu_pconf1012 3456789 r0000000000000000 w r0 0 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w 0xc3fe _800123 048c ? 0xc3fe _803c reserved 0xc3fe _8040 pcu_pstat r0000000000000000 w r000000000000 pd3 pd2 pd1 pd0 w 0x044 ? 0x07c reserved
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 199 10.3.1 register descriptions all registers may be accessed as 32-bit words, 16-bit half-words, or 8-bit bytes. the bytes are ordered according to big endian. fo r example, the pd0 field of the pcu_psta t register may be accessed as a word at address 0xc3fe_8040, as a half-word at address 0xc3fe_8042, or as a byte at address 0xc3fe_8043. 10.3.1.1 power domain #0 configuration register (pcu_pconf0) this register defines for power dom ain #0 whether it is on or off in each device mode. as power domain #0 is the always-on power domain (and includes the mc _pcu), none of its bits are programmable. this register is available for completeness reasons. 0xc3fe _8080 ? 0xc3fe _80fc 0xc3fe _8100 ? 0xc3fe _bffc reserved address 0xc3fe_8000 access: user read, supervisor read, test read r0000000000000000 w reset0000000000000000 r 00 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0010010111111111 figure 10-2. power domain #0 conf iguration register (pcu_pconf0) table 10-3. power domain configur ation register field descriptions field description rst power domain control during reset mode 0 power domain off 1 power domain on test power domain control during test mode 0 power domain off 1 power domain on table 10-2. mc_pcu memory map (continued)
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 200 freescale semiconductor 10.3.1.2 power domain #1 configuration register (pcu_pconf1) this register defines for power domain #1 whether it is on or off in each device mode. the bit field description is the same as in table 10-3 . as the platform, clock generati on, and mode control reside in safe power domain control during safe mode 0 power domain off 1 power domain on drun power domain control during drun mode 0 power domain off 1 power domain on run0 power domain control during run0 mode 0 power domain off 1 power domain on run1 power domain control during run1 mode 0 power domain off 1 power domain on run2 power domain control during run2 mode 0 power domain off 1 power domain on run3 power domain control during run3 mode 0 power domain off 1 power domain on halt power domain control during halt mode 0 power domain off 1 power domain on stop power domain control during stop mode 0 power domain off 1 power domain on stby0 power domain control during standby mode 0 power domain off 1 power domain on address 0xc3fe_8004 access: user read, supervisor read, test read r0000000000000000 w reset0000000000000000 r 00 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0000010111111111 figure 10-3. power domain #1 conf iguration register (pcu_pconf1) table 10-3. power domain configuration register field descriptions (continued) field description
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 201 power domain #1, this power domai n is only powered down during the standby mode. therefore, none of the bits is programmable. this regist er is available for completeness reasons. the difference between pcu_pconf0 and pcu_pconf1 is the reset value of the stby0 bit: during the standby mode, power domain #1 is disconn ected from the power supply, and therefore pcu_pconf1.stby0 is always 0. power domain #0 is always on, a nd therefore pcu_pconf0.stby0 is 1. for further details about standby mode, please see section 10.4.4.2, standby mode transition . 10.3.1.3 power domain #2 configuration register (pcu_pconf2) this register defines for power domain #2 whether it is on or off in each device mode. the bit field description is the same as in table 10-3 . 10.3.1.4 power domain #2?101234 56789 configuration registers (pcu_pconf2?10123456789) address 0xc3fe_8008 access: user read/write, su pervisor read/write, test read/write r0000000000000000 w reset0000000000000000 r 00 stby0 00 stop0 0 halt0 run3 run2 run1 run0 drun safe test rst w reset0000010111111111 figure 10-4. power domain #2 conf iguration register (pcu_pconf2) address 0xc3fe_8008 access: user read/write, su pervisor read/write, test read/write r0000000000000000 w reset0000000000000000 r 00 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0000010111111111 figure 10-5. power domain #2 conf iguration register (pcu_pconf2)
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 202 freescale semiconductor these registers define for each power domain #2 through #10123456789 whethe r it is on or off in each device mode. the bit field desc ription is the same as in table 10-3 . 10.3.1.5 power domain status register (pcu_pstat) this register reflects the power stat us of all available power domains. 10.4 functional description 10.4.1 general the mc_pcu controls all availabl e power domains on a device mode basis. the pcu_pconfn registers specify during which system/user modes a power domain is powered up. the power state for each individual power domain is reflected by the bits in the pcu_pstat register. address 0xc3fe_800c access: user read/write, su pervisor read/write, test read/write r0000000000000000 w reset0000000000000000 r 00 stby0 00 stop 0 halt run3 run2 run1 run0 drun safe test rst w reset0000010111111111 figure 10-6. power domain #3 conf iguration register (pcu_pconf3) address 0xc3fe_8040 access: user read, supervisor read, test read r0000000000000000 w reset0000000000000000 r 000000000000 pd3 pd2 pd1 pd0 w reset 0 0 0 10 10 10 10 10 10 10 10 10 10 10 1 1 figure 10-7. power domain status register (pcu_pstat) table 10-4. power domain status register (pcu_pstat) field descriptions field description pd n power status for power domain # n 0 power domain is inoperable 1 power domain is operable
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 203 on a mode change, the mc_pcu ev aluates which power domai n(s) must change power state. the power state is controlled by a st ate machine (fsm) for each individual power domain (see figure 10-8 ), which ensures a clean and safe state transition. 10.4.2 reset / power-on reset after any reset, the soc will tran sition to the reset mode during which all power domains are powered up (see chapter 8, mode entry module (mc_me) ). once the reset sequence has been completed, the drun mode is entered and software can begin the mc_p cu configuration. 10.4.3 mc_pcu configuration per default, all power domains are powered in all modes other than st andby. software can change the configuration for each power do main on a mode basis by program ming the pcu_pconfn registers. each power domain that is powered down is held in a reset state. read/write accesses to peripherals in those power domains will re sult in a transfer error. 10.4.4 mode transitions on a mode change requested by the mc_me, the mc _pcu evaluates the power configurations for all power domains. it compares the settings in the pcu_pconfn register s for the new mode with the settings for the current mode. if the configuration for a pow er domain differs between the modes, a power state change request is generated. these requests are handled by a finite stat e machine to ensu re a smooth and safe transition from one power state to another. 10.4.4.1 drun, safe, test, run0?3, halt, and stop mode transition the drun, safe, test, run0?3, halt, and stop modes allow an increased power saving. the level of power saving is software-controllable via the settings in the pcu_pconfn registers for power domain #2 onwards. the settings fo r power domains #0 and #1 cannot be changed. therefore, power domains #0 and #1 remain connected to the power supply for all modes beside standby. figure 10-8 shows an example for a mode tr ansition from run0 to halt a nd back, which will result in power domain #2 being powered down during the hal t mode. in this case, pcu_pconf2. halt is programmed to be 0. when the mc_pcu receives the mode change request to halt mode, it starts its power-down phase. during the power-down phase, clocks are disabled and the reset is asse rted, resulting in a loss of all information for this power domain. then the power domain is disconnected fr om the power supply (power-down state).
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 204 freescale semiconductor figure 10-8. mc_pcu events during power sequences (non-standby mode) when the mc_pcu receives a mode change request to run0, it starts its power-up phase if pcu_pconf2.run0 is 1. the power domain is reconn ected to the power supply, and the voltage in power domain #2 will increas e slowly. once the voltage of power domain #2 is within an operable range, its clocks are enabled, and its resets are deasserted (power-up state). note it is possible that, due to a mode ch ange, power-up is requested before a power domain completed its power-dow n sequence. in this case, the information in that power domain is lost. 10.4.4.2 standby mode transition standby offers the maximum power saving. the level of pow er saving is software -controllable via the settings in the pcu_pconfn regi sters for power domain #2 onwards. power domain #0 stays connected to the power supply while power do main #1 is disconnected from the power supply. among others, power domain #1 contains the platform and the mc_me. therefore this mode differs from all other user/system modes. once standby is entered it can onl y be left via a syst em wakeup. on exiting the standby mode, all power domains are powered up accord ing to the settings in the pcu_pconfn registers, and the drun mode is entered. in drun mode, at least power domains #0 and #1 are powered. figure 10-9 shows an example for a mode transition fr om run0 to standby to drun. all power domains that have pcu_pconfn.stby0 cleared will enter power-down phase. in this example only power domain #1 will be disa bled during standby mode. when the mc_pcu receives the mode change request to standby mode it starts the power down phase for power domain #1. during the power dow n phase, clocks are disabled and reset is asserted resulting in a loss of all information for this power domain. then the power domain is disc onnected from the power supply (power-down state). new mode power-down run0 voltage in pstat.pd2 halt run0 notes: not drawn to scale; pconf2.run0 = 1; pconf2.halt = 0 current mode power-up phase power domain #2 run0 halt run0 requested by me power-down state power-up state power-up state phase
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 205 figure 10-9. mc_pcu events during power sequences (standby mode) when the mc_pcu receives a syst em wakeup request, it starts the power-up phase. the power domain is reconnected to the power supply and the voltage in power domain #1 will increase slowly. once the voltage is in an operable range, clocks are enable d and the reset is deasse rted (power-up state). note it is possible that due to a wakeup re quest, power-up is requested before a power domain completed its power-dow n sequence. in this case, the information in that power domain is lost. 10.4.4.3 power saving for me mories during standby mode all memories that are not powered down during st andby mode automatically enter a power saving state. no software configuration is required to enable this power savi ng state. while a memory is residing in this state an increased power saving is achieved. data in the memories is retained. 10.5 initialization information to initialize the mc_pcu, the registers pcu_ pconf2?3 should be progr ammed. after programming is done, those registers should no longer be changed. new mode power-down run0 voltage in pstat.pd1 standby notes: not drawn to scale; pconf1.r un0 = 1; pconf1.stby0 = 0 current mode power-up phase power domain #1 run0 standby drun requested by me power-down state power-up state power-up state phase mode set due to reset being asserted to power domain #1 wakeup request
chapter 10 power control unit (mc_pcu) MPC5606BK microcontroller reference manual, rev. 2 206 freescale semiconductor 10.6 application information 10.6.1 standby mode considerations standby offers maximum power saving possibility. but power is only saved during the time a power domain is disconnected from the suppl y. increased power is required when a power domain is reconnected to the power supply. additional power is required duri ng restoring the information (for example, in the platform). care should be taken that the time during which the soc is operating in standby mode is significantly longer than the required time for restoring the information.
chapter 11 voltage regulators and power supplies MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 207 chapter 11 voltage regulators and power supplies 11.1 voltage regulators the power blocks provide a 1.2 v digital supply to the internal logic of the device. the main supply is 3.3 v?5 v 10% and digital/regulated output supply is 1.2 v 10%. the volta ge regulator used in MPC5606BK comprises three regulators. ? high power regulator (hpreg) ? low power regulator (lpreg) ? ultra low power regulator (ulpreg) the hpreg and lpreg regulators ar e switched off during standby m ode to save consumption from the regulator itself. in standby mode, the supply is provided by the ulpreg regulator. in stop mode, the user can configure the hpreg regulator to switch off (see chapter 8, mode entry module (mc_me) ). in this case, when current is low enough to be handled by lpreg alone, the hpreg regulator is switched off and the suppl y is provided by the lpreg regulator. the internal voltage regulator requires an external ca pacitance (creg) to be c onnected to the device in order to provide a stable low volta ge digital supply to the device. capacitances should be placed on the board as near as possible to the associated pins. the regulator has two digital domains, one for th e high power regulator (h preg) and the low power regulator (lpreg) called ?high power domain? and another one fo r the ultra low power regulator (ulpreg) called ?standby domain.? fo r each domain there is a low volta ge detector for the 1.2 v output voltage. additionally there are two low voltage dete ctors for the main/input supply with different thresholds, one at the 3.3 v level a nd the other one at the 5 v level. 11.1.1 high power regulator (hpreg) the hpreg converts the 3.3 v?5 v input supply to a 1. 2 v digital supply. for more information, see the voltage regulator electri cal characteristics section of the data sheet. the regulator can be switched off by software. refer to the main volta ge regulator cont rol bit (mvron) of the mode configur ation registers in chapter 8, mode entry module (mc_me) . 11.1.2 low power regulator (lpreg) the lpreg generates power for the device in the stop mode, providi ng the output supply of 1.2 v. it always sees the minimum exte rnal capacitance. the contro l part of the regulator ca n be used to disable the low power regulator. it is managed by mc_me.
chapter 11 voltage regulators and power supplies MPC5606BK microcontroller reference manual, rev. 2 208 freescale semiconductor 11.1.3 ultra low power regulator (ulpreg) the ulpreg generates power for th e standby domain as well as a part of the main domain and might or might not see the external capacitance . the control circuit of ulpreg can be used to disable the ultra low power regulator by software: th is action is managed by mc_me. 11.1.4 lvds and por there are three kinds of lvd available: 1. lvd_main for the 3.3 v?5 v input supply with thresholds at approximately 3 v level 1 2. lvd_main5 for the 3.3 v?5 v input supply wi th threshold at approximately 4.5 v level 1 3. lvd_dig for the 1.2 v output voltage the lvd_main and lvd_main5 sense the 3.3 v?5 v power supply for core, shared with io ring supply and indicate when the 3.3 v?5 v supply is stabilized. two lvd_digs are provided in the design. one lvd_di g is placed in the high power domain and senses the hpreg/lpreg output notifying that the 1.2 v output is stable. the other lvd_dig is placed in the standby domain and senses the sta ndby 1.2 v supply level notifying that the 1.2 v output is stable. the reference voltage used for all lvds is generated by the low power refe rence generator a nd is trimmed for lvd_dig, using the bits lp[4:7]. therefore, dur ing the pre-trimming period, lvd_dig exhibits higher thresholds, whereas during post trimming, the thresholds come in the desired range. power-down pins are provided for lvds. when lvds are power-down, their outputs are pulled high. por is required to initiali ze the device during supply rise. por works only on the rising edge of the main supply. to ensure its functi oning during the following ri sing edge of the supply, it is reset by the output of the lvd_main block when main s upply reaches below the lower volta ge threshold of the lvd_main. por is asserted on power-up when vdd supply is above v porup min (refer to data sheet for details). it will be released only after vdd supply is above v porh (refer to data sheet for details). vdd above v porh ensures power management module including in ternal lvds modules are fully functional. 11.1.5 vreg digital interface the voltage regulator digital interface provides the temporization delay at initial power-up and at exit from low-power modes. a signal, indicating that ultra lo w power domain is powered, is used at power-up to release reset to temporization count er. at exit from low-power mode s, the power-down for high power regulator request signal is monitored by the digital interface and used to release reset to the temporization counter. in both cases, on completion of the delay counter, a end- of-count signal is releas ed, it is gated with an other signal indicating ma in domain voltage fine in order to release the vregok signal. this is used by mc_rgm to release the reset to the device. it mana ges other specific requireme nts, like the transition between high power/low power mode to ultra low power mode avoiding a voltage drop below the permissible thres hold limit of 1.08 v. the vreg digital interface also holds control register to mask 5 v lv d status coming from the voltage regulator at the power-up. 1. see section ?voltage monitor electrical characteristics? of the data sheet for detailed information about this voltage value.
chapter 11 voltage regulators and power supplies MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 209 11.1.6 register description the vreg_ctl register is mapped to the mc_pcu address space as described in chapter 10, power control unit (mc_pcu) . 11.2 power supply strategy from a power-routing perspective, th e device is organized as follows. the device provides four dedicated supply domai ns at package level: 1. hv (high voltage external power supply for i/ os and most analog module) ? this must be provided externally through vdd_hv/vss_hv power pins. voltage values should be aligned with v dd /v ss . refer to data sheet for details. 2. adc (high voltage external pow er supply for adc module) ? this must be provided externally through vdd_hv_adc/vss_hv_adc power pins. voltage values should be aligned with v dd_hv_adc /v ss_hv_adc . refer to data sheet for details. 3. bv (high voltage external power supply for volta ge regulator module) ? this must be provided externally through vdd_bv_/vss_ bv power pins. voltage values should be aligned with v dd /v ss . refer to data sheet for details. address: 0xc3fe_8080 access: user read/write 0123456789101112131415 r000000000000000 0 w reset000000000000000 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 5v_lvd_mask w reset000000000000000 1 figure 11-1. voltage regulator control register (vreg_ctl) table 11-1. vreg_ctl field descriptions field description 5v_lvd_mask mask bit for 5 v lvd from regulator this is a read/write bit and must be unmasked by writing a 1 by software to generate lvd functional reset request to mc_rgm for 5 v trip. 1: 5 v lvd is masked 0: 5 v lvd is not masked.
chapter 11 voltage regulators and power supplies MPC5606BK microcontroller reference manual, rev. 2 210 freescale semiconductor 4. lv (low voltage internal power supply for co re, fmpll and flash digital logic) ? this is generated internally by embedded voltage regulator and provided to the co re, fmpll and flash. three vdd_lv/vss_lv pins pairs are provided to connect the three de coupling capacitances. this is generated internally by in ternal voltage regulator but provi ded outside to connect stability capacitor. refer to data sheet for details. the four dedicated supply domains ar e further divided within the package in order to reduce as much as possible emc and noise issues. ? hv_io: high voltage pad supply ? hv_fla n : high voltage flash memory supply ? hv_osc0reg 1 : high voltage external oscillator and regulator supply ? hv_adr: high voltage reference for adc module. supplies are further star routed to reduce impact of adc resistive reference on adc capacitive reference accuracy. ? hv_adv: high voltage supply for adc module ? bv: high voltage supply for voltage regulator ballast. these two ba llast pads are used to supply the core and the flash memory. each pad cont ains two ballasts to supply 80 ma and 20 ma, respectively. core is hence s upplied through two ballasts of 80 ma capability and cflash and dflash through two 20 ma ballasts. the hv suppl y for both ballasts is shorted through double bonding. ? lv_cor: low voltage supply for the core. it is also used to provide supply for fmpll through double bonding. ?lv_fla n : low voltage supply for flash memory module n . it is supplied with dedicated ballast and shorted to lv_cor through double bonding. ?lv_pll 2 : low voltage supply for fmpll 11.3 power domain organization based on stringent requirements for current consumptio n in different operationa l modes, the device is partitioned into different power dom ains. organization into these power domains primarily means separate power supplies that are separated fr om each other by use of power switches (switc h sw1 for power domain no. 1 and switch sw2 for power domain no. 2 as shown in figure 11-2 ). these different separated power supplies are hence enabling to switch off power to certain regions of the device to avoid even leakage current consumption in logic suppl ied by the corresponding power supply. this device employs three prim ary power domains, namely pd0, pd1, and pd2. as pcu supports dynamic power down of domains base d on different device mode, such a possible domain is depicted below in dotted periphery. power domain organization and connections to the internal regulator are depicted in figure 11-2 . 1. regulator ground is separated from oscillator groun d and shorted to the lv ground through star routing 2. during production test, it is also possible to provide the vdd_lv externally through pins by configuring regulator in bypass mode.
chapter 11 voltage regulators and power supplies MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 211 figure 11-2. power domain organization vdd_lv_bkp v dd pd0 pd1 pcu hpvdd ulpvdd lpvdd sw1 ipe_iso0 sirc rgm firc vgate hv por1hv por2hv nbypass hppd lppd v ss vreg rtc/ can sampler wkpu cflash dflash pe0 pe9 pe11 rc dig wakeup pads siul sscm reset e200z0h platform pa 0 pa 1 pa 2 pj4 vdd12 330nf cgm cgl me peripheral set pll peripheral set avddref avddsupply avsssupply avssref vdd5_cfla vdd5_dlf 330nf 330nf adc0 / vdd_lv_cor vdd_lv_bkp vdd_lv_bkp domain vdd_lv_fla0 ipe_pd v dd5b vdd_lv_fla1 8kb ram (pd2) 24 kb ram sw20 v ss osc dig sxosc rc dig api wkp fil 48 kb ram adc1 pd2
chapter 11 voltage regulators and power supplies MPC5606BK microcontroller reference manual, rev. 2 212 freescale semiconductor this page is intent ionally left blank.
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 213 chapter 12 wakeup unit (wkpu) 12.1 overview the wakeup unit supports two internal sources and as many as 27 external sources that can generate interrupts or wakeup events, of which one can caus e non-maskable interrupt requests or wakeup events. figure 12-1 is the block diagram of the wakeup unit a nd its interfaces to ot her system components. the wakeup vector mapping is shown in table 12-1 . all unused wkpu pins must use a pull resistor ? either pullup (internal or external ) or pulldown (external) ? to ensu re no leakage from floating inputs. table 12-1. wakeup vector mapping wakeup number port siu pcr# port input function 1 (can be used in conjunction with wkpu function) wkpu irq to intc irq# wisr register 2 bit position package 100-pin qfp 144-pin qfp 176-pin qfp wkpu0 api n/a 3 ? wakeupirq0 46 eif0 31 ? 3 ? 3 ? 3 wkpu1 rtc n/a 3 ?eif130 ? 3 ? 3 ? 3 wkpu2 pa1 pcr1 nmi eif2 29 ??? wkpu3 pa2 pcr2 ? eif3 28 ??? wkpu4 pb1 pcr17 can0rx, lin0rx eif4 27 ??? wkpu5 pc11 pcr43 can1rx, can4rx eif5 26 ??? wkpu6 pe0 pcr64 can5rx eif6 25 ??? wkpu7 pe9 pcr73 can2rx, can3rx eif7 24 ??? wkpu8 pb10 pcr26 ? wakeupirq1 47 eif8 23 ??? wkpu9 pa4 pcr4 lin5rx eif9 22 ??? wkpu10 pa15 pcr15 ? eif10 21 ??? wkpu11 pb3 pcr19 lin0rx eif11 20 ??? wkpu12 pc7 pcr39 lin1rx eif12 19 ??? wkpu13 pc9 pcr41 lin2rx eif13 18 ??? wkpu14 pe11 pcr75 lin3rx eif14 17 ??? wkpu15 pf11 pcr91 lin4rx eif15 16 x 4 ??
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 214 freescale semiconductor wkpu16 pf13 pcr93 lin5rx wakeupirq2 48 eif16 15 x 4 ?? wkpu17 pg3 pcr99 ? eif17 14 x 4 ?? wkpu18 pg5 pcr101 ? eif18 13 x 4 ?? wkpu19 pa0 pcr0 ? eif19 12 ??? wkpu20 pg7 pcr103 lin6rx eif20 11 x 4 ?? wkpu21 pg9 pcr105 lin7rx eif21 10 x 4 ?? wkpu22 pf9 pcr89 can2rx, can3rx eif22 9 x 4 ?? wkpu23 pi3 pcr131 ? eif23 8 x 4 x 4 ? wkpu24 pi1 pcr129 ? 49 eif24 7 x 4 x 4 ? wkpu25 pb8 pcr24 ? eif25 6 ??? wkpu26 pb9 pcr25 ? eif26 5 ??? wkpu27 pd0 pcr48 ? eif27 4 ??? wkpu28 pd1 pcr49 ? eif28 3 ??? 1 this column does not contain an exhaustive list of functions on that pin. rather, it includes peripheral communication function s (such as can and linflex rx) that could be used to wake up the microcontroller. dspi pins are not included because dspi would typically be used in master mode. 2 wisr, irer, wrer, wifeer , wifeef, wifer, wipuer 3 port not required to use timer functions. 4 unavailable wkpu pins must use internal pullup enabled using wipuer. table 12-1. wakeup vector mapping (continued) wakeup number port siu pcr# port input function 1 (can be used in conjunction with wkpu function) wkpu irq to intc irq# wisr register 2 bit position package 100-pin qfp 144-pin qfp 176-pin qfp
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 215 figure 12-1. wkpu block diagram 12.2 features the wakeup unit supports th ese distinctive features: ? non-maskable interrupt support with ? one nmi source with bypassable glitch filter ? independent interrupt destination: non-maskable interrupt, critic al interrupt, or machine check request ? edge detection ? external wakeup/interrupt support with ? four system interrupt vectors fo r as many as 29 interrupt sources ? analog glitch filter per each wakeup line ? independent interrupt mask ? edge detection ? configurable system wakeup tri ggering from all interrupt sources ? configurable pullup ? on-chip wakeup support ips bus pa d s interrupt controller pbridge mode / power ctl irqs sys wakeup wakeup 0-27 platform 0-3 nmi / wakeup - configuration irq / wakeup - configuration wakeup unit iomux rtc & api 2 filter filter filter bypass filter bypass nmi enable
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 216 freescale semiconductor ? two wakeup sources ? wakeup status mapped to same register as external wake up/interrupt status 12.3 external signal description the wakeup unit has 29 signal inputs th at can be used as external inte rrupt sources in normal run mode or as system wakeup source s in all power down modes. the 27 external signal inputs include one signal input that can be used as a non-maskable interrupt source in normal run, halt or stop modes or a system wakeup source in stop or standby modes. the exception is with ports pb[8] and pb [9], which have wakeup functional ity in all modes except standby. note the user should be aware that the wa ke-up pins are enabled in all modes, therefore, the wake-up pins should be correctly terminated to ensure minimal current consumpt ion. any unused wake-up signal input should be terminated by using an external pull up or pulldown, or by internal pullup enabled at wkpu_wipuer. also, care has to be taken on packages where the wake-up signal inputs are not bonded. for these packages the user must ensure the internal pullup are en abled for those signals not bonded. 12.4 memory map and register description this section provides a detailed description of all registers accessibl e in the wkpu module. 12.4.1 memory map table 12-2 shows the wkpu memory map. table 12-2. wkpu memory map base address: 0xc3f9_4000 address offset register name location 0x00 nmi status flag register (nsr) on page 217 0x04 ? 0x07 reserved 0x08 nmi configuration register (ncr) on page 218 0x0c ? 0x13 reserved 0x14 wakeup/interrupt status flag register (wisr) on page 219 0x18 interrupt request enable register (irer) on page 219 0x1c wakeup request enable register (wrer) on page 220 0x20 ? 0x27 reserved 0x28 wakeup/interrupt rising-edge event enable register (wireer) on page 220 0x2c wakeup/interrupt falling-edge event enable register (wifeer) on page 221
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 217 note reserved registers will read as 0, writes will have no effect. if sscm_error[rae] is enabled, a tran sfer error will be issued when trying to access completely reserved register space. 12.4.2 nmi status flag register (nsr) this register holds the non-mask able interrupt status flags. 0x30 wakeup/interrupt filter enable register (wifer) on page 221 0x34 wakeup/interrupt pullup enable register (wipuer) on page 222 offset: 0x00 access: user read/write 0123456789101112131415 r nif0 novf0 00000000000000 ww1c w1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 12-2. nmi status flag register (nsr) table 12-3. nsr field descriptions field description nif0 nmi status flag if enabled (nree0 or nfee0 set), nif0 causes an interrupt request. 1 an event as defined by nree0 and nfee0 has occurred 0 no event has occurred on the pad novf0 nmi overrun status flag it will be a copy of the current nif0 value whenever an nmi event occurs, thereby indicating to the software that an nmi occurred while the last one was not yet serviced. if enabled (nree0 or nfee0 set), novf0 causes an interrupt request. 1 an overrun has occurred on nmi input 0 no overrun has occurred on nmi input table 12-2. wkpu memory map (continued) base address: 0xc3f9_4000 address offset register name location
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 218 freescale semiconductor 12.4.3 nmi configuration register (ncr) this register holds the configuration bits for the non-maskable interrupt settings. offset: 0x08 access: user read/write 0123456789101112131415 r nlock0 ndss0 nwre0 0 nree0 nfee0 nfe0 00000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 12-3. nmi config uration register (ncr) table 12-4. ncr field descriptions field description nlock0 nmi configuration lock register writing a 1 to this bit lo cks the configuration for the nmi until it is unlocked by a system reset. writing a 0 has no effect. ndss0 nmi destination source select 00 non-maskable interrupt 01 critical interrupt 10 machine check request 11 reserved?no nmi, critical interrupt, or machine check request generated nwre0 nmi wakeup request enable 1 a set nif0 bit or set novf0 bit causes a system wakeup request 0 system wakeup requests from the corresponding nif0 bit are disabled note: software should only enable the nmi after the i vpr/ivor registers have been configured. this should be noted when booting from reset or standby mode as all registers will have been cleared to their reset state. nree0 nmi rising-edge events enable 1 rising-edge event is enabled 0 rising-edge event is disabled nfee0 nmi falling-edge events enable 1 falling-edge event is enabled 0 falling-edge event is disabled nfe0 nmi filter enable enable analog glitch filter on the nmi pad input. 1 filter is enabled 0 filter is disabled
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 219 note writing a 0 to both nree0 and nfee0 disables the nmi functionality completely (that is, no system wakeup or interrupt will be generated on any pad activity)! 12.4.4 wakeup/interrupt status flag register (wisr) this register holds the wakeup/interrupt flags. note status bits associated with on-chip wa keup sources are located to the left of the external wakeup/interrupt status bi ts and are read onl y. the wakeup for these sources must be configured and cleared at the on-ch ip wakeup source. also, the configuration registers for the external interrupts/wakeups do not have corresponding bits. 12.4.5 interrupt request enable register (irer) this register is used to enable the interrupt messa ging from the wakeup/interrupt pads to the interrupt controller. offset: 0x14 access: user read/write 012345678910111213141516171819202122232425262728293031 r000 eif[28:0] 1 1 eif[24:20] and eif[18:15] not available in 100- pin lqfp; eif[24:23] not available in 144-pin lqfp w w1c reset00000000000000000000000000000000 figure 12-4. wakeup/interrupt status flag register (wisr) table 12-5. wisr field descriptions field description eif[x] external wakeup/interrupt wkpu[x] status flag this flag can be cleared only by writing a 1. writi ng a 0 has no effect. if enabled (irer[x]), eif[x] causes an interrupt request. 1 an event as defined by wireer and wifeer has occurred 0 no event has occurred on the pad
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 220 freescale semiconductor 12.4.6 wakeup request enable register (wrer) this register is used to enable the system wakeup messaging from the wakeup/in terrupt pads to the mode entry and power control modules. 12.4.7 wakeup/interrupt rising-edge event enable register (wireer) this register is used to enable rising-edge trig gered events on the corresponding wakeup/interrupt pads. note the rtc_api can only be configured on the rising edge. offset: 0x18 access: user read/write 012345678910111213141516171819202122232425262728293031 r 0 0 0 eire[28:0] 1 1 eire[24:20] and eire[1 8:15] not available in 100-pin lqfp; eire [24:23] not available in 144-pin lqfp w w1c reset00000000000000000000000000000000 figure 12-5. interrupt request enable register (irer) table 12-6. irer field descriptions field description eire[x] external interrupt request enable x 1 a set eif[x] bit causes an interrupt request 0 interrupt requests from the corresponding eif[x] bit are disabled offset: 0x1c access: user read/write 012345678910111213141516171819202122232425262728293031 r000 wre[28:0] 1 1 wre[24:20] and wre[18:15] not av ailable in 100-pin lqfp; wre[24:23] not available in 144-pin lqfp w reset00000000000000000000000000000000 figure 12-6. wakeup request enable register (wrer) table 12-7. wrer field descriptions field description wre[x] external wakeup request enable x 1 a set eif[x] bit causes a system wakeup request 0 system wakeup requests from the corresponding eif[x] bit are disabled
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 221 . 12.4.8 wakeup/interrupt falling-edge event enable re gister (wifeer) this register is used to enable falling-edge tri ggered events on the corresponding wakeup/interrupt pads. 12.4.9 wakeup/interrupt filter enable register (wifer) this register is used to enable an analog filter on the corresponding interr upt pads to filter out glitches on the inputs. note there is no analog filter for the rtc_api. offset: 0x28 access: user read/write 012345678910111213141516171819202122232425262728293031 r000 iree[28:0] 1 1 iree[24:20] and iree[18:15] not available in 100-pin lqfp; iree[24:23] not avai lable in 144-pin lqfp w reset00000000000000000000000000000000 figure 12-7. wakeup/interrupt rising-edge event enable register (wireer) table 12-8. wireer field descriptions field description iree[x] external interrupt rising-edge events enable x 1 rising-edge event is enabled 0 rising-edge event is disabled offset: 0x2c access: user read/write 012345678910111213141516171819202122232425262728293031 r000 ifee[28:0] 1 1 ifee[24:20] and ifee[18:15] not available in 100-pi n lqfp; ifee[24:23] not available in 144-pin lqfp w reset00000000000000000000000000000000 figure 12-8. wakeup/interrupt falling-edge event enable register (wifeer) table 12-9. wifeer field descriptions field description ifeex external interrupt falling-edge events enable x 1 falling-edge event is enabled 0 falling-edge event is disabled
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 222 freescale semiconductor 12.4.10 wakeup/interrupt pullu p enable register (wipuer) this register is used to enable a pullup on the corresponding interrupt pads to pull an unconnected wakeup/interrupt input to a value of 1. 12.5 functional description 12.5.1 general this section provides a complete func tional description of the wakeup unit. offset: 0x30 access: user read/write 012345678910111213141516171819202122232425262728293031 r000 ife[28:0] 1 1 ife[24:20] and ife[18:15] not available in 100-pi n lqfp; ife[24:23] not available in 144-pin lqfp w reset00000000000000000000000000000000 figure 12-9. wakeup/interrupt filter enable register (wifer) table 12-10. wifer field descriptions field description ife[x] external interr upt filter enable x enable analog glitch filter on the external interrupt pad input. 1 filter is enabled 0 filter is disabled offset: 0x34 access: user read/write 012345678910111213141516171819202122232425262728293031 r000 ipue[28:0] 1 1 ipue[24:20] and ipue[18:15] not avai lable in 100-pin lqfp; ipue[24:23] not available in 144-pin lqfp w reset00000000000000000000000000000000 figure 12-10. wakeup/interrupt pullup enable register (wipuer) table 12-11. wipuer field descriptions field description ipue[x] external interrupt pullup enable x 1 pullup is enabled 0 pullup is disabled
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 223 12.5.2 non-maskable interrupts the wakeup unit supports one non-maskable interrupt that is allocated to the following pins: ? 100-pin lqfp: pin 7 ? 144-pin lqfp: pin 11 ? 176-pin lqfp: pin 19 the wakeup unit supports the genera tion of three types of interrupts from the nmi. the wakeup unit supports the capturing of a second ev ent per nmi input before the interr upt is cleared, thus reducing the chance of losing an nmi event. each nmi passes through a bypassable analog glitch filter. note glitch filter control a nd pad configuration should be done while the nmi is disabled in order to avoid erroneou s triggering by glitches caused by the configuration process itself. figure 12-11. nmi pad diagram 12.5.2.1 nmi management glitch filter edge detect flag overrun destination nmi critical irq machine check cpu mode/ pwr ctl ndss0 nwre0 nree0 nfee0 nfe0 nmi configuration register (ncr) wakeup enable
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 224 freescale semiconductor the nmi can be enabled or disabled using the single ncr register laid out to cont ain all configuration bits for an nmi in a single byte (see figure 12-3 ). the pad defined as an nmi can be configured by the user to recognize interrupts with an active rising edge, an active falling edge or both edges being active. a setting of having both edge events disabled results in no interrupt being detected, and should not be configured. the active nmi edge is controlled by the user th rough the configuration of the nree0 and nfee0 bits. note after reset, nree0 and nfee0 are set to 0. therefore, the nmi functionality is disabled after reset and must be enabled explicitly by software. once the pad?s nmi functionality has been enabled, the pad cannot be reconfigured in the iomux to override or disable the nmi. the nmi destination interrupt is controlled by the user through th e configuration of the ndss0 field. see table 12-4 for details. an nmi supports a status flag and an overrun flag, which are lo cated in the nsr register (see figure 12-2 ). the nif0 and novf0 fields in this register are clea red by writing a 1 to them; this prevents inadvertent overwriting of other flags in the regi ster. the status flag is set whenever an nmi event is detected. the overrun flag is set whenever an nmi event is detected and the status flag is set (that is, has not yet been cleared). note the overrun flag is cleared by writing a 1 to the appropriate overrun bit in the nsr register. if the status bit is cl eared and the overrun b it is still set, the pending interrupt will not be cleared. 12.5.3 external wakeups/interrupts the wakeup unit supports as many as 27 external wa keup/interrupts that can be allocated to any pad necessary at the soc level. th is allocation is fixed per soc. the wakeup unit supports as many as four interrupt vect ors to the interrupt contro ller of the soc. each interrupt vector can support up to the number of external interrupt sources from th e device pads with the total across all vectors being equal to the number of external interrupt sources. each external interrupt source is assigned to exactly one interrupt vector. the interrupt vector assignment is sequential so that one interrupt vector is for external interrupt sources 0 through n ? 1, th e next is for n through n + m ? 1, and so forth. see figure 12-12 for an overview of the external interrupt imp lementation for the exam ple of four interrupt vectors with as many as eight external interr upt sources each.
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 225 figure 12-12. external interrupt pad diagram all of the external interrupt pads within a single group have equal priori ty. it is the responsibility of the user software to search through th e group of sources in the most a ppropriate way for their application. note glitch filter control and pad configuration should be done while the external interrupt line is disabled in order to avoid erroneous triggering by glitches caused by the configuration process itself. 12.5.3.1 external interrupt management each external interrupt can be enabled or disabled independently. this can be performed using a single rolled up register ( figure 12-5 ). a pad defined as an external interr upt can be configured by the user to recognize external interrupts with an active rising edge, an active falling edge or both edge s being active. note writing a 0 to both iree[x] and ifee[x] disables the external interrupt functionality for that pad completely (that is, no system wakeup or interrupt will be generated on any activity on that pad)! the active irq edge is controlled by the users th rough the configuration of the registers wireer and wifeer. each external interrupt supports an i ndividual flag that is held in the fl ag register (wisr). the bits in the wisr[eif] field are cleared by writing a 1 to them; this prevents in advertent overwriting of other flags in the register. or or interrupt controller interrupt pads wireer[28:0] interrupt edge enable wifeer[28:0] falling rising edge detection analog glitch filter wifer[28:0] glitch filter enable interrupt enable or irq_16_23 irq_15_08 irq_07_00 flag[19:16] flag[15:8] wisr[28:0] flag[7:0] wrer[28:0] wakeup enable mode/ irer[28:0] rtc api flag[24:20] irq_24_28 power ctl vectors
chapter 12 wakeup unit (wkpu) MPC5606BK microcontroller reference manual, rev. 2 226 freescale semiconductor 12.5.4 on-chip wakeups the wakeup unit supports two on-chip wakeup source s. it combines the on-chip wakeups with the external ones to generate a single wakeup to the system. 12.5.4.1 on-chip wakeup management in order to allow software to dete rmine the wakeup source at one location, on-c hip wakeups are reported along with external wakeups in the wisr register (see figure 12-4 for details). enabling and clearing of these wakeups are done via the on-chip wakeup source?s own registers.
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 227 chapter 13 real time clock / autonomous periodic interrupt (rtc/api) 13.1 overview the rtc/api is a free running counter used for time keeping applications. the rtc may be configured to generate an interrupt at a predefined interval independent of the mode of operation (run mode or low power mode). if in a low power mode when the rtc interval is reached, the rtc firs t generates a wakeup, and then asserts the interrupt request. the rtc al so supports an autonomous periodic interrupt (api) function used to generate a period ic wakeup request to exit a low power mode or an interrupt request. 13.2 features features of the rtc/api include: ? three selectable counter clock sources ? sirc (128 khz) ? sxosc (32 khz) ? firc (16 mhz) ? optional ? 512 prescaler and optional ? 32 prescaler ? 32-bit counter ? supports times as long as 1.5 months with 1 ms resolution ? runs in all modes of operation ? reset when disabled by software and by por ? 12-bit compare value to support interrupt interv als from 1 second to longer than 1 hour, with 1 second resolution ? rtc compare value changeable while counter is running ? rtc status and control re gister are reset only by por ? autonomous periodic interrupt (api) ? 10-bit compare value to support wake up intervals of 1.0 ms to 1 second ? compare value changeable while counter is running ? configurable interrupt for rtc ma tch, api match, and rtc rollover ? configurable wakeup event for rtc match, api match, and rtc rollover
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 228 freescale semiconductor figure 13-1. rtc/api block diagram 0 1 2 clksel[0:1] 3 sirc firc sxosc == cnten rtccnt rtcval 10:21 rtcf rtcie rtc interrupt offset reg == 22:31 api wakeup + load 22:31 apival apien reset reset 32-bit counter sync sync rtc wakeup apif apiie api sync interrupt rovrf sync reserved div512 div32 div32en div512en rtcie rovren
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 229 figure 13-2. clock gating for rtc clocks 13.3 device-specific information for MPC5606BK, the device specific information is the following: ? sxosc, firc, and sirc clocks are provided as counter clocks for th e rtc. default clock on reset is sirc divided by 4. ? the rtc will be reset on dest ructive reset, with the excep tion of software watchdog reset. ? the rtc provides a configurable divider by 512 to be optionally used when firc source is selected. 13.4 modes of operation 13.4.1 functional mode there are two functional modes of operation for th e rtc: normal operation and low power mode. in normal operation, all rtc registers can read or writte n and the input isolation is disabled. the rtc/api 32-bit counter cell c.g. en sirc (cnten & clksel== 00) cell en sxosc (cnten & clksel== 01) cell en firc (cnten & clksel== 10) cell c.g. en reserved (cnten & clksel== 11) c.g. c.g. 0 1 2 clksel[0:1] 3 cell c.g. en 1 0 div 512 cell c.g. en 1 0 div 32 div512en div32en cnten
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 230 freescale semiconductor and associated interrupts ar e optionally enabled. in low power mode, the bus in terface is disabled and the input isolation is enabled. the rtc/api is enabled if enabled prior to entry into low power mode. 13.4.2 debug mode on entering into the debug mode th e rtc counter freezes on the last valid count if the rtcc[frzen] is set. on exit from debug mode counter continues from the frozen value. 13.5 register descriptions table 13-1 lists the rtc/api registers. 13.5.1 rtc supervisor control register (rtcsupv) the rtcsupv register contains the supv bit, which determines whethe r other registers are accessible in supervisor mode or user mode. note rtcsupv register is accessible only in supervisor mode. table 13-1. rtc/api register map base address: 0xc3fe_c000 address offset register location 0x0 rtc supervisor control register (rtcsupv) on page 230 0x4 rtc control register (rtcc) on page 231 0x8 rtc status register (rtcs) on page 233 0xc rtc counter register (rtccnt) on page 234 offset: 0x0 access: read/write 012345678910111213141516171819202122232425262728293031 r supv w reset10000000000000000000000000000000 figure 13-3. rtc supervisor control register (rtcsupv) table 13-2. rtcsupv field descriptions field description supv rtc supervisor bit 0 all registers are accessible in bot h user as well as supervisor mode. 1 all other registers are accessi ble in supervisor mode only.
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 231 13.5.2 rtc control register (rtcc) the rtcc register contains: ? rtc counter enable ? rtc interrupt enable ? rtc clock source select ? rtc compare value ?api enable ? api interrupt enable ? api compare value offset: 0x4 access: user read/write 0123 4 56789101112131415 r cnten rtcie frzen rovren rtcval w reset0000 0 00000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r apien apiie clksel div512en div32en apival w reset0000 0 00000000000 figure 13-4. rtc control register (rtcc) table 13-3. rtcc field descriptions field description cnten counter enable the cnten field enables the rtc counter. making cnten bit 0 has the effect of asynchronously resetting (synchronous reset negation) all the rtc and api logic. this allows for the rtc configuration and clock source selection to be updated without causing synchronization issues. 1 counter enabled 0 counter disabled rtcie rtc interrupt enable the rtcie field enables interrupts requests to the system if rtcf is asserted. 1 rtc interrupts enabled 0 rtc interrupts disabled frzen freeze enable the counter freezes on entering the debug mode on the last valid count value if the frzen bit is set. after coming out of the debug mode, the counter starts from the frozen value. 0 counter does not freeze in debug mode. 1 counter freezes in debug mode.
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 232 freescale semiconductor rovren counter roll over wakeup/interrupt enable the rovren bit enables wakeup and interrupt requests when the rtc has rolled over from 0xffff_ffff to 0x0000_0000. the rtcie bit must also be set in order to generate an interrupt from a counter rollover. 1 rtc rollover wakeup/interrupt enabled 0 rtc rollover wakeup/interrupt disabled rtcval note: rtc compare value the rtcval bits are compared to bits 10:21 of the rtc counter and if match sets rtcf. rtcval can be updated when the counter is running. apien autonomous periodic interrupt enable the apien bit enables the autonomous periodic interrupt function. 1 api enabled 0 api disabled apiie api interrupt enable the apiie bit enables interrupts requests to the system if apif is asserted. 1 api interrupts enabled 0 api interrupts disabled clksel clock select this field selects the clock source for the rtc. clksel may only be updated when cnten is 0. the user should ensure that oscillator is enabled before selecting it as a clock source for rtc. 00 sxosc 01 sirc 10 firc 11 reserved div512en divide by 512 enable the div512en bit enables the 512 clock divider. div512en may only be updated when cnten is 0. 0 divide by 512 is disabled. 1 divide by 512 is enabled. div32en divide by 32 enable the div32en bit enables the 32 clock divider. div32en may only be updated when cnten is 0. 0 divide by 32 is disabled. 1 divide by 32 is enabled. apival api compare value the apival field is compared with bits 22:31 of the rtc counter and if match asserts an interrupt/wakeup request. apival may only be updated when apien is 0 or api function is undefined. note: api functionality starts only when apival is no nzero. the first api interrupt takes two more cycles because of synchronization of apival to the rtc clock, and apival + 1 cycles for subsequent occurrences. after that, interrupts are periodic in nature. the minimum supported value of apival is 4. table 13-3. rtcc field descriptions (continued) field description
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 233 13.5.3 rtc status register (rtcs) the rtcs register contains: ? rtc interrupt flag ? api interrupt flag ? rollovr flag offset: 0x8 access: user read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r 0 0 rtcf 0 0 0 0 0 0 0 0 0 0 0 0 0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 apif 0 0 rovrf 0 0 0 0 0 0 0 0 0 0 w reset0000000000000000 figure 13-5. rtc status register (rtcs) table 13-4. rtcs field descriptions field description rtcf rtc interrupt flag the rtcf bit indicates that the rtc counter has reached the counter value matching rtcval. rtcf is cleared by writing a 1 to rtcf. writing a 0 to rtcf has no effect. 1 rtc counter matches rtcval 0 rtc counter is not equal to rtcval apif api interrupt flag the apif bit indicates that the rtc counter has reached the counter value matching api offset value. apif is cleared by writing a 1 to apif. writing a 0 to apif has no effect. 1 api interrupt 0 no api interrupt note: the periodic interrupt comes after apival[0:9] + 1 rtc counts rovrf counter roll over interrupt flag the rovrf bit indicates that the rtc has rolled over from 0xffff_ffff to 0x0000_0000. rovrf is cleared by writing a 1 to rovrf. 1 rtc has rolled over 0 rtc has not rolled over
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 234 freescale semiconductor 13.5.4 rtc counter register (rtccnt) the rtccnt register contains the current value of the rtc counter. 13.6 rtc functional description the rtc consists of a 32-bit free running counter enabled with the rtcc[cnten] bit (cnten when negated asynchronously resets the c ounter and synchronously enables the counter when enabled). the value of the counter may be read via the rtccnt regi ster. note that due to the clock synchronization, the rtccnt value may actually represen t a previous counter value. the di fference between the counter and the read value depends on ratio of counter clock an d system clock. maximum po ssible difference between the two is 6 count values. the clock source to the counter is selected with the rtcc[clksel] field, which gives the options for clocking the rtc/api. the output of the clock mux can be optionally divided by combination of 512 and 32 to give a 1 ms rtc/api count period for different clock sources. note that the rtcc[cnten] bit must be disabled when the rtc/ap i clock source is switched. when the counter value for counte r bits 10:21 match the 12-bit value in the rtcc[rtcval] field, then the rtcs[rtcf] interrupt flag bit is set (after proper clock synchronization). if the rtcc[rtcie] interrupt enable bit is set, then the rtc interrupt request is generate d. the rtc supports interrupt requests in the range of 1 s to 4096 s (> 1 hr) with a 1 s resoluti on. if there is a match while in low power mode then the rtc will first generate a wakeup re quest to force a wakeup to run mode, then the rtcf flag will be set. a rollover wakeup and/or interrupt can be genera ted when the rtc transitions from a count of 0xffff_ffff to 0x0000_0000. the rollover fl ag is enabled by setting th e rtcc[rovren] bit. an rtc counter rollover with this bit will cause a wakeup from low power mode. an interrupt request is generated for an rtc counter rollover when both the rtcc[rovren] and rtcc[rtcie] bits are set. all the flags and counter values are synchronized with the system clock. it is assumed that the system clock frequency is always more than or equal to the rtc_clk used to run the counter. offset: 0xc access: read 012345678910111213141516171819202122232425262728293031 r rtccnt w reset00000000000000000000000000000000 figure 13-6. rtc counter register (rtccnt) table 13-5. rtccnt field descriptions field description rtccnt rtc counter value due to the clock synchronization, the rtccnt valu e may actually represent a previous counter value.
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 235 13.7 api functional description setting the rtcc[apien] bit enables the autonom ous interrupt function. the 10-bit rtcc[apival] field selects the time interval fo r triggering an interrupt and/or wa keup event. since the rtc is a free running counter, the apival is added to the current count to calculate an offset. when the counter reaches the offset count, a interrupt and/or wakeup request is generate d. then the offset valu e is recalculated and again re-triggers a new request wh en the new value is reached. apiv al may only be updated when apien is disabled. when a compare is reached, the rtcs[api f] interrupt flag bit is set (after proper clock synchronization). if the rt cc[apiie] interrupt enable bit is set, then the api interrupt request is generated. if there is a match while in low power mode, then the api wi ll first generate a wakeup request to force a wakeup into normal operation, then the apif flag will be set.
chapter 13 real time clock / autonomous periodic interrupt (rtc/api) MPC5606BK microcontroller reference manual, rev. 2 236 freescale semiconductor this page is intent ionally left blank.
chapter 14 can sampler MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 237 chapter 14 can sampler 14.1 introduction the can sampler peripheral has been designed to stor e the first identifier of can message detected on the can bus while no precise clock (crystal) is running at that time on the device, typically in low power modes (stop, halt or stanby) or in run mode with crystal switched off. depending on both can baud rate and lo w power mode used, it is possible to catch either the first or the second can frame by sampling one c an rx port among 6 and storing all samples in internal registers. after selection of the mode (first or second frame), the can sampler stores samples of the 48 bits or skips the first frame and stores samples of the 48 bits of second frame using the 16 mhz fast internal rc oscillator and the 5- bit clock prescaler. after completion, software must process the sample d data in order to rebuild the 48 minimal bits. figure 14-1. extended can data frame 14.2 main features ? store 384 samples, equivalent to 48 can bit at 8 samples/bit ? sample frequency from 500 khz to 16 mhz, equiva lent at 8 samples/bit to can baud rates of 62.5 kbit/s to 2 mbit/s ? user selectable can rx sample port [can0rx?can5rx] ? 16 mhz fast internal rc oscillator clock ? 5-bit clock prescaler ? configurable trigger mode (immediate, next frame) ? flexible samples processing by software ? very low power consumption base identifier (11-bit) sof spr extended identifier (18-bit) ide bit rtr bit r1 r0 data length code
chapter 14 can sampler MPC5606BK microcontroller reference manual, rev. 2 238 freescale semiconductor 14.3 memory map and register description the can sampler registers are listed in table 14-1 . 14.3.1 control register (cr) table 14-1. can sampler memory map base address: 0xffe7_0000 address offset register location 0x00 control register (cr) on page 238 0x04?0x30 sample registers 0?11 on page 239 offset: 0x00 access: read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_complete busy active_ck 000 mode can_rx_sel brp can_smplr_en w reset0000000000000000 figure 14-2. control register (cr) table 14-2. cr field descriptions field description rx_complete 0: can frame has not been stored in the sample registers 1: can frame is stored in the sample registers busy this bit indicates the status of sampling 0: sampling is complete or has not started 1: sampling is ongoing active_ck this bit indicates the current clock (xmem_ck) for sample registers 0: ipg_clk_s is currently xmem_ck 1: rc_clk is currently xmem_ck mode 0:skip the first frame and sample and store the second frame (sf_mode) 1:sample and store the first frame (ff_mode)
chapter 14 can sampler MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 239 14.3.2 can sampler sample registers 0?11 14.4 functional description as the can sampler is driven by the 16 mhz fast in ternal rc oscillator to sample properly the can identifier, two modes are possible depending on both can baud rate and low power mode used: ? immediate sampling on falling edge detection (first can frame): this mode is used when the fast internal rc oscillator 16 mh z is available in lp mode, for example, stop or halt. ? sampling on next frame (second can frame): this mode is used when the fast internal rc oscillator 16 mhz is switched of f in low power mode, such as stan dby. due to the start-up times of both the voltage regulator and the fast internal rc oscillator 16 mhz (~10 s), the can sampler would miss the first bits of a c an identifier sent at 500 kbit/s. therefore the first identifier is ignored and the sampling is performed on the fi rst falling edge of after interframe space. can_rx_sel these bits determine which rx bit is sampled. 000: rx0 is selected 001: rx1 is selected 010: rx2 is selected 011: rx3 is selected 100: rx4 is selected 101: rx5 is selected 110: rx6 is selected 111: rx7 is selected brp baud rate prescaler these bits are used to set the baud rate before going into standby mode 00000: prescaler has 1 11111: prescaler has 32 can_smplr_en can sampler enable this bit enables the can sampler before going into standby or stop mode. 0: can sampler is disabled 1: can sampler is enabled offsets: 0x04?0x30 (12 regi sters) access: read/write 0123456789101112131415 r sr[0:15] w reset the reset values are unknown. they will be filled only after the first can sampling. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r sr[16:31] w reset the reset values are unknown. they will be filled only after the first can sampling. figure 14-3. can sampler sample registers 0?11 table 14-2. cr field descriptions (continued) field description
chapter 14 can sampler MPC5606BK microcontroller reference manual, rev. 2 240 freescale semiconductor the can sampler performs sampling on a user sele cted can rx port among six rx ports available, normally when the device is in standby or stop mode storing the samples in internal registers. the user is required to configure the baud rate to achieve eight samples per can nom inal bit. it does not perform any sort of filtering on input samples. thereafter th e software must enable the sampler by setting can_smplr_en bit in cr register. it then become s the master controller for accessing the internal registers implemented for storing samples. when enabled, the can sampler waits for a low pulse on the selected rx line, taking it as a valid bit of the first can frame, and generates the rc wakeup request , which can be used to start the rc oscillator. depending upon the mode, it stores the first 8 samples of the 48 bits on sele cted rx line or skips the first frame and stores 8 bits for first 48 bits of second frame. in ff_mode, it sample s the can rx line on rc clock and stores the 8 samples of first 48 bits (384 samples). in sf_mode, it samples the rx and waits for 11 consecutive dominant bits (11 8 samples), taking it as the end of fi rst frame. it then waits for first low pulse on the rx, taking it as a valid start of frame (sof) of the second frame. the sampler takes 384 samples (48 bytes 8) using the rc clock (configuring 8 samples per nom inal bit) of the second frame, including the sof bit. these samples are stored in consecutive addresses of the (12 32) internal registers. rx_complete bit is set to 1, indicating that sampling is complete. software should now process the sampled data by fi rst becoming master for accessing samples internal registers by resetting can_smplr_en bit.the sampler will need to be enabled again to start waiting for a new sampling routine. 14.4.1 enabling/disabling the can sampler the can sampler is disabled on reset and the cpu is able to access the 12 registers used for storing samples. the can sampler must be enabled befo re going into standby or stop mode by setting can_smplr_en bit in the control regi ster (cr) by writing 1 to this bit. any activity on selected rx line, the sampler enable s the 16 mhz fast internal rc oscillator. when can_smplr_en is reset to 0, the sampler should at le ast receive three rc cloc k pulses to reset itself, after which the rc can be switched off. when the software wishes to access the sample regist ers contents it must first reset the can_smplr_en bit by writing a 0. before accessing the register conten ts it must monitor active_ck bit for 0.when this bit is reset it can safely access th e (12 32) sample registers. while shifting from normal to sample mode and vice versa, the sample register signals must be static and inactive to ensure the data is not corrupt. 14.4.2 selecting the rx port one rx port can be selected per sampling routine. the port to be sampled is selected by can_rx_sel. table 14-3. internal multiplexer correspondence can_rx_sel rx selected 000 can0rx on pb[1] 001 can1rx on pc[11] 010 can2rx on pe[9]
chapter 14 can sampler MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 241 14.4.3 baud rate generation sampling is performed at a ba ud rate that is set by the software as a multiple of rc osci llator frequency of 62.5 ns (assuming rc is configured for high frequenc y mode, that is, 16 mhz). user must set the baud rate prescaler (brp) such that 8 samples per bit are achieved. baud rate setting must be made by software before going into standby or stop mode. this is done by setting brp bits 5:1 in control register. the reset value of brp is 00000 and can be set to maximum value of 11111, which gives a prescale value of brp + 1 thus providing a brp range of 1 to 32. ? maximum bit rate supported for sampling is 2 mbit/s using brp as 1 ? minimum bit rate supported for sa mpling is 62.5 kbit/s using brp as 32 for example, suppose the system is transmitting at 125 kbit/s. in this case, nominal bit period: t=1/(125 10 3 )s = 8 10 ?3 10 ?3 s= 8s eqn. 14-1 to achieve 8 samples per bit sample period= 8/8 s = 1 s brp = 1 s/62.5 ns = 16. thus in this case brp = 01111 011 can3rx on pe[9] 100 can4rx on pc[11] 101 can5rx on pe[0] 110 rx6 111 rx7 table 14-3. internal multiplexer correspondence (continued) can_rx_sel rx selected
chapter 14 can sampler MPC5606BK microcontroller reference manual, rev. 2 242 freescale semiconductor this page is intent ionally left blank.
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 243 ??? core platform modules ???
MPC5606BK microcontroller reference manual, rev. 2 244 freescale semiconductor this page is intent ionally left blank.
chapter 15 e200z0h core MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 245 chapter 15 e200z0h core 15.1 overview the e200 processor family is a set of cpu cores that implement co st-efficient versions of the power architecture. e200 processors are designed for deeply embedded control a pplications that require low cost solutions rather than maximum performance. the e200z0h processors integrate an integer execution unit, branch control unit, instruction fetch and load/store units, and a multi-ported re gister file capable of sustaining three read and two write operations per clock. most integer instructions execute in a sing le clock cycle. branch targ et prefetching is performed by the branch unit to allow single-cycle branches in some cases. the e200z0h core is a single-issue, 32-bit power ar chitecture technology vle- only design with 32-bit general purpose registers (gprs). all ar ithmetic instructions that execute in the core operate on data in the general purpose registers (gprs). instead of the base power architecture technology support, the e200z0h core only implements the vle (variable-length encoding) apu, providing improved code density. 15.2 microarchitecture summary the e200z0h processor utilizes a four stage pipeline for instruction ex ecution. the instruction fetch (stage 1), instruction decode/reg ister file read/effective address ca lculation (stage 2), execute/memory access (stage 3), and regist er writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. the integer execution unit consists of a 32-bit arithmet ic unit (au), a logic unit (lu), a 32-bit barrel shifter (shifter), a mask-inserti on unit (miu), a condition regist er manipulation unit (cru), a count-leading-zeros unit (clz), an 8x32 hardware multiplier array, re sult feed-forward hardware, and a hardware divider. arithmetic and logical operations ar e executed in a single cycle with the exception of the divide and multiply instructions. a c ount-leading-zeros unit operate s in a single clock cycle. the instruction unit contains a pc incrementer and a dedicated branch address a dder to minimize delays during change of flow operations. se quential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetch ing from the btb is performed to accelerate certain taken branches in the e200z0h. prefetch ed instructions are placed into an instruction buffer with 4entries in e200z0h, each capable of holding a single 32-bit instruction or a pair of 16-b it instructions. conditional branches that are not taken execute in a single clock. branches with successful target prefetching have an effective execu tion time of one clock on e200z0h. al l other taken branches have an execution time of two clocks. memory load and store operations are provided for byte, halfword, and word (32-bi t) data with automatic zero or sign extension of byte and halfword load da ta as well as optional byte reversal of data. these
chapter 15 e200z0h core MPC5606BK microcontroller reference manual, rev. 2 246 freescale semiconductor instructions can be pipelined to allow effective single cycle throughput. load and store multiple word instructions allow low overhead context save and restore operations. the load /store unit contains a dedicated effective address adder to allow effective addres s generation to be optimi zed. also, a load-to-use dependency does not incur any pipeline bubbles for most cases. the condition register unit supports the condition regi ster (cr) and condition re gister operations defined by the power architecture platform. th e condition register cons ists of eight 4-bit fi elds that reflect the results of certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions, and provide a mechanism for testing and branching. vectored and autovectored interrupt s are supported by the cpu. vectored interrupt support is provided to allow multiple interrupt sources to have unique in terrupt handlers invoked with no software overhead.
chapter 15 e200z0h core MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 247 15.3 block diagram figure 15-1. e200z0h block diagram 15.4 features the following is a list of some of the key features of the e200z0h core: ? 32-bit power architecture vle-only programmer?s model ? single issue, 32-bit cpu ? implements the vle apu for reduced code footprint ? in-order execution and retirement cpu control logic load/ data address store unit instruction unit branch unit pc unit instruction buffer gpr cr spr multiply unit data bus interface unit control 32 32 n once control logic interface control data (mtspr/mfspr) integer execution unit external spr ctr xer lr data address instruction bus interface unit control 32 32 n
chapter 15 e200z0h core MPC5606BK microcontroller reference manual, rev. 2 248 freescale semiconductor ? precise exception handling ? branch processing unit ? dedicated branch address calculation adder ? branch acceleration using branch target buffer ? supports independent instruction and data accesse s to different memory subsystems, such as sram and flash memory via independent instru ction and data bus in terface units (bius) (e200z0h only). ? load/store unit ? 1 cycle load latency ? fully pipelined ? big-endian support only ? misaligned access support ? zero load-to-use pipeline bu bbles for ali gned transfers ? power management ? low power design ? power saving modes: nap, sleep, and wait ? dynamic power management of execution units ? testability ? synthesizeable, full muxd scan design ? abist/mbist for optional memory arrays 15.4.1 instruction unit features the features of the e200 instruction unit are: ? 32-bit instruction fetch path s upports fetching of one 32-bit instru ction per clock, or as many as two 16-bit vle instructions per clock ? instruction buffer with 4 entries in e200z0h, each holding a single 32-bit inst ruction, or a pair of 16-bit instructions ? dedicated pc incrementer s upporting instruction prefetches ? branch unit with dedicated branch address adde r supporting single cycle of execution of certain branches, two cycles for all others 15.4.2 integer unit features the e200 integer unit supports single cycle ex ecution of most integer instructions: ? 32-bit au for arithmetic and comparison operations ? 32-bit lu for logical operations ? 32-bit priority encoder for count leading zeros function ? 32-bit single cycle barrel sh ifter for shifts and rotates
chapter 15 e200z0h core MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 249 ? 32-bit mask unit for data masking and insertion ? divider logic for signed and uns igned divide in 5 to 34 clocks with minimized execution timing ? 8 32 hardware multiplier arra y supports 1 to 4 cycle 32 32 ? 32 multiply (early out) 15.4.3 load/store unit features the e200 load/store unit supports lo ad, store, and the load multiple / store multiple instructions: ? 32-bit effective address adder fo r data memory address calculations ? pipelined operation supports throughput of one load or store operation per cycle ? 32-bit interface to memory (dedicated memory interface on e200z0h) 15.4.4 e200z0h system bus features the features of the e200z0h system bus interface are as follows: ? independent instruction and data buses ?amba 1 ahb 2 lite rev 2.0 specification with support for arm v6 amba extensions ? exclusive access monitor ? byte lane strobes ? cache allocate support ? 32-bit address bus plus attr ibutes and control on each bus ? 32-bit read data bus for instruction interface ? separate uni-directional 32-bit r ead data bus and 32-bit write data bus for data interface ? overlapped, in-order accesses 15.5 core registers and programmer?s model this section describes the registers implemented in the e200z0h cores. it includes an overview of registers defined by the power architecture platform, highl ighting differences in how these registers are implemented in the e200 core, and provides a detail ed description of e200- specific registers. full descriptions of the architecture-def ined register set are provided in the power architecture specification. the power architecture defines regist er-to-register operations for all co mputational instructions. source data for these instructions are acces sed from the on-chip registers or are provided as immediate values embedded in the opcode. the three-regi ster instruction format allows sp ecification of a target register distinct from the two source register s, thus preserving the original data for use by other instructions. data is transferred between memory and registers wi th explicit load and store instructions only. figure 15-2 , and figure 15-1 show the e200 register set, including the registers that ar e accessible while in supervisor mode, and the registers that are acce ssible in user mode. the num ber to the right of the special-purpose registers (spr s) is the decimal number used in the in struction syntax to access the register (for example, the integer except ion register (xer) is spr 1). 1. advanced microcontroller bus architecture 2. advanced high performance bus
chapter 15 e200z0h core MPC5606BK microcontroller reference manual, rev. 2 250 freescale semiconductor note e200z0h is a 32-bit implementation of the power architecture specification. in this document, register bits ar e sometimes numbered from bit 0 (most significant bit) to 31 (least significant bit), rather than the book e numbering scheme of 32:63, t hus register bit numbers for some registers in book e are 32 higher. where appropriate, the book e defi ned bit numbers are shown in parentheses.
chapter 15 e200z0h core MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 251 figure 15-2. e200z0 supervisor mode program model sprs spr general exception handling/control registers save and restore machine state msr pvr processor control registers supervisor mode program model sprs sprg0 sprg1 spr 272 spr 273 srr0 srr1 csrr0 csrr1 dsrr0 1 dsrr1 1 spr 26 spr 27 spr 58 spr 59 spr 574 spr 575 processor id pir spr 286 interrupt vector prefix ivpr spr 63 debug registers 2 debug control dbcr0 dbcr1 dbcr2 dbcr3 1 spr 308 spr 309 spr 310 spr 561 instruction address compare iac1 iac2 iac3 iac4 spr 312 spr 313 spr 314 spr 315 data address compare dac1 dac2 spr 316 spr 317 1 - these e200-specific registers may not be supported by other power architecture processors. 2 - optional registers defined by the power architecture technology 3 - read-only registers processor version hardware implementation dependent 1 hid0 hid1 spr 1008 spr 1009 cache registers spr 9 general-purpose registers count register ctr spr 8 link register lr condition register cr gpr0 gpr1 gpr31 spr 515 cache configuration (read-only) l1cfg0 spr 1 xer xer general registers spr 287 debug status dbsr spr 304 system version 1 svr spr 1023 esr spr 62 exception syndrome data exception address dear spr 61 machine check syndrome register mcsr spr 572 btb control 1 spr 1013 bucsr btb register memory management registers process id pid0 spr 48 configuration (read only) spr 1015 mmucfg dvc1 dvc2 spr 318 spr 319
chapter 15 e200z0h core MPC5606BK microcontroller reference manual, rev. 2 252 freescale semiconductor this page is intent ionally left blank.
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 253 chapter 16 enhanced direct memory access (edma) 16.1 device-specific features ? 16 programmable channels to support independent 8- , 16-, or 32-bit single value or block transfers ? support of variable sized queues and circular queues ? source and destination address registers independe ntly configured to po st-incrementor remain constant ? each transfer initiated by peripheral, cpu, pe riodic timer interrupt or edma channel request ? peripheral edma request s ources possible from dspi, i 2 c, 10-bit adc, 12-bit adc, linflexd, and emios ? each edma channel able to optionally send interrupt request to cpu on completion of single value or block transfer ? dma transfers possible between system memori es and all accessible me mory mapped locations including peripheral and registers ? programmable edma channel m ux allows assignment of any ed ma source to any available edma channel with total of as many as 32 request sources ? dma supports the following functionality: ? scatter gather ? channel linking ? inner loop offset ?arbitration ? fixed group, fixed channel ? round robin group, fixed channel ? round robin group, round robin channel ? fixed group, round robin channel ? channel preemption ? cancel channel transfer ? interrupts ? the edma has a single interrupt request for each implemented channel and a combined edma error interrupt to flag transfer errors to the syst em. each channel edma interrupt can be enabled or disabled and pr ovides notification of a completed transfer. refer to the interrupt vector in chapter 18, interrupt controller (intc) , for the allocation of these interrupts. 16.2 introduction the enhanced direct memory access controller (edma) is a second-generation platfo rm block capable of performing complex data movements through 16 program mable channels, with mi nimal intervention from the host processor. the hardware microarchitectur e includes a dma engine th at performs source and destination address calculations, and the actual data movement opera tions, along with an sram-based
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 254 freescale semiconductor memory containing the transfer control descriptors (tcd) for th e channels. this implementation minimizes the overall block size. figure 16-1 is a block diagram of the edma module. figure 16-1. edma block diagram 16.2.1 features the edma module supports the following features: ? all data movement via dual-address transfer s: read from source, write to destination ? programmable source, destinat ion addresses, transfer size, plus support for enhanced addressing modes ? transfer control descriptor organized to support two-deep, nested transfer operations ?an inner data transfer loop defined by a minor byte transfer count ?an outer data transfer loop define d by a major iteration count ? channel service request via one of three methods: slave interface edma edma done system bus data path control address program model/ slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n ?1 edma peripheral bus read data channel arbitration request path sram transfer control descriptor ( tcd ) sram n = 16 channels
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 255 ? explicit software initiation ? initiation via a channel-to-channel li nking mechanism for c ontinuous transfers ? independent channel linking at end of minor loop and/or major loop ? peripheral-paced hardware requests (one per channel) ? for all three methods, one se rvice request per execution of the minor loop is required ? support for fixed-priority and round-robin channel arbitration ? channel completion reported vi a optional interrupt requests ? one interrupt per channel, optionally asse rted at completion of major iteration count ? error terminations are optionally enabled per ch annel, and logically summed together to form a small number of error interrupt outputs ? support for scatter/gath er edma processing ? support for complex data structures ? support to cancel transfers via software or hardware 16.3 memory map and register definition 16.3.1 memory map the edma memory map is shown in table 16-1 . the edma base addre ss is 0xfff4_4000. the address of each register is given as an offset to the edma base address. registers are listed in address order, identified by complete name and mnemonic, and list the type of accesses allowed. the edma?s programming model is partitioned into two regions?the first regi on defines a number of registers providing control f unctions; the second region corresponds to th e local transfer control descriptor memory. table 16-1. edma memory map base address: 0xfff4_4000 address offset register location 0x0000 edma_cr ? edma control register on page 257 0x0004 edma_esr ? edma error status register on page 259 0x0008 reserved 0x000c edma_erqrl ? edma enable request low register (channels 15?00) on page 261 0x0010 reserved 0x0014 edma_eeirl ? edma enable error interrupt low register (channels 15?00) on page 262 0x0018 edma_serqr ? edma set enable request register on page 263 0x0019 edma_cerqr ? edma clear enable request register on page 264 0x001a edma_seeir ? edma set ena ble error interrupt register on page 264 0x001b edma_ceeir ? edma clear enable error inte rrupt register on page 265
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 256 freescale semiconductor 0x001c edma_cirqr ? edma clear interrupt request register on page 265 0x001d edma_cer ? edma clear error register on page 266 0x001e edma_ssbr ? edma set start bit register on page 266 0x001f edma_cdsbr ? edma clear done status bit register on page 267 0x0020 reserved 0x0024 edma_irqrl ? edma interrupt request low register on page 267 0x0028 reserved 0x002c edma_erl ? edma error low register on page 268 0x0030 reserved 0x0034 edma_hrsl ? edma hardware request status register on page 269 0x0038 ? 0x01fc reserved 0x0100 edma_cpr0 ? edma channel 0 priority register on page 269 0x0101 edma_cpr1 ? edma channel 1 priority register on page 269 0x0102 edma_cpr2 ? edma channel 2 priority register on page 269 0x0103 edma_cpr3 ? edma channel 3 priority register on page 269 0x0104 edma_cpr4 ? edma channel 4 priority register on page 269 0x0105 edma_cpr5 ? edma channel 5 priority register on page 269 0x0106 edma_cpr6 ? edma channel 6 priority register on page 269 0x0107 edma_cpr7 ? edma channel 7 priority register on page 269 0x0108 edma_cpr8 ? edma channel 8 priority register on page 269 0x0109 edma_cpr9 ? edma channel 9 priority register on page 269 0x010a edma_cpr10 ? edma channel 10 priority register on page 269 0x010b edma_cpr11 ? edma channel 11 priority register on page 269 0x010c edma_cpr12 ? edma channel 12 priority register on page 269 0x010d edma_cpr13 ? edma channel 13 priority register on page 269 0x010e edma_cpr14 ? edma channel 14 priority register on page 269 0x010f edma_cpr15 ? edma channel 15 priority register on page 269 0x0110 reserved 0x1000 tcd00 ? edma transfer control descriptor 00 on page 271 0x1020 tcd01 ? edma transfer control descriptor 01 on page 271 0x1040 tcd02 ? edma transfer control descriptor 02 on page 271 table 16-1. edma memory map (continued) base address: 0xfff4_4000 address offset register location
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 257 16.3.2 register descriptions 16.3.2.1 dma control register (edma_cr) the 32-bit edma_cr defines the basic op erating configuration of the edma. arbitration among the channels can be configured to use a fixe d priority or a round r obin. in fixed-priority arbitration, the highest priority ch annel requesting service is selected to execute. the priorities are assigned by the channel priority registers (see section 16.3.2.16, dma channel n priority (edma_cprn)) ). in round-robin arbitration m ode, the channel priorities are ignored and the channels are cycled through, from channe l 15 down to channel 0, without regard to priority. see figure 16-2 and table 16-2 for the edma_cr definition. 0x1060 tcd03 ? edma transfer control descriptor 03 on page 271 0x1080 tcd04 ? edma transfer control descriptor 04 on page 271 0x10a0 tcd05 ? edma transfer control descriptor 05 on page 271 0x10c0 tcd06 ? edma transfer control descriptor 06 on page 271 0x10e0 tcd07 ? edma transfer control descriptor 07 on page 271 0x1100 tcd08 ? edma transfer control descriptor 08 on page 271 0x1120 tcd09 ? edma transfer control descriptor 09 on page 271 0x1140 tcd10 ? edma transfer control descriptor 10 on page 271 0x1160 tcd11 ? edma transfer control descriptor 11 on page 271 0x1180 tcd12 ? edma transfer control descriptor 12 on page 271 0x11a0 tcd13 ? edma transfer control descriptor 13 on page 271 0x11c0 tcd14 ? edma transfer control descriptor 14 on page 271 0x11e0 tcd15 ? edma transfer control descriptor 15 on page 271 0x1200 reserved table 16-1. edma memory map (continued) base address: 0xfff4_4000 address offset register location
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 258 freescale semiconductor offset: 0x0000 access: read/write 0123456789101112131415 r00000000000000 cx ecx w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 grp0pri emlm clm halt hoe erga erca edbg ebw w reset: 0 0 00000000000000 figure 16-2. dma control register (edma_cr) table 16-2. edma_cr field descriptions field description cx cancel transfer 0 normal operation. 1 cancel the remaining data transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect afte r the last write of the current read/write sequence. the cxfr bit clears itself after the cancel has been honored. this cancel retires the channel normally as if the minor loop was completed. ecx error cancel transfer 0 normal operation. 1 cancel the remaining data transfer in the same fashion as the cx cancel transfer. stop the executing channel and force the minor loop to be finished. the cancel takes effect after the last write of the current read/write sequence. the ecx bit clears itself after the cancel has been honored. in addition to cancelling the transfer, the ecx treats the cancel as an error condition; thus updating the edma_esr regist er and generating an optional error interrupt (see section 16.3.2.2, dma er ror status (edma_esr) ). grp0pri channel group 0 priority group 0 priority level when fixed priority group arbitration is enabled. emlm enable minor loop mapping 0 minor loop mapping disabled. tcdn.wor d2 is defined as a 32-bit nbytes field. 1 minor loop mapping enabled. when set, tcdn.word2 is redefined to include individual enable fields, an offset field and the nbytes field. the individual enable fields allow the minor loop offset to be applied to the source address, the destination address, or both. th e nbytes field is reduced when either offset is enabled. clm continuous link mode 0 a minor loop channel link made to itself will go through channel arbitration before being activated again. 1 a minor loop channel link made to itself will not go through channel arbitration before being activated again. upon minor loop completion the channel will active again if that channel has a minor loop channel link enabled and the link channel is itself. this effectively applies the minor loop offs ets and restarts the next minor loop. halt halt dma operations 0 normal operation. 1 stall the start of any new channels. executing channels are allowed to complete. channel execution will resume when the halt bit is cleared.
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 259 16.3.2.2 dma error status (edma_esr) the edma_esr provides information a bout the last recorded channel error. channel errors can be caused by a configuration error (an illegal sett ing in the transfer control descriptor or an illegal priority register setting in fixed-arbitra tion mode) or an error termination to a bus master read or write cycle. a configuration error is caused when the starting source or destinati on address, source or destination offsets, minor loop byte count, and th e transfer size represent an inc onsistent state. the addresses and offsets must be aligned on 0-modulo-transfer_size boundaries, and the minor loop byte count must be a multiple of the source and destinat ion transfer sizes. all source read s and destination writes must be configured to the natural boundary of th e programmed transfer size respectively. in fixed-arbitration mode, a configur ation error is generated when any tw o channel priority levels are equal and any channel is activated. the errchn field is undefi ned for this type of error. all channel priority levels must be unique before any service requests are made. if a scatter-gather operation is en abled on channel completion, a configuration error is reported if the scatter-gather address (dlast_s ga) is not aligned on a 32-byte bounda ry. if minor loop channel linking is enabled on channel completion, a c onfiguration error is reported when the link is attempted if the tcd.citer.e_link bit is not equal to the tcd.biter .e_link bit. all confi guration error conditions except scatter-gather and minor loop li nk error are reported as the channel is activated and assert an error interrupt request if enabled. when properly enabled, a scatter-gather configuration error is reported when the scatter-gather operation begins at major loop completion. a minor loop ch annel link configuration error is reported when the link operation is serviced at minor loop completion. if a system bus read or wr ite is terminated with an error, the data transfer is immediately stopped and the appropriate bus error flag is set. in this case, the state of the channe l?s transfer control descriptor is updated by the dma engine with the current s ource address, destination address, and minor loop byte count at the point of the fault. if a bus error occurs on the last read prior to beginning the write seque nce, the write will hoe halt on error 0 normal operation. 1 any error will cause the halt bit to be set. subsequently, all service requests will be ignored until the halt bit is cleared. erga enable round robin group arbitration 0 fixed priority arbitration is used for selection among the groups. 1 round robin arbitration is used for selection among the groups. erca enable round robin channel arbitration 0 fixed priority arbitration is used for channel selection within each group. 1 round robin arbitration is used for channel selection within each group. edbg enable debug 0 the assertion of the device debug mode is ignored. 1 the assertion of the device debug mode causes the edma to stall the start of a new channel. executing channels are allowed to complete. channel execution will resume when either the device comes out of de bug mode or the edbg bit is cleared. ebw 0 the bufferable write signal (hprot [2]) is not asserted during amba ahb writes. 1 the bufferable write signal (hprot[2]) is asserted on all amba ahb writes except for the last write sequence. table 16-2. edma_cr field descriptions (continued) field description
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 260 freescale semiconductor execute using the data captur ed during the bus error. if a bus error o ccurs on the last write prior to switching to the next read sequence, the read sequence will ex ecute before the channel is terminated due to the destination bus error. the occurrence of any type of erro r causes the dma engine to stop the active channel and the appropriate channel bit in the edma error register to be asserte d. at the same time, the details of the error condition are loaded into the edma_esr. the major loop comp lete indicators, setti ng the transfer control descriptor done flag and the possibl e assertion of an interr upt request, are not affect ed when an error is detected. after the error status has been updated, th e dma engine continues to operate by servicing the next appropriate channel. a channel that experiences an error condition is not automatically disabled. if a channel is terminated by an error a nd then issues another service request before the error is fixed, that channel will execute and terminat e with the same error condition. offset: 0x0004 access: read 0123456789101112131415 rvld000000000000000 w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 cpe errchn[0:5] sae soe dae doe nce sge sbe dbe w reset: 0 0 00000000000000 figure 16-3. dma error status (edma_esr) register table 16-3. edma_esr field descriptions field description vld logical or of all edma_erl status bits. 0 no edma_erl bits are set. 1 at least one edma_erl bit is set indicati ng a valid error exists that has not been cleared. cpe channel priority error 0 no channel priority error. 1 the last recorded error was a configuration error in the channel priorities within a group. all channel priorities within a group are not unique. errchn[0:5] error channel number or cancelled channel number the channel number of the last recorded error (excluding gpe and cpe errors) or last recorded transfer that was error cancelled. sae source address error 0 no source address configuration error. 1 the last recorded error was a configuration error detected in the tcd.saddr field. tcd.saddr is inconsistent with tcd.ssize. soe source offset error 0 no source offset configuration error. 1 the last recorded error was a configurati on error detected in the tcd.soff field. tcd.soff is inconsistent with tcd.ssize.
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 261 16.3.2.3 dma enable request (edma_erqrl) the edma_erqrl provides a bit map for the 16 channels to enable the request signal for each channel. edma_erqrl maps to channels 15?0. the state of any given channel enable is directly affected by writes to this register; the state is also affected by writes to the edma_serqr, and edma_c erqr registers. the edma_cerqr and edma_serqr registers are provided so the request enable fo r a single channel can be modified without performing a read-modify-write seque nce to the edma_erqrl register. both the edma request input signal and this enable request flag must be asse rted before a channel?s hardware service request is accepted. the state of the edma enable request flag does not affect a channel service request made through software or a linked channel request. dae destination address error 0 no destination address configuration error. 1 the last recorded error was a configuration error detected in the tcd.daddr field. tcd.daddr is inconsistent with tcd.dsize. doe destination offset error 0 no destination offset configuration error. 1 the last recorded error was a configuration error detected in the tcd.doff field. tcd.doff is inconsistent with tcd.dsize. nce nbytes/citer c onfiguration error 0 no nbytes/citer configuration error. 1 the last recorded error was a configuratio n error detected in the tcd.nbytes or tcd.citer fields. tcd.nbytes is not a multiple of tcd.ssize and tcd.dsize, or tcd.citer is equal to zero, or tcd.citer.e_link is not equal to tcd.biter.e_link. sge scatter/gather configuration error 0 no scatter/gather configuration error. 1 the last recorded error was a configuratio n error detected in the tcd.dlast_sga field. this field is checked at the beginning of a scatter/gather operat ion after major loop completion if tcd.e_sg is enabled. tcd.dlast_sga is not on a 32 byte boundary. sbe source bus error 0 no source bus error. 1 the last recorded error was a bus error on a source read. dbe destination bus error 0 no destination bus error. 1 the last recorded error was a bus error on a destination write. table 16-3. edma_esr field descriptions (continued) field description
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 262 freescale semiconductor as a given channel completes the processing of its majo r iteration count, there is a flag in the transfer control descriptor that may affect the ending state of the edma_erqrl bit for that channel. if the tcd.d_req bit is set, then the corresponding edma_erqrl bit is cleared, disabl ing the edma request; else if the d_req bit is cleared, the st ate of the edma_erqrl bit is unaffected. 16.3.2.4 dma enable error interrupt (edma_eeirl) the edma_eeirl provides a bit map for the 16 channe ls to enable the error interrupt signal for each channel. edma_eeirl maps to channels 15?0. the state of any given channel?s error interrupt enable is directly affected by writes to these registers; it is also affected by writes to the edma_seeir and edma_ceeir register s. the edma_seeir and edma_ceeir registers are provided so that the er ror interrupt enable for a single channel can be modified without the performi ng a read-modify-write sequence to the edma_eeirl register. both the edma error indicator and this error interrupt enable flag must be asserted before an error interrupt request for a give n channel is asserted. see figure 16-5 and table 16-5 for the edma_eeirl definition. offset: 0x000c access: read/write 0123456789101112131415 r0000000000000000 w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r erq15 erq14 erq13 erq12 erq11 erq10 erq09 erq08 erq07 erq06 erq05 erq04 erq03 erq02 erq01 erq00 w reset: 0 0 00000000000000 figure 16-4. dma enable request (edma_erqrl) registers table 16-4. edma_erqrl field descriptions field description erqn enable edma request n 0 the edma request signal for channel n is disabled. 1 the edma request signal for channel n is enabled.
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 263 16.3.2.5 dma set enable request (edma_serqr) the edma_serqr provides a simple memory-ma pped mechanism to set a given bit in the edma_erqrl to enable the edma re quest for a given channel. the data value on a register write causes the corresponding bit in the edma_erqrl to be se t. setting bit 1 (serq[ 0]) provides a global set function, forcing the entire contents of edma_erqrl to be asserted. r eads of this register return all zeroes. offset: 0x0014 access: read/write 0123456789101112131415 r0000000000000000 w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eei15 eei14 eei13 eei12 eei11 eei10 eei09 eei08 eei07 eei06 eei05 eei04 eei03 eei02 eei01 eei00 w reset: 0 0 00000000000000 figure 16-5. dma enable error interrupt (edma_eeirl) register table 16-5. edma_eeirl field descriptions field description eein enable error interrupt n 0 the error signal for channel n does not generate an error interrupt. 1 the assertion of the error signal for channel n generate an error interrupt request. offset: 0x0018 access: write 01234567 r00000000 w serq reset: 00000000 figure 16-6. dma set enable request (edma_serqr) register table 16-6. edma_serqr field descriptions field description serq set enable request 0?15 set the corresponding bit in edma_erqrl 64?127 set all bits in edma_erqrl
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 264 freescale semiconductor 16.3.2.6 dma clear enable request (edma_cerqr) the edma_cerqr provides a simp le memory-mapped mechanism to clear a given bit in the edma_erqrl to disable the edma request for a given channel. the data value on a register write causes the corresponding bit in th e edma_erqrl to be cleared. se tting bit 1 (cerq[0]) provides a global clear function, forcing the enti re contents of the edma_erqrl to be zeroed, disa bling all edma request inputs. reads of this re gister return all zeroes. see figure 16-7 and table 16-7 for the edma_cerqr definition. 16.3.2.7 dma set enable er ror interrupt (edma_seeir) the edma_seeir provides a memory-mapped mechanis m to set a given bit in the edma_eeirl to enable the error interrupt for a gi ven channel. the data value on a re gister write causes the corresponding bit in the edma_eeirl to be set. setting bit 1 (see i[0]) provides a global set function, forcing the entire contents of edma_eeirl to be asserted. reads of this regi ster return all zeroes. see figure 16-8 and table 16-8 for the edma_seeir definition. offset: 0x0019 access: write 01234567 r00000000 w cerq reset: 00000000 figure 16-7. dma clea r enable request (edma_cerqr) register table 16-7. edma_cerqr field descriptions field description cerq clear enable request 0?63 clear corresponding bit in edma_erqrl 64?127 clear all bits in edma_erqrl offset: 0x001a access: write 01234567 r00000000 w seei reset: 00000000 figure 16-8. dma set enable error interrupt (edma_seeir) register table 16-8. edma_seei r field descriptions name description seei set enable error interrupt 0?63 set the corresponding bit in edma_eeirl 64?127 set all bits in edma_eeirl
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 265 16.3.2.8 dma clear enable error interrupt (edma_ceeir) the edma_ceeir provides a memory-m apped mechanism to clear a give n bit in the edma_eeirl to disable the error inte rrupt for a given channel. the data value on a register write ca uses the corresponding bit in the edma_eeirl to be cleared. setting bit 1 (ceei[0]) provides a global clear function, forcing the entire contents of the edma_eeirl to be zeroe d, disabling error interrupts for all channels. reads of this register returns all zeroes. see figure 16-9 and table 16-9 for the edma_ceeir definition. 16.3.2.9 dma clear interru pt request (edma_cirqr) the edma_cirqr provides a memory -mapped mechanism to clear a gi ven bit in the edma_irqrl to disable the interrupt request for a given channel. the given value on a register write causes the corresponding bit in the edma_irq rl to be cleared. setting bit 1 (cint[0]) provide s a global clear function, forcing the entire contents of the edma_irqrl to be zero ed, disabling all edma interrupt requests. reads of this regi ster return all zeroes. see figure 16-10 and table 16-10 for the edma_cirqr definition. offset: 0x001b access: write 01234567 r00000000 w ceei[0:6] reset: 00000000 figure 16-9. dma clear enable error interrupt (edma_ceeir) register table 16-9. edma_ceeir field descriptions field description ceei clear enable error interrupt 0?63 clear corresponding bit in edma_eeirl 64?127 clear all bits in edma_eeirl offset: 0x001c access: write 01234567 r00000000 w cint reset: 00000000 figure 16-10. dma clear interrupt request (edma_cirqr) fields table 16-10. edma_cirqr field descriptions field description cint[0:6] clear interrupt request 0?63 clear the corresponding bit in edma_irqrl 64?127 clear all bits in edma_irqrl
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 266 freescale semiconductor 16.3.2.10 dma clear error (edma_cer) the edma_cer provides a memory-mapped mechanis m to clear a given bit in the edma_erl to disable the error condition flag fo r a given channel. the given valu e on a register write causes the corresponding bit in the edma_erl to be cleared. setting bit 1 (cerr[0]) provides a global clear function, forcing the entire contents of the edma_erl to be zeroe d, clearing all channe l error indicators. reads of this register return all zeroes. see figure 16-11 and table 16-11 for the edma_cer definition. 16.3.2.11 dma set start bit (edma_ssbr) the edma_ssbr provides a memory-mapped mechanism to set the start bit in the tcd of the given channel. the data value on a regist er write causes the start bit in the corresponding transfer control descriptor to be set. set ting bit 1 (ssb[0]) provides a global set function, forcing all start bits to be set. reads of this register return all zeroes. see table 16-19 for the tcd start bit definition. offset: 0x001d access: write 01234567 r00000000 w cerr reset: 00000000 figure 16-11. dma clear error (edma_cer) register table 16-11. edma_cer field descriptions field description cerr clear error indicator 0?63 clear corresponding bit in edma_erl 64?127 clear all bits in edma_erl offset: 0x001e access: write 01234567 r00000000 w ssrt reset: 00000000 figure 16-12. dma set start bit (edma_ssbr) register table 16-12. edma_ssbr field descriptions field description ssrt set start bit (channel service request) 0?63 set the corresponding channel?s tcd.start 64?127 set all tcd.start bits
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 267 16.3.2.12 dma clear done status (edma_cdsbr) the edma_cdsbr provides a memory-mapped mechanis m to clear the done bit in the tcd of the given channel. the data value on a re gister write causes the done bit in the corres ponding transfer control descriptor to be cleare d. setting bit 1 (cdsb[0]) provides a globa l clear function, forcing all done bits to be cleared. see table 16-19 for the tcd done bit definition. 16.3.2.13 dma interrupt request (edma_irqrl) the edma_irqrl provides a bit map for the 16 channe ls signaling the presence of an interrupt request for each channel. edma_irq rl maps to channels 15?0. the dma engine signals the occurrence of a program med interrupt on the completion of a data transfer as defined in the transfer control descriptor by setting the appropriate bit in this register. the outputs of this register are directly routed to the interrupt controller (intc). during the execution of the interrupt service routine associated with any given channel, so ftware must clear the appr opriate bit, negating the interrupt request. typically, a write to the edma_cirqr in the interrupt service routine is used for this purpose. the state of any given channel?s interr upt request is directly affected by wr ites to this register; it is also affected by writes to the edma_cirqr. on writes to the edma_i rqrl, a 1 in any bit position clears the corresponding channel?s interrupt request. a 0 in any bit position has no af fect on the corresponding channel?s current interrupt status. the edma_cirqr is provided so the interrupt request for a single channel can be cleared without performing a read -modify-write sequence to the edma_irqrl. see figure 16-14 and table 16-14 for the edma_irql definition. offset: 0x001f access: write 01234567 r00000000 w cdne[0:6] reset: 00000000 figure 16-13. dma clear done status (edma_ cdsbr) register table 16-13. edma_cdsbr field descriptions field description cdne[0:6] clear done status bit 0?63 clear the corresponding channel?s done bit 64?127 clear all tcd done bits
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 268 freescale semiconductor 16.3.2.14 dma error (edma_erl) the edma_erl provides a bit map for the 16 channels signaling the presence of an error for each channel. edma_erl ma ps to channels 15?0. the dma engine signals the occurren ce of a error condition by setting the appropriate bit in this register. the outputs of this register are enabled by the contents of the ed ma_eeir, then logi cally summed across 16 channels to form an error interr upt request, which is then routed to the interrupt controller. during the execution of the interrupt se rvice routine associated wi th any edma errors, it is software?s responsibility to clear the appropriate bit, negating the error interr upt request. typically, a write to the edma_cer in the interrupt service routine is used for this pur pose. the normal edma channel completion indicators, setting the transfer control descript or done flag and the possible asserti on of an interrupt request, are not affected when an error is detected. the contents of this register can also be polled. a non- zero value indicates the pres ence of a channel error, regardless of the state of the edma _eeir. the edma_esr[vld] bit is a logical or of all bits in this register, and it provides a single bit indication of any errors. the state of any given channel?s error indicators is affected by writes to this register; it is also affected by writes to the edma_cer. on writes to edma_erl, a 1 in any bit position clears the corresponding channel?s error status. a 0 in any bit position has no affect on the corresponding channel?s current error status. the edma_cer is provided so the error indicator for a si ngle channel can be cleared. see figure 16-15 and table 16-15 for the edma_erl definition. offset: 0x0024 access: read/write 0123456789101112131415 r0000000000000000 w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r int15 int14 int13 int12 int11 int10 int09 int08 int07 int06 int05 int04 int03 int02 int01 int00 w reset: 0 0 00000000000000 figure 16-14. dma interrupt request (edma_irqrl) registers table 16-14. edma_irqrl field descriptions field description intn dma interrupt request n 0 the interrupt request for channel n is cleared. 1 the interrupt request for channel n is active.
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 269 16.3.2.15 dma hardware re quest status (edma_hrsl) the edma_hrsl register provides a bi t map for the implemented channels to show the current hardware request status for each channel. this view into the hardware request signals may be used for debug purposes. see figure 16-16 and figure 16-16 for the edma_hrsl definition. offset: 0x002c access: read/write 0123456789101112131415 r0000000000000000 w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r err15 err14 err13 err12 err11 err10 err09 err08 err07 err06 err05 err04 err03 err02 err01 err00 w reset: 0 0 00000000000000 figure 16-15. dma error (edma_erl) registers table 16-15. edma_erl field descriptions field description errn dma error n 0 an error in channel n has not occurred. 1 an error in channel n has occurred. offset: 0x0034 access: read/write 0123456789101112131415 r0000000000000000 w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r hrs15 hrs14 hrs13 hrs12 hrs11 hrs10 hrs09 hrs08 hrs07 hrs06 hrs05 hrs04 hrs03 hrs02 hrs01 hrs00 w reset: 0 0 00000000000000 figure 16-16. dma hardware request status (edma_hrsl) register
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 270 freescale semiconductor 16.3.2.16 dma channel n priority (edma_cprn) when the fixed-priority channel ar bitration mode is enabled (edma_ cr[erca] = 0), the contents of these registers define the unique priorities associ ated with each channel. the channel priorities are evaluated by numeric value; th at is, 0 is the lowest priority, 1 is th e next higher priority, then 2, 3, etc. if software modifies channel priority va lues, then the software must ensure that the channel priorities contain unique values, otherwise a configurati on error will be reported. the range of the priority value is limited to the values of 0 through 15. channel preemption is enabled on a per-channel basis by setting the ecp bit in the edma_cprn register. channel preemption allows the executin g channel?s data transfers to be temporarily suspended in favor of starting a higher priority channel. after the preempting channel has completed all its minor loop data transfers, the preempted channel is restored and resumes execution. af ter the restored channel completes one read/write sequence, it is agai n eligible for preemption. if any highe r priority channel requests service, the restored channel will be suspe nded and the higher prior ity channel will be serv iced. nested preemption (attempting to preempt a preempting channel) is not supported. after a preempting channel begins execution, it cannot be preem pted. preemption is availa ble only when fixed arbitration is selected for channel arbitration mode a channel?s ability to preempt another channel can be disabled by setting the dpa bit in the edma_cprn register. when a channel?s preempt ability is disa bled, that channel cannot suspend a lower priority channel?s data transfer; regardless of the lower priority channel?s ecp setting. this allo ws for a pool of low priority, large data moving channels to be define d. these low priority channe ls can be configured to not preempt each other, thus preven ting a low priority channel from c onsuming the preempt slot normally available a true, high pr iority channel. see figure 16-17 and table 16-17 for the edma_cprn definition. table 16-16. edma_hrsl field descriptions field description hrsn dma hardware request status n 0 a hardware service request for channel n is not present. 1 a hardware service request for channel n is present. note: the hardware request status reflects the stat e of the request as seen by the arbitration logic. therefore, this status is affected by the edma_erqrl[n] bit. offset: 0x0100 + n access: read/write 01234567 r ecp dpa grppri chpri w reset: 0 0 ****** * = defaults to channel number (n) after reset figure 16-17. dma channel n pr iority (edma_cprn) register
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 271 16.3.2.17 transfer control descriptor (tcd) each channel requires a 32-byte tr ansfer control descriptor for de fining the desired data movement operation. the channel de scriptors are stored in the local memory in sequential order: channel 0, channel 1,... channel 15. the definitions of the tcd are presented as eight 32-bit values. table 16-18 is a field list of the basic tcd structure. figure 16-18 and table 16-19 define the fields of the tcd n structure. table 16-17. edma_cprn field descriptions field description ecp enable channel preemption 0 channel n cannot be suspended by a higher priority channel?s service request. 1 channel n can be temporarily suspended by the service request of a higher priority channel. dpa disable preempt ability 0 channel n can suspend a lower priority channel. 1 channel n cannot suspend any channel, regardless of channel priority. chpri[0:3] channel n arbitration priority channel priority when fixed-priority arbitration is enabled. table 16-18. tcdn 32-bit memory structure edma offset tcdn field 0x1000+(32 n)+0x0000 source address (saddr) 0x1000+(32 n)+0x0004 transfer attribut es signed source address offset (soff) 0x1000+(32 n)+0x0008 inner minor byte count (nbytes) 0x1000+(32 n)+0x000c last source address adjustment (slast) 0x1000+(32 n)+0x0010 destination address (daddr) 0x1000+(32 n)+0x0014 current major iteration coun t (citer) signed destination address offset (doff) 0x1000 (32 n) 0x0018 last destination address adjustment / scatter-gather address (dlast_sga) 0x1000+(32 n)+0x001c beginning major iter ation count (biter) channel control/status
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 272 freescale semiconductor note the tcd structures for the edma channels shown in figure 16-18 are implemented in internal sram. these stru ctures are not initialized at reset; therefore, all channel tcd parameters must be initialized by the application code before activating that channel. word offset 012345678910111213141516171819202122232425262728293031 0x0000 saddr 0x0004 smod ssize dmod dsize soff 0x0008 nbytes 1 1 the fields implemented in word 2 depend on whether edma_cr(emlm) is set to 0 or 1. see table 16-2 . 0x8 smloe 1 dmloe 1 mloff or nbytes 1 nbytes 1 0x000c slast 0x0010 daddr 0x0014 citer.e_ link citer or citer.linkch citer doff 0x0018 dlast_sga 0x001c biter.e_ link biter or biter.linkch biter bwc major linkch done active major.e_link e_sg d_req int_half int_maj start 012345678910111213141516171819202122232425262728293031 figure 16-18. tcd structure
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 273 table 16-19. tcd n field descriptions bits / word offset [n:n] name description 0?31 / 0x0 [0:31] saddr [0:31] source address. memory address pointing to the source data. word 0x0, bits 0?31. 32?36 / 0x4 [0:4] smod [0:4] source address modulo. 0 source address modulo feature is disabled. non-0 this value defines a specific address range that is specified to be the value after saddr + soff calculation is performed or the original register value. the setting of this field provides the ability to easily implement a circular data queue. for data queues requiring power-of-2 size bytes, the queue should start at a 0-modulo-size address and the smod field should be set to the appropriate value for the queue, freezing the desired number of upper address bits. the value programmed into this fi eld specifies the number of lower address bits that are allowed to change. for this circular queue application, the soff is typically set to the transfer size to implement post-increment addressing with the sm od function constraining the addresses to a 0-modulo-size range. 37?39 / 0x4 [5:7] ssize [0:2] source data transfer size. 000 8-bit 001 16-bit 010 32-bit 011 reserved 100 16-byte (32-bit, 4-beat, wrap4 burst) 101 32-byte (32-bit, 8-beat, wrap8 burst) 110 reserved 111 reserved the attempted specification of a rese rved encoding causes a configuration error. 40?44 / 0x4 [8:12] dmod [0:4] destination address modulo. see the smod[0:5] definition. 45?47 / 0x4 [13:15] dsize [0:2] destination data transfer size . see the ssize[0:2] definition. 48?63 / 0x4 [16:31] soff [0:15] source address signed offset. sign-ex tended offset applied to the current source address to form the next-state value as each source read is completed. 64?95 / 0x8 [0:31] nbytes [0:31] inner minor byte transfer count. number of bytes to be transferred in each service request of the channel. as a c hannel is activated, the contents of the appropriate tcd is loaded into the dma engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. after the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. note: the nbytes value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 gb transfer.
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 274 freescale semiconductor 64?95 / 0x8 [0:31] nbytes 1 [0:31] inner minor byte transfer count. number of bytes to be transferred in each service request of the channel. as a c hannel is activated, the contents of the appropriate tcd is loaded into the edma engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. once the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. note: the nbytes value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 gbyte transfer. 64 0x8 [0] smloe 1 0 source minor loop offset enable this flag selects whether the minor loop offset is applied to the source address upon minor loop completion. 0 the minor loop offset is not applied to the saddr. 1 the minor loop offset is applied to the saddr. 65 0x8 [1] dmloe 1 1 destination minor loop offset enable this flag selects whether the minor l oop offset is applied to the destination address upon minor loop completion. 0 the minor loop offset is not applied to the daddr. 1 the minor loop offset is applied to the daddr. 66?85 0x8 [2:21] mloff or nbytes 1 [0:19] inner minor byte transfer count or minor loop offset if both smloe and dmloe are cleared, this field is part of the byte transfer count. if either smloe or dmloe are set, th is field represents a sign-extended offset applied to the source or destination address to form the next-state value after the minor loop is completed. 86?95 / 0x8 [22:31] nbytes 1 inner minor byte transfer count. number of bytes to be transferred in each service request of the channel. as a c hannel is activated, the contents of the appropriate tcd is loaded into the edma engine, and the appropriate reads and writes performed until the complete byte transfer count has been transferred. this is an indivisible operation and cannot be stalled or halted. once the minor count is exhausted, the current values of the saddr and daddr are written back into the local memory, the major iteration count is decremented and restored to the local memory. if the major iteration count is completed, additional processing is performed. note: the nbytes value of 0x0000_0000 is interpreted as 0x1_0000_0000, thus specifying a 4 gbyte transfer. 96?127 / 0xc [0:31] slast [0:31] last source address adjustment. adju stment value added to the source address at the completion of the oute r major iteration count. this value can be applied to restore the source address to the initial value, or adjust the address to reference t he next data structure. 128?159 / 0x10 [0:31] daddr [0:31] destination address. memory address pointing to the destination data. table 16-19. tcd n field descriptions (continued) bits / word offset [n:n] name description
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 275 160 / 0x14 [0] citer.e_link enable channel-to-channel linking on minor loop completion. as the channel completes the inner minor loop, this flag enables the linking to another channel, defined by citer.li nkch[0:5]. the link target channel initiates a channel service request via an internal mechanism that sets the tcd.start bit of the specified channel. if channel linking is disabled, the citer value is extended to 15 bits in place of a link channel number. if the major loop is exhausted, this link mechanism is suppressed in favor of the major.e_link channel linking. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. note: this bit must be equal to the biter.e_link bit otherwise a configuration error will be reported. 161?166 / 0x14 [1:6] citer [0:5] or citer.linkch [0:5] current major iteration count or link channel number. if channel-to-channel linking is disa bled (tcd.citer.e_link = 0), then ? no channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. tcd bits [161:175] are used to form a 15-bit citer field. otherwise, ? after the minor loop is exhausted, the dma engine initiates a channel service request at the channel defined by citer.linkch[0:5] by setting that channel?s tcd.start bit. 167?175 / 0x14 [7:15] citer [6:14] current major iteration count. this 9- or 15-bit count represents the current major loop count for the channel. it is decremented each time the minor loop is completed and updated in the transfer control descriptor memory. after the major iteration count is exha usted, the channel performs a number of operations (for example, final source and destination address calculations), optionally generating an interrupt to signal channel completion before reloading the citer field from the beginning iteration count (biter) field. note: when the citer field is initially loaded by software, it must be set to the same value as that contained in the biter field. note: if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. 176?191 / 0x14 [16:31] doff [0:15] destination address signed offset. sign-extended offset applied to the current destination address to form the next-state value as each destination write is completed. table 16-19. tcd n field descriptions (continued) bits / word offset [n:n] name description
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 276 freescale semiconductor 192?223 / 0x18 [0:31] dlast_sga [0:31] last destination address adjustment or the memory address for the next transfer control descriptor to be loade d into this channel (scatter-gather). if scatter-gather processing for the channel is disabled (tcd.e_sg = 0) then ? adjustment value added to the destination address at the completion of the outer major iteration count. this value can be applied to restore the destination address to the initial value, or adjust the address to reference the next data structure. otherwise, ? this address points to the beginning of a 0-modulo-32 byte region containing the next transfer control descriptor to be loaded into this channel. this channel reload is performed as the major iteration count completes. the scatte r-gather address must be 0-modulo-32 byte, otherwise a configuration error is reported. 224 / 0x1c [0] biter.e_link enables channel-to-channel linkin g on minor loop complete. as the channel completes the inner minor loop, this flag enables the linking to another channel, defined by bite r.linkch[0:5]. the link target channel initiates a channel service request via an internal mechanism that sets the tcd.start bit of the specified channel. if channel linking is disabled, the biter value is extended to 15 bits in pl ace of a link channel number. if the major loop is exhausted, this link mechanism is suppressed in favor of the major.e_link channel linking. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. note: when the tcd is first loaded by software, this field must be set equal to the corresponding citer field, otherwise a configuration error will be reported. as the major iteration count is exhausted, the contents of this field is reloaded into the citer field. 225?230 / 0x1c [1:6] biter [0:5] or biter.linkch[0:5] starting major iteration count or link channel number. if channel-to-channel linking is disabled (tcd.biter.e_link = 0), then ? no channel-to-channel linking (or chaining) is performed after the inner minor loop is exhausted. tcd bits [225:239] are used to form a 15-bit biter field. otherwise, ? after the minor loop is exhausted, the dma engine initiates a channel service request at the channel, de fined by biter. linkch[0:5], by setting that channel?s tcd.start bit. note: when the tcd is first loaded by software, this field must be set equal to the corresponding citer field, otherwise a configuration error will be reported. as the major iteration count is exhausted, the contents of this field is reloaded into the citer field. 231?239 / 0x1c [7:15] biter [6:14] starting major iteration count. as the transfer control descriptor is first loaded by software, this field must be equal to the value in the citer field. as the major iteration count is exhaus ted, the contents of this field are reloaded into the citer field. note: if the channel is configured to execute a single service request, the initial values of biter and citer should be 0x0001. table 16-19. tcd n field descriptions (continued) bits / word offset [n:n] name description
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 277 240?241 / 0x1c [16:17] bwc [0:1] bandwidth control. this 2-bit field provides a mechanism to effectively throttle the amount of bus bandwidth consumed by the edma. in general, as the edma processes the inner minor loop, it continuously generates read/write sequences until the minor co unt is exhausted. this field forces the edma to stall after the completion of each read/write access to control the bus request bandwidth seen by the system bus crossbar switch (xbar). 00 no dma engine stalls 01 reserved 10 dma engine stalls for 4 cycles after each r/w 11 dma engine stalls for 8 cycles after each r/w 242?247 / 0x1c [18:23] major.linkch [0:5] link channel number. if channel-to-channel linking on major loop complete is disabled (tcd.major.e_link = 0) then, ? no channel-to-channel linking (or chaining) is performed after the outer major loop counter is exhausted. otherwise ? after the major loop counter is ex hausted, the dma engine initiates a channel service request at the chann el defined by major.linkch[0:5] by setting that channel?s tcd.start bit. 248 / 0x1c [24] done channel done. this flag indicates the edma has completed the outer major loop. it is set by the dma engine as the citer count reaches zero; it is cleared by software or hardware when the channel is activated (when the dma engine has begun processing the channel, not when the first data transfer occurs). note: this bit must be cleared to writ e the major.e_link or e_sg bits. 249 / 0x1c [25] active channel active. this flag signals the channel is currently in execution. it is set when channel service begins, and is cleared by the dma engine as the inner minor loop completes or if any error condition is detected. 250 / 0x1c [26] major.e_link enable channel-to-channel lin king on major loop completion. as the channel completes the outer major loop, this flag enables the linking to another channel, defined by major.link ch[0:5]. the link target channel initiates a channel service request via an internal mechanism that sets the tcd.start bit of the specified channel. note: to support the dynamic linking coherency model, this field is forced to zero when written to while the tcd.done bit is set. 0 the channel-to-channel linking is disabled. 1 the channel-to-channel linking is enabled. table 16-19. tcd n field descriptions (continued) bits / word offset [n:n] name description
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 278 freescale semiconductor 16.4 functional description this section provides an overview of the microarchitectur e and functional operati on of the edma block. 251 / 0x1c [27] e_sg enable scatter-gather processing. as the channel completes the outer major loop, this flag enables scatter-gather processing in the current channel. if enabled, the dma engine uses dlast_sga as a memory pointer to a 0-modulo-32 address containing a 32-byte data structure that is loaded as the transfer control descriptor into the local memory. note: to support the dynamic scatter-gather coherency model, this field is forced to zero when written to while the tcd.done bit is set. 0 the current channel?s tcd is normal format. 1 the current channel?s tcd specifies a scatter gather format. the dlast_sga field provides a memory pointer to the next tcd to be loaded into this channel after the outer major loop completes its execution. 252 / 0x1c [28] d_req disable hardware request. if this flag is set, the edma hardware automatically clears the corresponding edma_erqrl bit when the current major iteration count reaches zero. 0 the channel?s edma_erqrl bit is not affected. 1 the channel?s edma_erqrl bit is cleared when the outer major loop is complete. 253 / 0x1c [29] int_half enable an interrupt when major counter is half complete. if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the edma_erqrl when the current major iteration count reaches the halfway point. specifically, the comp arison performed by the edma engine is (citer == (biter >> 1)). this halfway point interrupt request is provided to support double-buffered (also known as ping-pong) schemes, or other types of data movement where the pr ocessor needs an early indication of the transfer?s progress. citer = biter = 1 with int_half enabled will generate an interrupt as it satisfies the equation (citer == (biter >> 1)) after a single activation. 0 the half-point interrupt is disabled. 1 the half-point interrupt is enabled. 254 / 0x1c [30] int_maj enable an interrupt when major iteration count completes. if this flag is set, the channel generates an interrupt request by setting the appropriate bit in the edma_erqrl when the current ma jor iteration count reaches zero. 0 the end-of-major loop interrupt is disabled. 1 the end-of-major loop interrupt is enabled. 255 / 0x1c [31] start channel start. if this flag is set the channel is requesting service. the edma hardware automatically clears this flag after the channel begins execution. 0 the channel is not explicitly started. 1 the channel is explicitly started via a software initiated service request. 1 the fields implemented at 0x8 depend on whethe r edma_cr(emlm) is set to 0 or 1. refer to ta b l e 1 6 - 2 . table 16-19. tcd n field descriptions (continued) bits / word offset [n:n] name description
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 279 the edma module is partitioned into two major mo dules: the dma engine and the transfer control descriptor local memory. the dma e ngine is further partitioned into four submodules, which are detailed below. ? dma engine ? address path: this module implements registered versions of two cha nnel transfer control descriptors: channel x and channel y, and is responsible for all the master bus address calculations. all the implemente d channels provide the same functionality. this hardware structure allows the data transfers associated with one channel to be preempted after the completion of a read/write sequence if a higher priority channel service request is asserted while the first channel is active. after a channel is activated, it runs until the minor loop is completed unless preempted by a higher prio rity channel. this capability provides a mechanism (optionally enabled by edma_cpr n [ecp]) where a large data move operation can be preempted to minimize the time a nother channel is bloc ked from execution. when another channel is activated, the contents of its transfer control de scriptor is read from the local memory and loaded into the register s of the other address path channel{x,y}. after the inner minor loop completes ex ecution, the address path hardware writes the new values for the tcd n .{saddr, daddr, citer} back into the lo cal memory. if the major iteration count is exhausted, additional processing is performed, includi ng the final address pointer updates, reloading the tcdn .citer field, and a possibl e fetch of the next tcd n from memory as part of a scatter-gather operation. ? data path: this module implements the actual bu s master read/write da tapath. it includes 32 bytes of register storage (match ing the maximum transfer size) and the necessary mux logic to support any required data alignment. the system read data bus is the primary input, and the system write data bus is the primary output. the address and data path modul es directly support the two-st age pipelined system bus. the address path module represents th e 1st stage of the bus pipeline (the address phase), while the data path module implements the second st age of the pipeline (the data phase). ? program model/channel ar bitration: this module implements the first section of edma?s programming model and also the channel arbitr ation logic. the programming model registers are connected to the slave bus (not shown). the edma peripheral re quest inputs and edma interrupt request outputs are also connected to this module (via the control logic). ? control: this module provides all the control f unctions for the dma engi ne. for data transfers where the source and destination sizes are equal, the dma engine performs a series of source read, destination write operations until the number of bytes speci fied in the inner minor loop byte count has been moved. a minor loop interaction is defined as the number of bytes to transfer ( n bytes) divided by the transfer size. transfer size is defined as: if (ssize < dsize) transfer size = destination transfer size (# of bytes) else transfer size = source transfer size (# of bytes)
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 280 freescale semiconductor minor loop tcd variables are soff, smod , doff, dmod, nbytes, saddr, daddr, bwc, active, and start. major loop tcd va riables are dlast, slast, citer, biter, done, d_req, int_maj, ma jor_lnkch, and int_half. for descriptors where the sizes are not equal, multiple access of the smaller size data are required for each reference of the larger size. fo r example, if the source size references 16-bit data and the destination is 32-bit data, tw o reads are performed, then one 32-bit write. ? tcd local memory ? memory controller: this logi c implements the required dual-ported controller, handling accesses from both the dma engine as well as re ferences from the slave bus. as noted earlier, in the event of simultaneous accesses, the dma engine is given priority and the slave transaction is stalled. the hooks to a bist cont roller for the local tcd memory are included in this module. ? memory array: the tcd is implemented us ing a single-ported, sy nchronous compiled ram memory array. 16.4.1 edma basic data flow the edma transfers data based on a two-deep, nested flow. the basic fl ow of a data transfer can be partitioned into three segments. as shown in figure 16-19 , the first segment involves the channel service request. in the diagram, this example uses the assert ion of the edma peripheral request signal to request service for channel n . channel service request vi a software and the tcdn.start bit follows the same basic flow as an edma peripheral request. the edma peripheral request input signal is registered internally and then routed to through the dma engi ne, first through the control module, then into the program model/channel arbitr ation module. in the next cycle, the channel arbitration is performed using the fixed-priority or round-robin algo rithm. after the arbitrat ion is complete, the activated channel number is sent through the address path a nd converted into the required addres s to access the tcd local memory. next, the tcd memory is accessed and the required de scriptor read from the local memory and loaded into the dma engine address path channel{x,y} register s. the tcd memory is organized 64 bits in width to minimize the time needed to fe tch the activated channel? s descriptor and load it into the edma engine address path channel{x,y} registers.
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 281 figure 16-19. edma operation, part 1 in the second part of the basic data flow as shown in figure 16-20 , the modules associated with the data transfer (address path, da ta path, and control) sequence through th e required source reads and destination writes to perform the actual data movement. the source reads are in itiated and the fetched data is temporarily stored in the da ta path module until it is gated onto the system bus during the destination write. this source read/destination write processing cont inues until the inner mi nor byte count has been transferred. the edma done handshake signal is asserted at the end of the minor byte count transfer. slave interface edma edma peripheral request system bus data path control address program model/ slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n ?1 edma interrupt request bus read data channel arbitration edma done handshake path sram transfer control descriptor ( tcd ) sram n = 16 channels
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 282 freescale semiconductor figure 16-20. edma operation, part 2 after the inner minor byte count has been moved, the fi nal phase of the basic data flow is performed. in this segment, the address path logic performs the requ ired updates to certain fiel ds in the channel?s tcd; for example, saddr, daddr, citer. if the outer major iteration count is exhausted, then there are additional operations performed. thes e include the final address adjust ments and reloading of the biter field into the citer. additiona lly, assertion of an optional interrupt request occurs at th is time, as does a possible fetch of a new tcd from memory using the scatter-gather address pointer included in the descriptor. the updates to the tcd memory and the assertion of an interrupt request are shown in figure 16-21 . slave interface edma edma interrupt request system bus program model/ slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n ?1 edma peripheral bus read data channel arbitration request sram transfer control descriptor (tcd) sram data path control address path edma done handshake n = 16 channels
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 283 figure 16-21. edma operation, part 3 16.5 initialization / application information 16.5.1 edma initialization a typical initialization of the edma has the following sequence: 1. write the edma_cr if a configurati on other than the default is desired. 2. write the channel priority levels into the edma_cpr n registers if a configuration other than the default is desired. 3. enable error interrupts in the edma_eeirl and/or edma_eeirh registers if desired. 4. write the 32-byte tcd for each ch annel that may request service. 5. enable any hardware service requests via the edma_erqrh and/or edma_erqrl registers. 6. request channel service by softwa re (setting the tcd.start bit) or by hardware (slave device asserting its dma peri pheral request signal). after any channel requests service, a channel is select ed for execution based on th e arbitration and priority levels written into the programmer's model. the dm a engine will read the entire tcd, including the slave interface edma edma done system bus slave write data slave write address bus write data slave read data bus address edma engine tcd0 tcd n ?1 edma peripheral bus read data request sram transfer control descriptor (tcd) sram data path address path control program model/ channel arbitration n = 16 channels
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 284 freescale semiconductor primary transfer contro l parameter shown in table 16-20 , for the selected channel into its internal address path module. as the tcd is being read, the first transfer is initiated on the system bus unless a configuration error is detected. tr ansfers from the source (as defined by the source address, tcd.saddr) to the destination (as defined by the destination address, tcd.daddr) conti nue until the specified number of bytes (tcd.n bytes) have been transfer red. when the transfer is complete, the dma engine's local tcd.saddr, tcd.daddr, and tc d.citer are written back to the main tcd memory and any minor loop channel linking is performed, if enabled. if the major l oop is exhausted, further post processing is executed; for example, interrupt s, major loop channel linking, and scatter-gather operations, if enabled. figure 16-22 shows how each dma request initiates one minor loop transf er (iteration) without cpu intervention. dma arbitration can occur after e ach minor loop, and one level of minor loop dma preemption is allowed. the number of minor loops in a major loop is specified by the beginning iteration count (biter). table 16-20. tcd primary control and status fields tcd field name description start control bit to start channel when using a software initiated dma service (automatically cleared by hardware) active status bit indicating the c hannel is currently in execution done status bit indicating major loop completion (cleared by software when using a software initiated dma service) d_req control bit to disable dma request at end of major loop completion when using a hardware-initiated dma service bwc control bits for throttling bandwidth control of a channel e_sg control bit to enable scatter-gather feature int_half control bit to enable interrupt when major loop is half complete int_maj control bit to enable interrupt when major loop completes
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 285 figure 16-22. example of multiple loop iterations figure 16-23 lists the memory array terms and how the tcd settings interrelate. figure 16-23. memory array terms 16.5.2 dma programming errors the dma performs various tests on the transfer control descriptor to veri fy consistency in the descriptor data. most programming errors are re ported on a per-channel basis with th e exception of channel-priority error, or edma_esr[cpe]. for all error types other than channe l-priority errors, the channel numbe r causing the error is recorded in the edma_esr. if the error source is not removed before the next acti vation of the problem channel, the error will be detected and recorded again. dma request minor loop 3 current major loop iteration count (citer) example memory array ? ? ? dma request minor loop 2 ? ? ? dma request minor loop 1 ? ? ? major loop xaddr: (starting address) xsize: (size of one data minor loop (nbytes in minor loop, often the same value as xsize) offset (xoff): number of bytes added to current address after each transfer (often the same value as xsize) ? minor loop each dma source (s) and destination (d) has its own: ? address (xaddr) ? size (xsize) ? offset (xoff) xlast: number of bytes added to current address peripheral queues typically have size and offset equal to nbytes ? ? after major loop (typically used to loop back) transfer) ? ? ? ? ? ? last minor loop ? modulo (xmod) ? last address adjustment (xlast) where x = s or d ? ? ?
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 286 freescale semiconductor if priority levels are not unique, the highest (channel) priority that has an active request is selected, but the lowest numbered (channel) with that priority is selected by arbitr ation and executed by the dma engine. the hardware service request handshake signals, error interrupts, and error repor ting are associated with the selected channel. 16.5.3 dma request assignments the assignments between the dma requ ests from the modules to the cha nnels of the edma are shown in table 16-21 . the source column is written in c language syntax. the syntax is module_instance.register[bit]. 16.5.4 dma arbitration mode considerations 16.5.4.1 fixed-channel arbitration in this mode, the channel service request from the highest priority channel is selected to execute. preemption is available in this scenario only. 16.5.4.2 round-robin ch annel arbitration in this mode, channels are servi ced starting with the highest channe l number and rotating through to the lowest channel number without regard to the assigned channel priority levels. table 16-21. dma request summary for edma dma request channel source description dma_mux_chconfig0_source 0 dma_mux.chconfig0[source] dma mux channel 0 source dma_mux_chconfig1_source 1 dma_mux.chconfig1[source] dma mux channel 1 source dma_mux_chconfig2_source 2 dma_mux.chconfig2[source] dma mux channel 2 source dma_mux_chconfig3_source 3 dma_mux.chconfig3[source] dma mux channel 3 source dma_mux_chconfig4_source 4 dma_mux.chconfig4[source] dma mux channel 4 source dma_mux_chconfig5_source 5 dma_mux.chconfig5[source] dma mux channel 5 source dma_mux_chconfig6_source 6 dma_mux.chconfig6[source] dma mux channel 6 source dma_mux_chconfig7_source 7 dma_mux.chconfig7[source] dma mux channel 7 source dma_mux_chconfig8_source 8 dma_mux.chconfig8[source] dma mux channel 8 source dma_mux_chconfig9_source 9 dma_mux.chconfig9[source] dma mux channel 9 source dma_mux_chconfig10_source 10 dma_mux.chconfig 10[source] dma mux channel 10 source dma_mux_chconfig11_source 11 dma_mux.chconfig 11[source] dma mux channel 11 source dma_mux_chconfig12_source 12 dma_mux.chconfig 12[source] dma mux channel 12 source dma_mux_chconfig13_source 13 dma_mux.chconfig 13[source] dma mux channel 13 source dma_mux_chconfig14_source 14 dma_mux.chconfig 14[source] dma mux channel 14 source dma_mux_chconfig15_source 15 dma_mux.chconfig 15[source] dma mux channel 15 source
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 287 16.5.5 dma transfer 16.5.5.1 single request to perform a simple transfer of n bytes of data with one activation, set the major loop to 1 (tcd.citer = tcd.biter = 1). the data transfer w ill begin after the channel service request is acknowledged and the channel is selected to execute. after the transfer is co mplete, the tcd.done bit will be set and an interrupt will be generated if properly enabled. for example, the following tcd entry is configured to transfer 16 bytes of data. the edma is programmed for one iterati on of the major loop transferring 16 byt es per iteration. the source memory has a byte-wide memory port located at 0x1000. the destin ation memory has a word wide port located at 0x2000. the address offsets are programmed in increments to match the size of th e transfer; 1 byte for the source and 4 bytes for the destination. the final source and destination addr esses are adjusted to return to their beginning values. tcd.citer = tcd.biter = 1 tcd.nbytes = 16 tcd.saddr = 0x1000 tcd.soff = 1 tcd.ssize = 0 tcd.slast = ?16 tcd.daddr = 0x2000 tcd.doff = 4 tcd.dsize = 2 tcd.dlast_sga= ?16 tcd.int_maj = 1 tcd.start = 1 (must be written last after all other fields have been initialized) all other tcd fields = 0 this would generate the fo llowing sequence of events: 1. slave write to the tcd.star t bit requests channel service. 2. the channel is selected by arbitration for servicing. 3. edma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1. 4. edma engine reads: channel tcd data from local memory to internal register file. 5. the source to destination transfers are executed as follows: a) read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b) write_word(0x2000) ? first iteration of the minor loop c) read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d) write_word(0x2004) ? second iteration of the minor loop e) read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f) write_word(0x2008) ? third iteration of the minor loop
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 288 freescale semiconductor g) read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h) write_word(0x200c) ? last iteration of the minor loop ? major loop complete 6. edma engine writes: tcd.saddr = 0x1000, tcd.daddr = 0x2000, tcd.citer = 1 (tcd.biter). 7. edma engine writes: tcd.acti ve = 0, tcd.done = 1, edma_irqr n = 1. 8. the channel retires. the edma goes idle or se rvices the next channel. 16.5.5.2 multiple requests the next example is the same as previous, excepting transferring 32 bytes via tw o hardware requests. the only fields that change are the ma jor loop iteration count and the fina l address offsets. the edma is programmed for two iterations of the major loop tran sferring 16 bytes per itera tion. after the channel?s hardware requests are enabled in the edma_erqr, channel service requests ar e initiated by the slave device (erqr should be set after tcd). note that tcd.start = 0. tcd.citer = tcd.biter = 2 tcd.nbytes = 16 tcd.saddr = 0x1000 tcd.soff = 1 tcd.ssize = 0 tcd.slast = ?32 tcd.daddr = 0x2000 tcd.doff = 4 tcd.dsize = 2 tcd.dlast_sga= ?32 tcd.int_maj = 1 tcd.start = 0 (must be written last after all other fields have been initialized) all other tcd fields = 0 this generates the following sequence of events: 1. first hardware (edma peripheral re quest) request for channel service. 2. the channel is selected by arbitration for servicing. 3. edma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1. 4. edma engine reads: channel tcd data from local memory to internal register file. 5. the source to destination transfers are executed as follows: a) read_byte(0x1000), rea d_byte(0x1001), read_byte( 0x1002), read_byte(0x1003) b) write_word(0x2000) ? first iteration of the minor loop c) read_byte(0x1004), rea d_byte(0x1005), read_byte( 0x1006), read_byte(0x1007) d) write_word(0x2004) ? second iteration of the minor loop
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 289 e) read_byte(0x1008), rea d_byte(0x1009), read_byte(0 x100a), read_byte(0x100b) f) write_word(0x2008) ? third iteration of the minor loop g) read_byte(0x100c), r ead_byte(0x100d), read_byte (0x100e), read_byte(0x100f) h) write_word(0x200c) ? last iteration of the minor loop 6. edma engine writes: tcd.saddr = 0x1010, tcd.daddr = 0x2010, tcd.citer = 1. 7. edma engine writes: tcd.active = 0. 8. the channel retires ? one iteration of the major loop. the edma goes idle or se rvices the next channel. 9. second hardware (edma peripheral request) requests channel service. 10. the channel is selected by arbitration for servicing. 11. edma engine writes: tcd.done = 0, tcd.start = 0, tcd.active = 1. 12. edma engine reads: channel tcd data from local memory to internal register file. 13. the source to destination transfers are executed as follows: a) read_byte(0x1010), r ead_byte(0x1011), rea d_byte(0x1012), read_byte(0x1013) b) write_word(0x2010) ? first iteration of the minor loop c) read_byte(0x1014), rea d_byte(0x1015), read_byte( 0x1016), read_byte(0x1017) d) write_word(0x2014) ? second iteration of the minor loop e) read_byte(0x1018), rea d_byte(0x1019), read_byte(0 x101a), read_byte(0x101b) f) write_word(0x2018) ? third iteration of the minor loop g) read_byte(0x101c), r ead_byte(0x101d), read_byte (0x101e), read_byte(0x101f) h) write_word(0x201c) ? last iteration of the minor loop ? major loop complete 14. edma engine writes: tcd.saddr = 0x1000, tcd.daddr = 0x2000, tcd.citer = 2 (tcd.biter). 15. edma engine writes: tcd.acti ve = 0, tcd.done = 1, edma_irqr n = 1. 16. the channel retires ? major loop complete. the edma goes idle or se rvices the next channel. 16.5.5.3 modulo feature the modulo feature of the ed ma provides the ability to implement a ci rcular data queue in which the size of the queue is a power of two. mod is a 5-bit fiel d for both the source and de stination in the tcd and specifies which lower address bits are allowed to increment from their original value after the address + offset calculation. all upper addr ess bits remain the same as in the original value. a setting of 0 for this field disables the modulo feature. table 16-22 shows how the transfer addresses are specified based on the setting of the mod field. here a circular buffer is cr eated where the address wraps to the origin al value while the 28 upper address bits (0x1234567x) retain their original value. in this example the source address is set to 0x12345670, the offset is set to 4 bytes and the mod field is set to 4, allowing for a 2 4 byte (16-byte) size queue.
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 290 freescale semiconductor 16.5.6 tcd status 16.5.6.1 minor loop complete there are two methods to test for minor loop completion when using soft ware initiated service requests. the first method is to read the tc d.citer field and test for a change . another method may be extracted from the sequence below. the second method is to test the tcd.start bit an d the tcd.active bit. the minor loop complete condition is indicated by both bits reading zero after the tcd.start was written to a 1. polling the tcd.active bit may be inc onclusive because the acti ve status may be missed if the channel execution is short in duration. the tcd status bits execute the following sequence for a software activated channel: 1. tcd.start = 1, tcd.active = 0, tcd.done = 0 (channel service request via software). 2. tcd.start = 0, tcd.active = 1, tc d.done = 0 (channel is executing). 3. tcd.start = 0, tcd.active = 0, tcd.done = 0 (channel has completed the minor loop and is idle), or 4. tcd.start = 0, tcd.active = 0, tcd.done = 1 (channel has complete d the major loop and is idle). the best method to test for minor loop completion wh en using hardware initiate d service requests is to read the tcd.citer field and test for a change. the hardware request and acknowledge handshakes signals are not visible in the programmer?s model. the tcd status bits execute the following sequence for a hardware activated channel: 1. edma peripheral request asserts (c hannel service request via hardware). 2. tcd.start = 0, tcd.active = 1, tc d.done = 0 (channel is executing). 3. tcd.start = 0, tcd.active = 0, tcd.done = 0 (channel has completed the minor loop and is idle), or 4. tcd.start = 0, tcd.active = 0, tcd.done = 1 (channel has complete d the major loop and is idle). for both activation types, the major loop complete stat us is explicitly indicated via the tcd.done bit. table 16-22. modulo feature example transfer number address 1 0x12345670 2 0x12345674 3 0x12345678 4 0x1234567c 5 0x12345670 6 0x12345674
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 291 the tcd.start bit is cleared automatically when th e channel begins execution, regardless of how the channel was activated. 16.5.6.2 active channel tcd reads the edma will read back the tr ue tcd.saddr, tcd.daddr, and tc d.nbytes values if read while a channel is executing. the true values of the sadd r, daddr, and nbytes are the values the edma engine is currently using in its inte rnal register file and not the values in the tcd local memory for that channel. the addresses (saddr a nd daddr) and nbytes (decrements to 0 as the transfer progresses) can give an indication of the progress of the transfer . all other values are read back from the tcd local memory. 16.5.6.3 preemption status preemption is available only when fixed arbitration is selected for channel-arbitration mode. a preemptable situation is one in which a preempt-enab led channel is running and a higher priority request becomes active. when the edma engine is not operating in fixe d-channel arbitration mode, the determination of the relative priority of the actively running and the out standing requests become undefined. channel priorities are treated as equal (or mo re exactly, constantly ro tating) when round-robin arbitration mode is selected. the tcd.active bit for the preempted channel remains asserted throughout the preemption. the preempted channel is temporarily suspended while the preempting cha nnel executes one iteration of the major loop. two tcd.active bits set at the same time in the overall tcd map indicates a higher priority channel is actively preempti ng a lower priority channel. 16.5.7 channel linking channel linking (or chaining) is a mechanism in whic h one channel sets the tc d.start bit of another channel (or itself), thus initiating a service request for that channel. this operation is automatically performed by the edma engine at the conclusion of the major or minor loop when properly enabled. the minor loop channel linking occurs at the completio n of the minor loop (or one iteration of the major loop). the tcd.citer.e_link field are used to dete rmine whether a minor loop link is requested. when enabled, the channel link is made af ter each iteration of the minor loop except for the last. when the major loop is exhausted, only the major loop channel link fields are used to determine if a channel link should be made. for example, with the initial fields of: tcd.citer.e_link = 1 tcd.citer.linkch = 0xc tcd.citer value = 0x4 tcd.major.e_link = 1 tcd.major.linkch = 0x7 will execute as: 1. minor loop done ? set channel 12 tcd.start bit 2. minor loop done ? set channel 12 tcd.start bit
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 292 freescale semiconductor 3. minor loop done ? set channel 12 tcd.start bit 4. minor loop done, major loop done ? set channel 7 tcd.start bit when minor loop linking is enabled (tcd.citer.e_l ink = 1), the tcd.citer field uses a nine bit vector to form the cu rrent iteration count. when minor loop linking is disabled (tcd.citer.e _link = 0), the tcd.citer field uses a 15-bit vector to form the current iterat ion count. the bits associated wi th the tcd.citer.linkch field are concatenated onto the citer value to increase the range of the citer. note after configuration, the tc d.citer.e_link bit and the tcd.biter.e_link bit must be equal or a configuration error will be reported. the citer and biter vector wi dths must be equal to calculate the major loop, halfway done interrupt point. table 16-23 summarizes how a dma channel can link to another dma channel, i.e, use another channel?s tcd, at the end of a loop. 16.5.8 dynamic programming 16.5.8.1 dynamic channel linking dynamic channel linking is the proce ss of setting the tcd.major.e_link bit during channel execution. this bit is read from the tcd local memory at the end of channel execution, thus allowing the user to enable the feature during channel execution. because the user is allowed to change the configur ation during execution, a c oherency model is needed. consider the scenario where the user attempts to execute a dynamic channel link by enabling the tcd.major.e_link bit at the same time the edma engi ne is retiring the channel. the tcd.major.e_link would be set in the programmer?s m odel, but it would be unclear whet her the actual link was made before the channel retired. the coherency model in table 16-24 is recommended when executi ng a dynamic channel link request. table 16-23. channel linking parameters desired link behavior tcd control field name description link at end of minor loop citer.e_link enable channel-to-channel linking on minor loop completion (current iteration). citer.linkch link channel number when linking at end of minor loop (current iteration). link at end of major loop major.e_link enable channel-to-channel linking on major loop completion. major.linkch link channel number when linking at end of major loop.
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 293 for this request, the tcd local memory controller forces the tcd.major.e_link bit to zero on any writes to a channel?s tcd.word7 after that channel?s tcd.done bit is set, indicating the major loop is complete. note the user must clear the tcd.done bi t before writing th e tcd.major.e_link bit. the tcd.done bit is cleared auto matically by the edma engine after a channel begins execution. 16.5.8.2 dynamic scatter/gather dynamic scatter/gather is the proces s of setting the tcd.e_sg bit during channel execution. this bit is read from the tcd local memory at the e nd of channel execution, thus allowing the user to enable the feature during channel execution. because the user is allowed to change the configur ation during execution, a c oherency model is needed. consider the scenario where the user attempts to execute a dynamic scatter/gather operation by enabling the tcd.e_sg bit at the same time the edma engine is retiring the channel. the tcd.e_sg would be set in the programmer?s model, but it would be unclear whether the actual scatter/gather request was honored before the channel retired. two methods for this coherency model are shown in the following subsections. method 1 has the advantage of reading the major.linkch field and the e_sg bit with a single r ead. for both dynamic channel linking and scatter/gather requests, the tcd local me mory controller forces the tcd.major.e_link and tcd.e_sg bits to zero on any writes to a channel? s tcd.word7 if that channel?s tcd.done bit is set indicating the major loop is complete. note the user must clear the tcd.done bi t before writing th e tcd.major.e_link or tcd.e_sg bits. the tcd.done bit is cleared automati cally by the edma engine after a channel begins execution. 16.5.8.2.1 method 1 (ch annel not using major loop channel linking) for a channel not using major loop cha nnel linking, the c oherency model in table 16-25 may be used for a dynamic scatter/ gather request. table 16-24. coherency model for a dynamic channel link request step action 1 write 1b to the tcd.major.e_link bit. 2 read back the tcd.major.e_link bit. 3 test the tcd.major.e_link request status: ? if tcd.major.e_link = 1b, the dy namic link attempt was successful. ? if tcd.major.e_link = 0b, the attempted dynamic link did not succeed (the channel was already retiring).
chapter 16 enhanced direct memory access (edma) MPC5606BK microcontroller reference manual, rev. 2 294 freescale semiconductor when the tcd.major.e_link bit is zero, the tcd.major. linkch field is not used by the edma. in this case, the tcd.major.linkch bits may be us ed for other purposes. this method uses the tcd.major.linkch field as a tcd identification (id). 16.5.8.2.2 method 2 (channel using major loop linking) for a channel using major loop channel linking, the coherency model in table 16-26 may be used for a dynamic scatter/gather reque st. this method uses the tcd.dlast_sg a field as a tcd identification (id). table 16-25. coherency model for method 1 step action 1 when the descriptors are built, write a unique tcd id in the tcd.major.linkch field for each tcd associated with a channel using dynamic scatter/gather. 2 write 1b to thetcd.d_req bit. note: should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future hardware activation of this channel. this stops the channel from executing with a destination address (daddr) that was ca lculated using a scatter/gather address (written in the next step) instead of a dlast final offset value. 3 write thetcd.dlast_sga field with the scatter/ gather address. 4 write 1b to the tcd.e_sg bit. 5 read back the 16 bit tcd control/status field. 6 test the tcd.e_sg request status and tcd.major.linkch value: ? if e_sg = 1b, the dynamic link attempt was successful. ? if e_sg = 0b and the major.linkch (id) did not change, the attempted dynamic link did not succeed (the channel was already retiring). ? if e_sg = 0b and the major.linkch (id) changed, the dynamic link attempt was successful (the new tcd?s e_sg value cleared the e_sg bit). table 16-26. coherency model for method 2 step action 1 write 1b to thetcd.d_req bit. note: should a dynamic scatter/gather attempt fail, setting the d_req bit will prevent a future hardware activation of this channel. this stops the channel from executing with a destination address (daddr) that was ca lculated using a scatter/gather address (written in the next step) instead of a dlast final offset value. 2 write thetcd.dlast_sga field with the scatter/ gather address. 3 write 1b to the tcd.e_sg bit. 4 read back the tcd.e_sg bit. 5 test the tcd.e_sg request status: ? if e_sg = 1b, the dynamic link attempt was successful. ? if e_sg = 0b, read the 32 bit tcd dlast_sga field. ? if e_sg = 0b and the dlast_sga did not change, the attempted dynamic link did not succeed (the channel was already retiring). ? if e_sg = 0b and the dlast_sga changed, th e dynamic link attempt was successful (the new tcd?s e_sg value cleared the e_sg bit).
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 295 chapter 17 edma channel multiplexer (dma_mux) 17.1 introduction the edma channel multiplexer (dma_mux) allows th e routing of 59 dma sour ces (slots) to 16 edma channels. this is illustrated in figure 17-1 . figure 17-1. dma_mux block diagram 17.2 features the dma_mux has these major features: ? 16 independently selectab le edma channel routers ? four channels with normal or periodic triggering capability ? 12 channels with normal capability ? capability to assign each channel ro uter to one of 59 possible periph eral dma sources, four always enabled sources, or one always disabled source ? three modes of operation: source #1 source #2 source #3 source #59 edma channel #1 edma channel #15 edma channel #0 dma_mux trigger #1 trigger #4 always enabled always enabled
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 296 freescale semiconductor ? disabled ? normal ? periodic trigger 17.3 modes of operation the following operation modes are available: ? disabled mode ? in this mode, the edma channe l is disabled. since di sabling and enabling of edma channels is done pr imarily via the edma configuration regi sters, this mode is used mainly as the reset state for an edma channel in the dma_mux. it may also be used to temporarily suspend an edma channel while re configuration of the sy stem takes place (for example, changing the period of an edma trigger). ? normal mode ? in this mode, an edma s ource (such as dspi_0_tx or dspi_0_rx example) is routed directly to the spec ified edma channel. the operation of the dma_mux in this mode is completely transparent to the system. ? periodic trigger mode ? in this mode, an ed ma source may only reques t an edma transfer (such as when a transmit buffer becomes empty or a receive buffe r becomes full) periodically. the period is configured in the registers of the periodic interrupt timer (pit). edma channels 0?3 may be used in all three modes, but channels 4?15 may only be configured to disabled or normal mode. 17.4 external signal description the dma_mux has no external pins. 17.5 memory map and register definition table 17-1 shows the memory map for the dma_mux. note that all addresses are offsets; the absolute address may be computed by a dding the specified offset to th e base address of the dma_mux. all registers are accessible via 8-, 16-, or 32-bit accesses. however, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses mu st be aligned to 32-bit boundari es. as an example, chconfig0 through chconfig3 are accessible by a 32-bit read/w rite to address base + 0x00, but performing a 32-bit access to address base + 0x01 is illegal. table 17-1. dma_mux memory map base address: 0xfffd_c000 address offset register location 0x0 channel #0 confi guration (chconfig0) on page 297 0x1 channel #1 confi guration (chconfig1) on page 297 ... ... ... 0xf channel #15 configuration (chconfig15) on page 297
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 297 17.5.1 channel configurat ion registers (chconfig n ) each of the total of 16 edma channe ls can be independently enabled/di sabled and associated with 1 of the 28 peripheral edma sources + 1 of the four always enabled edma sources in the system. note setting multiple chconfig registers with the same source value results in unpredictable behavior. note before changing the trigger or source settings an edma channel must be disabled via the chconfig n [enbl] bit. offset: 0x0 + n (16 registers) access: user read/write 01234567 r enbl trig source w reset00000000 figure 17-2. channel configuration registers (chconfig n ) table 17-2. chconfig n field descriptions field description enbl edma channel enable enbl enables the edma channel. 0 edma channel is disabled. this mode is primarily used during configuration of the dma_mux. the edma has separate channel enables/disables, which should be used to disable or reconfigure an edma channel. 1 edma channel is enabled trig edma channel trigger enable (for triggered channels only) trig enables the periodic trigger capability for the edma channel. 0 periodic triggering is disabled. if periodic triggering is disabled, and the enbl bit is set, the dma_mux will simply route the specified source to the edma channel. 1 triggering is enabled source edma channel source (slot) source specifies which edma source, if any, is routed to a particular edma channel. please see table 17-4 for dma_mux inputs mapping. table 17-3. channel and trigger enabling enbl trig function mode 0 x edma channel is disabled disabled mode 1 0 edma channel is enabled with no triggering (transparent) normal mode 1 1 edma channel is enabled with triggering periodic trigger mode
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 298 freescale semiconductor 17.6 dma_mux inputs 17.6.1 dma_mux peripheral sources table 17-4. edma channel mapping dma_mux channel module edma requ esting module dma_mux input # 0 ? always disabled ? 1 dspi 0 dspi_0 tx dma_mux source #1 2 dspi 0 dspi_0 rx dma_mux source #2 3 dspi 1 dspi_1 tx dma_mux source #3 4 dspi 1 dspi_1 rx dma_mux source #4 5 dspi 2 dspi_2 tx dma_mux source #5 6 dspi 2 dspi_2 rx dma_mux source #6 7 dspi 3 dspi_3 tx dma_mux source #7 8 dspi 3 dspi_3 rx dma_mux source #8 9 dspi 4 dspi_4 tx dma_mux source #9 10 dspi 4 dspi_4 rx dma_mux source #10 11 dspi 5 dspi_5 tx dma_mux source #11 12 dspi 5 dspi_5 rx dma_mux source #12 13 ? ? dma_mux source #13 14 ? ? dma_mux source #14 15 ? ? dma_mux source #15 16 ? ? dma_mux source #16 17 emios 0 emios0_ch0 dma_mux source #17 18 emios 0 emios0_ch1 dma_mux source #18 19 emios 0 emios0_ch9 dma_mux source #19 20 emios 0 emios0_ch18 dma_mux source #20 21 emios 0 emios0_ch25 dma_mux source #21 22 emios 0 emios0_ch26 dma_mux source #22 23 emios 1 emios1_ch0 dma_mux source #23 24 emios 1 emios1_ch9 dma_mux source #24 25 emios 1 emios1_ch17 dma_mux source #25 26 emios 1 emios1_ch18 dma_mux source #26 27 emios 1 emios1_ch25 dma_mux source #27 28 emios 1 emios1_ch26 dma_mux source #28
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 299 29 adc 0 adc0_eoc dma_mux source #29 30 adc 1 adc1_eoc dma_mux source #30 31 i 2 c iic_rx dma_mux source #31 32 i 2 c iic_tx dma_mux source #32 33 linflex 0 linflex0_rx dma_mux source #33 34 linflex 0 linflex0_tx dma_mux source #34 35 linflex 1 linflex1_rx dma_mux source #35 36 linflex 1 linflex1_tx dma_mux source #36 37 ? ? dma_mux source #37 38 ? ? dma_mux source #38 39 ? ? dma_mux source #39 40 ? ? dma_mux source #40 41 ? ? dma_mux source #41 42 ? ? dma_mux source #42 43 ? ? dma_mux source #43 44 ? ? dma_mux source #44 45 ? ? dma_mux source #45 46 ? ? dma_mux source #46 47 ? ? dma_mux source #47 48 ? ? dma_mux source #48 49 ? ? dma_mux source #49 50 ? ? dma_mux source #50 51 ? ? dma_mux source #51 52 ? ? dma_mux source #52 53 ? ? dma_mux source #53 54 ? ? dma_mux source #54 55 ? ? dma_mux source #55 56 ? ? dma_mux source #56 57 ? ? dma_mux source #57 58 ? ? dma_mux source #58 table 17-4. edma channel mapping (continued) dma_mux channel module edma requ esting module dma_mux input #
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 300 freescale semiconductor 17.6.2 dma_mux periodic trigger inputs 17.7 functional description the primary purpose of the dma_mux is to provide flex ibility in the system?s use of the available edma channels. as such, configuration of the dma_mux is intended to be a static procedure done during execution of the system boot code. howe ver, if the procedure outlined in section 17.8.2, enabling and configuring sources , is followed, the configuration of the dma_mux may be changed during the normal operation of the system. functionally, the dma_mux channels may be divided into two classes: channels that implement the normal routing functionality plus periodic triggering capability, and channels, that implement only the normal routing functionality. 17.7.1 edma channels with pe riodic triggering capability besides the normal routing functionality, the first four channels of the dma_mux provide a special periodic triggering capability that can be used to provide an automatic mech anism to transmit bytes, frames or packets at fixed intervals without the need for processor intervention. the trigger is generated by the periodic interrupt timer (pit); as such, the configuration of the periodic triggering interval is done via configuration registers in the pit. please see section 27.5, periodic interrupt timer (pit) , for more information on this topic. 59 ? ? dma_mux source #59 60 ? always enabled dma_mux source #60 61 ? always enabled dma_mux source #61 62 ? always enabled dma_mux source #62 63 ? always enabled dma_mux source #63 table 17-5. dma_mux periodic trigger inputs dma_mux trigger input pit channel trigger #1 pit0 trigger #2 pit1 trigger #3 pit4 trigger #4 pit5 table 17-4. edma channel mapping (continued) dma_mux channel module edma requ esting module dma_mux input #
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 301 note because of the dynamic nature of the system (such as edma channel priorities, bus arbi tration, or interrupt service routine le ngths), the number of clock cycles between a trigger a nd the actual edma transfer cannot be guaranteed. figure 17-3. dma_mux channel 0?3 block diagram the edma channel triggering capabilit y allows the system to schedule regular edma transfers, usually on the transmit side of certain periphe rals, without the intervention of th e processor. this trigger works by gating the request from the pe ripheral to the edma until a trigger event has been seen. this is illustrated in figure 17-4 . figure 17-4. dma_mux channel triggering: normal operation dma channel #0 trigger #4 trigger #2 trigger #1 source #1 source #2 source #3 source #28 always enabled always enabled dma channel #3 periph request trigger dma request
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 302 freescale semiconductor once the edma request has been serviced, the peripheral will negate its request, effectively resetting the gating mechanism until the peri pheral reasserts its request and the next trigger event is seen. this means that if a trigger is seen, but the peripheral is not reque sting a transfer, that trigge red will be ignored. this situation is illustrated in figure 17-5 . figure 17-5. dma_mux channel triggering: ignored trigger this triggering capability may be used with any pe ripheral that supports edma transfers, and is most useful for periodically polling exte rnal devices on a particular bus. as an example, the transmit side of a dspi is assi gned to an edma channel with a trigger, as described above. once set up, the spi will request edma transfers (presumably from memory) as long as its transmit buffer is empty. by using a trigger on this channel, the dspi transf ers can be automatically performed every 5 ? s (as an example). on the receive side of the spi, the spi and edma can be configured to transfer receive data into memory, effectively implementing a method to periodically read data from external devices and transfer the results into memory without processor intervention. a more detailed description of the capability of each trigger (such as resolution, or range of values) may be found in chapter 27, timers . 17.7.2 edma channels with no triggering capability channels 4?15 of the dma_mux provide the norm al routing functionali ty as described in section 17.3, modes of operation . periph request trigger dma request
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 303 figure 17-6. dma_mux channel 4?15 block diagram 17.8 initialization/application information 17.8.1 reset the reset state of each i ndividual bit is shown in section 17.5, memory map a nd register definition . in summary, after reset, all channe ls are disabled and must be explicitly enabled before use. 17.8.2 enabling and configuring sources 17.8.2.1 enabling a source with periodic triggering the following describes how to enable a source with periodic triggering: 1. determine with which edma cha nnel the source will be associat ed. remember that only the first four edma channels have pe riodic triggering capability. 2. clear the enbl and trig bits of the edma channel. 3. ensure that the edma channel is properly c onfigured in the edma. the edma channel may be enabled at this point. source #1 source #2 source #3 source #28 dma channel #4 dma channel #15 always enabled always enabled
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 304 freescale semiconductor 4. in the pit, configur e the corresponding timer. 5. select the source to be routed to the ed ma channel. write to the corresponding chconfig register, ensuring that the enbl and trig bits are set. example 17-1. configure source #3 transmit for us e with edma channel 2, with periodic triggering capability 1. write 0x00 to chconfig2 (base address + 0x02) 2. configure channel 2 in the ed ma, including enabling the channel 3. configure timer 4 in the periodic interrupt timer (pit) for the desired trigger interval 4. write 0xc3 to chconfig2 (base address + 0x02) the following code example il lustrates steps #1 and #4 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8 bits */ volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); in file main.c: #include "registers.h" : : *chconfig2 = 0x00; *chconfig2 = 0xc3; 17.8.2.2 enabling a source wit hout periodic triggering the following describes how to enable a source without periodic triggering: 1. determine with which edma cha nnel the source will be associ ated. remember that only edma channels 0?3 have periodi c triggering capability. 2. clear the enbl and trig bits of the edma channel. 3. ensure that the edma channel is properly c onfigured in the edma. the edma channel may be enabled at this point. 4. select the source to be routed to the ed ma channel. write to the corresponding chconfig register, ensuring that the enbl is set and the trig bit is cleared. example 17-2. configure source #5 transmit for use with edma channel 2, without periodic triggering capability 1. write 0x00 to chconfig2 (base address + 0x02) 2. configure channel 2 in the ed ma, including enabling the channel 3. write 0x85 to chconfig2 (base address + 0x02) the following code example il lustrates steps #1 and #3 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8 bits */ volatile unsigned char *chconfig2 = (volatile unsigned char *) (dmamux_base_addr+0x0002); in file main.c:
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 305 #include "registers.h" : : *chconfig2 = 0x00; *chconfig2 = 0x85; 17.8.2.3 disabling a source a particular edma source may be di sabled by not writing the correspondi ng source value into any of the chconfig registers. additionally, some module spec ific configuration may be necessary. please refer to the appropriate section for more details. 17.8.2.4 switching the source of an edma channel the following describes how to switch the source of an edma channel: 1. disable the edma channel in the edma and reconfigure th e channel for the new source. 2. clear the enbl and trig bits of the edma channel. 3. select the source to be routed to the ed ma channel. write to the corresponding chconfig register, ensuring that the enbl and trig bits are set. example 17-3. switch edma channel 8 from source #5 transmit to source #7 transmit 1. in the edma configuration registers, disable edma channel 8 and reconfigure it to handle the transfers to peripheral slot 7. this example assu mes channel 8 doesn?t have triggering capability. 2. write 0x00 to chconfig8 (base address + 0x08) 3. write 0x87 to chconfig8 (base address + 0x08). the following code example il lustrates steps #2 and #3 above: in file registers.h: #define dmamux_base_addr 0xfc084000/* example only ! */ /* following example assumes char is 8 bits */ volatile unsigned char *chconfig8 = (volatile unsigned char *) (dmamux_base_addr+0x0008); in file main.c: #include "registers.h" : : *chconfig8 = 0x00; *chconfig8 = 0x87;
chapter 17 edma channel multiplexer (dma_mux) MPC5606BK microcontroller reference manual, rev. 2 306 freescale semiconductor this page is intent ionally left blank.
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 307 chapter 18 interrupt controller (intc) 18.1 introduction the intc provides priority-based preemptive schedul ing of interrupt service requests (isrs). this scheduling scheme is suitable for statically scheduled hard real-t ime systems. the intc supports 204 interrupt requests. it is targeted to work with a power architecture technology processor and automotive powertrain applications where the isrs nest to multiple levels, but it also can be used with other processors and applications. for high priority interrupt requests in these target applications, the time from the assertion of the peripheral?s interrupt request from the peripheral to when the proc essor is performing useful work to service the interrupt request needs to be minimi zed. the intc supports this goal by providing a unique vector for each interrupt request sour ce. it also provides 16 priorities so that lower priority isrs do not delay the execution of higher priority isrs. since each individua l application will have different priorities for each source of interrupt request, the priori ty of each interrupt re quest is configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providi ng a modifiable priority mask, the priority can be raised temporarily so that all ta sks that share the resource cannot preempt each other. multiple processors can assert interrupt requests to each other through software configurable interrupt requests. these same software configurable interrupt requests also can be used to break the work involved in servicing an interrupt request into a high priori ty portion and a low priority portion. the high priority portion is initiated by a peripheral interrupt request, but then the isr can assert a software configurable interrupt request to finish the servicing in a lower priority isr. therefore th ese software configurable interrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. 18.2 features ? supports 196 peripheral and 8 software-c onfigurable interr upt request sources ? unique 9-bit vector per interrupt source ? each interrupt source can be pr ogrammed to one of 16 priorities ? preemption ? preemptive prioritized inte rrupt requests to processor ? isr at a higher priority preempts isrs or tasks at lower priorities ? automatic pushing or popping of pree mpted priority to or from a lifo ? ability to modify the isr or task priority; modi fying the priority can be used to implement the priority ceiling protocol fo r accessing shared resources. ? low latency ? 3 clocks from rece ipt of interrupt request from pe ripheral to interrupt request to processor
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 308 freescale semiconductor table 18-1. interrupt sources available interrupt sources (204 ) number available software 8 ecsm 1 edma 17 software watchdog (swt) 1 stm 4 flash/sram ecc (sec-ded) 2 real time counter (rtc/api) 2 system integration unit lite (siul) 3 wkpu 4 mc_me 4 mc_rgm 1 fxosc 1 sxosc 1 pit 8 adc_0 2 adc_1 2 flexcan_0 8 flexcan_1 8 flexcan_2 8 flexcan_3 8 flexcan_4 8 flexcan_5 8 linflex_0 3 linflex_1 3 linflex_2 3 linflex_3 3 linflex_4 3 linflex_5 3 linflex_6 3 linflex_7 3 dspi_0 5 dspi_1 5 dspi_2 5
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 309 18.3 block diagram figure 18-1 provides a block diagram of the intc. figure 18-1. intc block diagram 18.4 modes of operation 18.4.1 normal mode in normal mode, the intc has two handshaking modes with the processor: software vector mode and hardware vector mode. dspi_3 5 dspi_4 5 dspi_5 5 i2c_0 1 enhanced modular i/o subsystem 0 (emios_0) 16 emios_1 16 table 18-1. interrupt sources available (continued) interrupt sources (204 ) number available hardware vector enable software set/clear interrupt registers flag bits priority select registers peripheral interrupt requests module configuration register highest priority 4 priority comparator slave interface for reads & writes 1 push/update/acknowledge 1 1 1 update interrupt vector 1 interrupt request to processor memory mapped registers non-memory mapped logic end of interrupt register request selector priority arbitrator highest priority interrupt requests n 1 n 1 vector encoder interrupt vector 9 processor 0 interrupt acknowledge register interrupt vector 9 n 1 8 n 1 x 4-bits new priority 4 current priority 4 processor 0 current priority register processor 0 priority lifo pop 1 lowest vector interrupt request 1 vector table entry size pushed priority 4 popped priority 4 interrupt acknowledge peripheral bus
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 310 freescale semiconductor 18.4.1.1 software vector mode in software vector mode, so ftware, that is the interrupt exception handler, must read a register in the intc to obtain the vector associated with the interrupt request to the proc essor. the intc will use software vector mode for a given processor when its associated hven bit in intc_mcr is negated. the hardware vector enable signal to processor 0 or processor 1 is driven as negate d when its associated hven bit is negated. the vector is read from inc_iackr. re ading the intc_iackr negates the interrupt request to the associated processor. even if a higher priori ty interrupt request arrived while waiting for this interrupt acknowledge, the interrupt request to the proces sor will negate for at l east one clock. the reading also pushes the pri value in intc_cpr onto the a ssociated lifo and updates pri in the associated intc_cpr with the new priority. furthermore, the interrupt vector to the processor is driven as all 0s. the interrupt acknowledge signal from the associated processor is ignored. 18.4.1.2 hardware vector mode in hardware vector mode, the hardwa re is the interrupt vector signal from the intc in conjunction with a processor with the capability use that vector. in hard ware vector mode, this ha rdware causes the first instruction to be executed in handling the interrupt re quest to the processor to be specific to that vector. therefore the interrupt exception handl er is specific to a peripheral or software configurable interrupt request rather than being common to all of them. the intc uses hardware vector mode for a given processor when the associated hven bit in the intc _mcr is asserted. the hardwa re vector enable signal to the associated processor is driven as asserted. wh en the interrupt request to the associated processor asserts, the interrupt vector signal is updated. the va lue of that interrupt vector is the unique vector associated with the preempting peri pheral or software configurable in terrupt request. the vector value matches the value of the intvec field in the in tc_iackr field in the intc_iackr, depending on which processor was assigned to handle a given interrupt source. the processor negates the interrupt request to the pr ocessor driven by the intc by asserting the interrupt acknowledge signal for one cl ock. even if a higher priority interrupt request arrived while waiting for the interrupt acknowledge, the interrupt request to the processor will negate for at least one clock. the assertion of the interrupt acknowledge signal for a given processor pushes the associated pri value in the associated intc_cpr register onto the associ ated lifo and updates the associated pri in the associated intc_cpr register with the new priority . this pushing of the pri value onto the associated lifo and updating pri in the asso ciated intc_cpr does not occur when the associated interrupt acknowledge signal asserts and intc_sscir0_3?intc_sscir4_7 is writt en at a time such that the pri value in the associated intc_cpr register would need to be pushed and the previously last pushed pri value would need to be popped simu ltaneously. in this ca se, pri in the associated intc_cpr is updated with the new priority, and the associ ated lifo is neither pushed or popped. 18.4.1.3 debug mode the intc operation in debug mode is iden tical to its operation in normal mode.
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 311 18.4.1.4 stop mode the intc supports stop mode. the intc can have its clock input di sabled at any time by the clock driver on the device. while its clocks are di sabled, the intc regist ers are not accessible. the intc requires clocking in order for a peripheral inte rrupt request to generate an interrupt request to the processor. since the intc is not clocked in stop mode, periphera l interrupt requests cannot be used as a wakeup source, unless the device supports that interrupt request as a wakeup source. 18.5 memory map and register description 18.5.1 module memory map table 18-2 shows the intc memory map. 18.5.2 register description with exception of the intc_ssci n and intc_psr n , all registers are 32 bits in width. any combination of accessing the 4 bytes of a register with a single access is supported, provided that the access does not cross a register boundary. these supported accesses incl ude types and sizes of 8 bits, aligned 16 bits, misaligned 16 bits to the middl e 2 bytes, and aligned 32 bits. although intc_ssci n and intc_psr n are 8 bits wide, they can be accessed with a single 16-bit or 32-bit access, provided th at the access does not cross a 32-bit boundary. table 18-2. intc memory map base address: 0xfff4_8000 address offset register location 0x0000 intc module configuration register (intc_mcr) on page 312 0x0004 reserved 0x0008 intc current priority register for processor (intc_cpr) on page 312 0x000c reserved 0x0010 intc interrupt acknowledge register (intc_iackr) on page 314 0x0014 reserved 0x0018 intc end-of-interr upt register (intc_eoir) on page 315 0x001c reserved 0x0020?0x0027 intc software set/clear interrupt registers (intc_sscir0_3?intc_sscir4_7) on page 316 0x0028?0x003c reserved 0x0040?0x00d0 intc priority select registers (intc_psr0_3?intc_psr232_233) 1 1 the pri fields are reserved for peripheral interrupt requests whose vectors are labeled reserved in figure 18-3 . on page 317
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 312 freescale semiconductor in software vector mode, th e side effects of a read of intc_iackr are the same regardless of the size of the read. in either software or hardware vector mode, the size of a write to either intc_sscir0_3?intc_sscir4_7 or intc_eoir doe s not affect the ope ration of the write. 18.5.2.1 intc module configur ation register (intc_mcr) the module configuration register is us ed to configure options of the intc. 18.5.2.2 intc current priority re gister for processor (intc_cpr) offset: 0x0000 access: user read/write 0123456789101112131415 r0000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000 vtes 0000 hven w reset 0000000000000000 figure 18-2. intc module configuration register (intc_mcr) table 18-3. intc_mcr field descriptions field description vtes vector table entry size. controls the number of 0s to the right of intvec in section 18.5.2.3, intc interrupt acknowledge register (intc_iackr) . if the contents of intc_iackr are used as an address of an entry in a vector table as in software vector mode, then the number of rightmost 0s will determine the size of each vector table entry. vtes im pacts software vector mode operation but also affects intc_iackr[intvec] position in both hardware vector mode and software vector mode. 0 4 bytes 1 8 bytes hven hardware vector enable. controls whether the intc is in hardware ve ctor mode or software vector mode. refer to section 18.4, modes of operation , for the details of the handshaking with the processor in each mode. 0 software vector mode 1 hardware vector mode
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 313 the intc_cpr masks any peripheral or software configurable interrupt request set at the same or lower priority as the current value of the intc_cpr[pri] field from genera ting an interrupt request to the processor. when the intc interrupt acknowledge regi ster (intc_iackr) is r ead in software vector mode or the interrupt acknowledge signal from the pr ocessor is asserted in ha rdware vector mode, the value of pri is pushed onto the li fo, and pri is updated with the pr iority of the preempting interrupt request. when the intc end-of-inter rupt register (intc_eoir) is wr itten, the lifo is popped into the intc_cpr?s pri field. the masking priority can be raised or lowered by wr iting to the pri field, supporting the pcp. refer to section 18.7.5, priority ceiling protocol . note a store to modify the pri fi eld that closely precedes or follows an access to a shared resource can result in a non-c oherent access to th at resource. refer to section 18.7.5.2, ensuring coherency , for example code to ensure coherency. offset: 0x0008 access: user read/write 012345678910111213141516171819202122232425262728293031 r0000000000000000000000000000 pri w reset00000000000000000000000000001111 figure 18-3. intc current priority register (intc_cpr) table 18-4. intc_cpr field descriptions field description pri priority pri is the priority of the currently executing isr according to the field values defined in ta bl e 1 8 - 5 . table 18-5. pri values pri meaning 1111 priority 15?highest priority 1110 priority 14 1101 priority 13 1100 priority 12 1011 priority 11 1010 priority 10 1001 priority 9 1000 priority 8 0111 priority 7
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 314 freescale semiconductor 18.5.2.3 intc interrupt acknowledge register (intc_iackr) 0110 priority 6 0101 priority 5 0100 priority 4 0011 priority 3 0010 priority 2 0001 priority 1 0000 priority 0?lowest priority offset: 0x0010 access: user read/write 0123456789101112131415 r vtba[20:5] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba[4:0] intvec 0 0 w reset 0000000000000000 figure 18-4. intc interrupt acknowledge register (intc_iackr) when intc_mcr[vtes] = 0 offset: 0x0010 access: user read/write 0123456789101112131415 r vtba[19:4] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r vtba[3:0] intvec 0 0 0 w reset 0000000000000000 figure 18-5. intc interrupt acknowledge register (intc_iackr) when intc_mcr[vtes] = 1 table 18-5. pri values (continued) pri meaning
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 315 the interrupt acknowledge register provides a va lue that can be used to load the address of an isr from a vector table. the vector table ca n be composed of addresses of th e isrs specific to their respective interrupt vectors. in software vector mode, the intc _iackr has side effects from re ads. therefore, it must not be speculatively read while in this m ode. the side effects are the same regardless of the size of the read. reading the intc_iackr does not have si de effects in hardware vector mode. 18.5.2.4 intc end-of-interrupt register (intc_eoir) writing to the end-of-interrupt regi ster signals the end of the servici ng of the interrupt request. when the intc_eoir is written, the priority last pushed on th e lifo is popped into intc _cpr. an exception to this behavior is described in section 18.4.1.2, hardwa re vector mode . the values and size of data written to the intc_eoir are ignored. the values and sizes written to this regi ster neither update the intc_eoir contents or affect whet her the lifo pops. for possible future compatib ility, write four bytes of all 0s to the intc_eoir. reading the intc_eoir has no effect on the lifo. table 18-6. intc_iackr field descriptions field description vtba vector table base address can be the base address of a vector table of addresses of isrs. intvec interrupt vector it is the vector of the peripheral or software conf igurable interrupt request that caused the interrupt request to the processor. when the interrupt request to the processor asserts, the intvec is updated, whether the intc is in software or hardware vector mode. offset: 0x0018 access: write only 012345678910111213141516171819202122232425262728293031 r000000000000000000 00000000 000000 wsee text reset 00000000000000000000000000000000 figure 18-6. intc end-of-interrupt register (intc_eoir)
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 316 freescale semiconductor 18.5.2.5 intc software set/clear interrupt registers (intc_sscir0_3?i ntc_sscir4_7) the software set/clear interrupt regi sters support the setting or clearing of software configurable interrupt request. these registers cont ain eight independent sets of bits to set and clea r a corresponding flag bit by offset: 0x0020 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 clr0 0 0 0 0 0 0 0 clr1 w set0 set1 reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr2 0 0 0 0 0 0 0 clr3 w set2 set3 reset 0000000000000000 figure 18-7. intc software set/clear interrupt register 0?3 (intc_sscir[0:3]) offset: 0x0024 access: user read/write 0123456789101112131415 r 0 0 0 0 0 0 0 clr4 0 0 0 0 0 0 0 clr5 w set4 set5 reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 clr6 0 0 0 0 0 0 0 clr7 w set6 set7 reset 0000000000000000 figure 18-8. intc software set/clear interrupt register 4?7 (intc_sscir[4:7]) table 18-7. intc_sscir[0:7] field descriptions field description setx set flag bits writing a 1 sets the corresponding clr x bit. writing a 0 has no effect. each set x always will be read as a 0. clrx clear flag bits clr x is the flag bit. writing a 1 to clr x clears it provided that a 1 is not written simultaneously to its corresponding set x bit. writing a 0 to clr x has no effect. 0 interrupt request not pending within intc 1 interrupt request pending within intc
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 317 software. excepting being set by software, this flag bit behaves the same as a flag bit set within a peripheral. this flag bit ge nerates an interrupt request within the intc like a periphera l interrupt request. writing a 1 to set x will leave set x unchanged at 0 but sets clr x . writing a 0 to set x has no effect. clr x is the flag bit. writing a 1 to clr x clears it. writing a 0 to clr x has no effect. if a 1 is written simultaneously to a pair of set x and clr x bits, clr x will be asserted, rega rdless of whether clr x was asserted before the write. 18.5.2.6 intc priority select regi sters (intc_psr0 _3?intc_psr232_233) offset: 0x0040 access: user read/write 0123456789101112131415 r 0000 pri0 0000 pri1 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 pri2 0000 pri3 w reset 0000000000000000 figure 18-9. intc priority select register 0?3 (intc_psr[0:3]) offset: 0x0128 access: user read/write 0123456789101112131415 r0 0 0 0 pri232 0000 pri233 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset 0000000000000000 figure 18-10. intc priority select register 232?233 (intc_psr[232:233]) table 18-8. intc_psr0_3?intc_psr232_233 field descriptions field description pri priority select pri x selects the priority for interrupt requests. see section 18.6, functional description .
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 318 freescale semiconductor table 18-9. intc priority select register address offsets intc_psr x _ x offset address intc_psr x _ x offset address intc_psr0_3 0x0040 intc_psr120_123 0x00b8 intc_psr4_7 0x0044 intc_psr124_127 0x00bc intc_psr8_11 0x0048 intc_psr128_131 0x00c0 intc_psr12_15 0x004c intc_psr132_135 0x00c4 intc_psr16_19 0x0050 intc_psr136_139 0x00c8 intc_psr20_23 0x0054 intc_psr140_143 0x00cc intc_psr24_27 0x0058 intc_psr144_147 0x00d0 intc_psr28_31 0x005c intc_psr148_151 0x00d4 intc_psr32_35 0x0060 intc_psr152_155 0x00d8 intc_psr36_39 0x0064 intc_psr156_159 0x00dc intc_psr40_43 0x0068 intc_psr160_163 0x00e0 intc_psr44_47 0x006c intc_psr164_167 0x00e4 intc_psr48_51 0x0070 intc_psr168_171 0x00e8 intc_psr52_55 0x0074 intc_psr172_175 0x00ec intc_psr56_59 0x0078 intc_psr176_179 0x00f0 intc_psr60_63 0x007c intc_psr180_183 0x00f4 intc_psr64_67 0x0080 intc_psr184_187 0x00f8 intc_psr68_71 0x0084 intc_psr188_191 0x00fc intc_psr72_75 0x0088 intc_psr192_195 0x0100 intc_psr76_79 0x008c intc_psr196_199 0x0104 intc_psr80_83 0x0090 intc_psr200_203 0x0108 intc_psr84_87 0x0094 intc_psr204_207 0x010c intc_psr88_91 0x0098 intc_psr208_211 0x0110 intc_psr92_95 0x009c intc_psr212_215 0x0114 intc_psr96_99 0x00a0 intc_psr216_219 0x0118 intc_psr100_103 0x00a4 intc_psr220_223 0x011c intc_psr104_107 0x00a8 intc_psr224_227 0x0120 intc_psr108_111 0x00ac intc_psr228_231 0x0124 intc_psr112_115 0x00b0 intc_psr232_233 0x0128 intc_psr116_119 0x00b4
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 319 18.6 functional description the functional description involves the areas of interrupt request s ources, priority management, and handshaking with the processor. note the intc has no spurious vector s upport. therefore, if an asserted peripheral or software settabl e interrupt request, whose pri n value in intc_psr0?intc_psr233 is higher than the pri value in intc_cpr, negates before the interrupt request to the processo r for that peripheral or software settable interrupt request is acknowledged, the interrupt request to the processor still can assert or will remain asserted for that peripheral or software settable interrupt request. in this case, the interrupt vector will correspond to that peripheral or software settable interrupt request. also, the pri value in the intc_cpr will be updated with the corresponding pri n value in intc_psr n . furthermore, clearing the peripheral interrupt request?s enable bit in the peripheral or, alternatively, setting its mask bit has the same consequences as clearing its flag bit. setting its enable bit or clearing its mask bit while its flag bit is asserted has the same effect on the intc as an interrupt event setting the flag bit. table 18-10. interrupt vector table irq # offset size (bytes) interrupt module section a (core section) ? 0x0000 16 critical input (intc software vector mode) / nmi core ? 0x0010 16 machine check / nmi core ? 0x0020 16 data storage core ? 0x0030 16 instruction storage core ? 0x0040 16 external input (intc software vector mode) core ? 0x0050 16 alignment core ?0x0060 16program core ? 0x0070 16 reserved core ? 0x0080 16 system call core ? 0x0090 96 unused core ? 0x00f0 16 debug core ? 0x0100 1792 unused core section b (on-platform peripherals) 0 0x0800 4 software configurable flag 0 software
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 320 freescale semiconductor 1 0x0804 4 software configurable flag 1 software 2 0x0808 4 software configurable flag 2 software 3 0x080c 4 software configurable flag 3 software 4 0x0810 4 software configurable flag 4 software 5 0x0814 4 software configurable flag 5 software 6 0x0818 4 software configurable flag 6 software 7 0x081c 4 software configurable flag 7 software 8 0x0820 4 reserved 9 0x0824 4 platform flash bank 0 abort | platform flash bank 0 stall | platform flash bank 1 abort | platform flash bank 1 stall | ecsm 10 0x0828 4 combined error edma 11 0x082c 4 channel 0 edma 12 0x0830 4 channel 1 edma 13 0x0834 4 channel 2 edma 14 0x0838 4 channel 3 edma 15 0x083c 4 channel 4 edma 16 0x0840 4 channel 5 edma 17 0x0844 4 channel 6 edma 18 0x0848 4 channel 7 edma 19 0x084c 4 channel 8 edma 20 0x0850 4 channel 9 edma 21 0x0854 4 channel 10 edma 22 0x0858 4 channel 11 edma 23 0x085c 4 channel 12 edma 24 0x0860 4 channel 13 edma 25 0x0864 4 channel 14 edma 26 0x0868 4 channel 15 edma 27 0x086c 4 reserved 28 0x0870 4 timeout swt 29 0x0874 4 reserved 30 0x0878 4 match on channel 0 stm table 18-10. interrupt vector table (continued) irq # offset size (bytes) interrupt module
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 321 31 0x087c 4 match on channel 1 stm 32 0x0880 4 match on channel 2 stm 33 0x0884 4 match on channel 3 stm 34 0x0888 4 reserved 35 0x088c 4 ecc_dbd_platformflash | ecc_dbd_platformram platform ecc double bit detection 36 0x0890 4 ecc_sbc_platformflash | ecc_sbc_platformram platform ecc single bit correction 37 0x0894 4 reserved section c 38 0x0898 4 rtc rtc/api 39 0x089c 4 api rtc/api 40 0x08a0 4 reserved 41 0x08a4 4 siu external irq_0 siul 42 0x08a8 4 siu external irq_1 siul 43 0x08ac 4 siu external irq_2 siul 44 0x08b0 4 reserved 45 0x08b4 4 reserved 46 0x08b8 4 wakeup_irq_0 wkpu 47 0x08bc 4 wakeup_irq_1 wkpu 48 0x08c0 4 wakeup_irq_2 wkpu 49 0x08c4 4 wakeup_irq_3 wkpu 50 0x08c8 4 reserved 51 0x08cc 4 safe mode interrupt mc_me 52 0x08d0 4 mode transition interrupt mc_me 53 0x08d4 4 invalid mode interrupt mc_me 54 0x08d8 4 invalid mode config mc_me 55 0x08dc 4 reserved 56 0x08e0 4 functional and destructive reset alternate event interrupt (ipi_int) mc_rgm 57 0x08e4 4 fxosc counter expired (ipi_int_osc) fxosc 58 0x08e8 4 reserved 59 0x08ec 4 pitimer channel 0 pit table 18-10. interrupt vector table (continued) irq # offset size (bytes) interrupt module
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 322 freescale semiconductor 60 0x08f0 4 pitimer channel 1 pit 61 0x08f4 4 pitimer channel 2 pit 62 0x08f8 4 adc_eoc adc_0 64 0x0900 4 adc_wd adc_0 63 0x08fc 4 reserved 65 0x0904 4 flexcan_esr[err_int] flexcan_0 66 0x0908 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_0 67 0x090c 4 reserved 68 0x0910 4 flexcan_buf_00_03 flexcan_0 69 0x0914 4 flexcan_buf_04_07 flexcan_0 70 0x0918 4 flexcan_buf_08_11 flexcan_0 71 0x091c 4 flexcan_buf_12_15 flexcan_0 72 0x0920 4 flexcan_buf_16_31 flexcan_0 73 0x0924 4 flexcan_buf_32_63 flexcan_0 74 0x0928 4 dspi_sr[tfuf] dspi_sr[rfof] dspi_0 75 0x092c 4 dspi_sr[eoqf] dspi_0 76 0x0930 4 dspi_sr[tfff] dspi_0 77 0x0934 4 dspi_sr[tcf] dspi_0 78 0x0938 4 dspi_sr[rfdf] dspi_0 79 0x093c 4 linflex_rxi linflex_0 80 0x0940 4 linflex_txi linflex_0 81 0x0944 4 linflex_err linflex_0 82 0x0948 4 adc_eoc adc_1 83 0x094c 4 reserved 84 0x0950 4 adc_wd adc_1 85 0x0954 4 flexcan_esr[err_int] flexcan_1 86 0x0958 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_1 87 0x095c 4 reserved 88 0x0960 4 flexcan_buf_00_03 flexcan_1 table 18-10. interrupt vector table (continued) irq # offset size (bytes) interrupt module
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 323 89 0x0964 4 flexcan_buf_04_07 flexcan_1 90 0x0968 4 flexcan_buf_08_11 flexcan_1 91 0x096c 4 flexcan_buf_12_15 flexcan_1 92 0x0970 4 flexcan_buf_16_31 flexcan_1 93 0x0974 4 flexcan_buf_32_63 flexcan_1 94 0x0978 4 dspi_sr[tfuf] dspi_sr[rfof] dspi_1 95 0x097c 4 dspi_sr[eoqf] dspi_1 96 0x0980 4 dspi_sr[tfff] dspi_1 97 0x0984 4 dspi_sr[tcf] dspi_1 98 0x0988 4 dspi_sr[rfdf] dspi_1 99 0x098c 4 linflex_rxi linflex_1 100 0x0990 4 linflex_txi linflex_1 101 0x0994 4 linflex_err linflex_1 102 0x0998 4 reserved 103 0x099c 4 reserved 104 0x09a0 4 reserved 105 0x09a4 4 flexcan_[err_int] flexcan_2 106 0x09a8 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_2 107 0x09ac 4 reserved 108 0x09b0 4 flexcan_buf_00_03 flexcan_2 109 0x09b4 4 flexcan_buf_04_07 flexcan_2 110 0x09b8 4 flexcan_buf_08_11 flexcan_2 111 0x09bc 4 flexcan_buf_12_15 flexcan_2 112 0x09c0 4 flexcan_buf_16_31 flexcan_2 113 0x09c4 4 flexcan_buf_32_63 flexcan_2 114 0x09c8 4 dspi_sr[tfuf] dspi_sr[rfof] dspi_2 115 0x09cc 4 dspi_sr[eoqf] dspi_2 116 0x09d0 4 dspi_sr[tfff] dspi_2 117 0x09d4 4 dspi_sr[tcf] dspi_2 118 0x09d8 4 dspi_sr[rfdf] dspi_2 table 18-10. interrupt vector table (continued) irq # offset size (bytes) interrupt module
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 324 freescale semiconductor 119 0x09dc 4 linflex_rxi linflex_2 120 0x09e0 4 linflex_txi linflex_2 121 0x09e4 4 linflex_err linflex_2 122 0x09e8 4 linflex_rxi linflex_3 123 0x09ec 4 linflex_txi linflex_3 124 0x09f0 4 linflex_err linflex_3 125 0x09f4 4 i2c_sr[ibal] i2c_sr[tcf] i2c_sr[iaas] i2c_0 126 0x09f8 4 reserved 127 0x09fc 4 pitimer channel 3 pit 128 0x0a00 4 pitimer channel 4 pit 129 0x0a04 4 pitimer channel 5 pit 130 0x0a08 4 pitimer channel 6 pit 131 0x0a0c 4 pitimer channel 7 pit 132 0x0a10 4 reserved 133 0x0a14 4 reserved 134 0x0a18 4 reserved 135 0x0a1c 4 reserved 136 0x0a20 4 reserved 137 0x0a24 4 reserved 138 0x0a28 4 reserved 139 0x0a2c 4 reserved 140 0x0a30 4 reserved 141 0x0a34 4 emios_gf r[f0,f1] emios_0 142 0x0a38 4 emios_gf r[f2,f3] emios_0 143 0x0a3c 4 emios_gf r[f4,f5] emios_0 144 0x0a40 4 emios_gf r[f6,f7] emios_0 145 0x0a44 4 emios_gf r[f8,f9] emios_0 146 0x0a48 4 emios_gf r[f10,f11] emios_0 147 0x0a4c 4 emios_gf r[f12,f13] emios_0 148 0x0a50 4 emios_gf r[f14,f15] emios_0 149 0x0a54 4 emios_gf r[f16,f17] emios_0 table 18-10. interrupt vector table (continued) irq # offset size (bytes) interrupt module
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 325 150 0x0a58 4 emios_gf r[f18,f19] emios_0 151 0x0a5c 4 emios_gf r[f20,f21] emios_0 152 0x0a60 4 emios_gf r[f22,f23] emios_0 153 0x0a64 4 emios_gf r[f24,f25] emios_0 154 0x0a68 4 emios_gf r[f26,f27] emios_0 155 0x0a6c 4 emios_gf r[f28,f29] emios_0 156 0x0a70 4 emios_gf r[f30,f31] emios_0 section d (device specific vectors) 157 0x0a74 4 emios_gf r[f0,f1] emios_1 158 0x0a78 4 emios_gf r[f2,f3] emios_1 159 0x0a7c 4 emios_gf r[f4,f5] emios_1 160 0x0a80 4 emios_gf r[f6,f7] emios_1 161 0x0a84 4 emios_gf r[f8,f9] emios_1 162 0x0a88 4 emios_gf r[f10,f11] emios_1 163 0x0a8c 4 emios_gf r[f12,f13] emios_1 164 0x0a90 4 emios_gf r[f14,f15] emios_1 165 0x0a94 4 emios_gf r[f16,f17] emios_1 166 0x0a98 4 emios_gf r[f18,f19] emios_1 167 0x0a9c 4 emios_gf r[f20,f21] emios_1 168 0x0aa0 4 emios_gfr[f22,f23] emios_1 169 0x0aa4 4 emios_gfr[f24,f25] emios_1 170 0x0aa8 4 emios_gfr[f26,f27] emios_1 171 0x0aac 4 emios_gf r[f28,f29] emios_1 172 0x0ab0 4 emios_gfr[f30,f31] emios_1 173 0x0ab4 4 flexcan_esr flexcan_3 174 0x0ab8 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_3 175 0x0abc 4 reserved 176 0x0ac0 4 flexcan_buf_0_3 flexcan_3 177 0x0ac4 4 flexcan_buf_4_7 flexcan_3 178 0x0ac8 4 flexcan_buf_8_11 flexcan_3 179 0x0acc 4 flexcan_buf_12_15 flexcan_3 table 18-10. interrupt vector table (continued) irq # offset size (bytes) interrupt module
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 326 freescale semiconductor 180 0x0ad0 4 flexcan_buf_16_31 flexcan_3 181 0x0ad4 4 flexcan_buf_32_63 flexcan_3 182 0x0ad8 4 dspi_sr[tfuf] dspi_sr[rfof] dspi_3 183 0x0adc 4 dspi_sr[eoqf] dspi_3 184 0x0ae0 4 dspi_sr[tfff] dspi_3 185 0x0ae4 4 dspi_sr[tcf] dspi_3 186 0x0ae8 4 dspi_sr[rfdf] dspi_3 187 0x0aec 4 linflex_rxi linflex_4 188 0x0af0 4 linflex_txi linflex_4 189 0x0af4 4 linflex_err linflex_4 190 0x0af8 4 flexcan_esr flexcan_4 191 0x0afc 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_4 192 0x0b00 4 reserved 193 0x0b04 4 flexcan_buf_0_3 flexcan_4 194 0x0b08 4 flexcan_buf_4_7 flexcan_4 195 0x0b0c 4 flexcan_buf_8_11 flexcan_4 196 0x0b10 4 flexcan_buf_12_15 flexcan_4 197 0x0b14 4 flexcan_buf_16_31 flexcan_4 198 0x0b18 4 flexcan_buf_32_63 flexcan_4 199 0x0b1c 4 linflex_rxi linflex_5 200 0x0b20 4 linflex_txi linflex_5 201 0x0b24 4 linflex_err linflex_5 202 0x0b28 4 flexcan_esr flexcan_5 203 0x0b2c 4 flexcan_esr_boff | flexcan_transmit_warning | flexcan_receive_warning flexcan_5 204 0x0b30 4 reserved 205 0x0b34 4 flexcan_buf_0_3 flexcan_5 206 0x0b38 4 flexcan_buf_4_7 flexcan_5 207 0x0b3c 4 flexcan_buf_8_11 flexcan_5 208 0x0b40 4 flexcan_buf_12_15 flexcan_5 table 18-10. interrupt vector table (continued) irq # offset size (bytes) interrupt module
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 327 18.6.1 interrupt request sources the intc has two types of interr upt requests, peripheral and softwa re configurable. these interrupt requests can assert on any clock cycle. 209 0x0b44 4 flexcan_buf_16_31 flexcan_5 210 0x0b48 4 flexcan_buf_32_63 flexcan_5 211 0x0b4c 4 dspi_sr[tfuf] dspi_sr[rfof] dspi_4 212 0x0b50 4 dspi_sr[eoqf] dspi_4 213 0x0b54 4 dspi _sr[tfff] dspi_4 214 0x0b58 4 dspi_sr[tcf] dspi_4 215 0x0b5c 4 dspi_sr[rfdf] dspi_4 216 0x0b60 4 linflex_rxi linflex_6 217 0x0b64 4 linflex_txi linflex_6 218 0x0b68 4 linflex_err linflex_6 219 0x0b6c 4 dspi_sr[tfuf] dspi_sr[rfof] dspi_5 220 0x0b70 4 dspi_sr[eoqf] dspi_5 221 0x0b74 4 dspi _sr[tfff] dspi_5 222 0x0b78 4 dspi_sr[tcf] dspi_5 223 0x0b7c 4 dspi_sr[rfdf] dspi_5 224 0x0b80 4 linflex_rxi linflex_7 225 0x0b84 4 linflex_txi linflex_7 226 0x0b88 4 linflex_err linflex_7 227 0x0b8c 4 reserved 228 0x0b90 4 reserved 229 0x0b94 4 reserved 230 0x0b98 4 reserved 231 0x0b9c 4 reserved 232 0x0ba0 4 reserved 233 0x0ba4 4 32kxosc counter expired sxosc table 18-10. interrupt vector table (continued) irq # offset size (bytes) interrupt module
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 328 freescale semiconductor 18.6.1.1 peripheral interrupt requests an interrupt event in a peripheral?s hardware sets a flag bit that resi des in the peripheral. the interrupt request from the peripheral is driven by that flag bit. the time from when the peripheral starts to drive its peripheral interrupt request to the intc to the time that the intc starts to drive the interrupt request to the processor is three clocks. external interrupts are handled by the siu (see section 20.6.3, external interrupts ). 18.6.1.2 software configurable interrupt requests an interrupt request is triggered by software by writing a 1 to a set x bit in intc_sscir0_3?intc_sscir4_7. th is write sets the corr esponding flag bit, clr x , resulting in the interrupt request. the interrupt request is cleared by writing a 1 to the clr x bit. the time from the write to the set x bit to the time that th e intc starts to drive th e interrupt request to the processor is four clocks. 18.6.1.3 unique vector for ea ch interrupt request source each peripheral and software confi gurable interrupt request is assigne d a hardwired unique 9-bit vector. software configurable interrupts 0?7 are assigned vectors 0?7 respectively. the peripheral interrupt requests are assigned vectors 8 to as high as needed to in clude all the peripheral interrupt requests. the peripheral interrupt request input por ts at the boundary of the intc bl ock are assigned specific hardwired vectors within the intc (see table 18-1 ). 18.6.2 priority management the asserted interrupt requests are comp ared to each other based on their pri x values set in the intc priority select regist ers (intc_psr0_3?intc_psr232_233). the resu lt is compared to pri in the associated intc_cpr. the results of those comparis ons manage the priority of the isr executed by the associated processor. the associated lifo also assists in managing that priority. 18.6.2.1 current prio rity and preemption the priority arbitrator, selector, encode r, and comparator subblocks shown in figure 18-1 compare the priority of the asserted inte rrupt requests to the current priority. if the priority of any asserted peripheral or software configurable interrupt reque st is higher than the current priority for a given processor, then the interrupt request to the processor is asserted. al so, a unique vector for the preempting peripheral or software configurable interrupt request is generated for intc interrupt acknowledge register (intc_iackr), and if in hardware vector mode, for the interrupt vector provided to the processor. 18.6.2.1.1 priority arbitrator subblock the priority arbitrator subblock for e ach processor compares all the prioriti es of all of the asserted interrupt requests assigned to that processor, both peripheral a nd software configurable. th e output of the priority arbitrator subblock is the highest of those priorities assigned to a gi ven processor. also, any interrupt
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 329 requests that have this highest priority are output as asserted interrupt requests to the associated request selector subblock. 18.6.2.1.2 request selector subblock if only one interrupt request from the associated priority arbitrator subbloc k is asserted, then it is passed as asserted to the associ ated vector encoder subbloc k. if multiple interrupt re quests from the associated priority arbitrator s ubblock are asserted, the only the one with the lowest vector is passed as asserted to the associated vector encode r subblock. the lower vector is chosen regardless of the time order of the assertions of the peripheral or soft ware configurable interrupt requests. 18.6.2.1.3 vector encoder subblock the vector encoder subblock generate s the unique 9-bit vector for the as serted interrupt request from the request selector subblock fo r the associated processor. 18.6.2.1.4 priority comparator subblock the priority comparator subblock co mpares the highest priority output from the priority arbitrator subblock with pri in intc_cpr. if th e priority comparator subblock detect s that this highest priority is higher than the current priority, then it asserts the interrupt request to the associated processor. this interrupt request to the processor asse rts whether this highest priority is raised above the value of pri in intc_cpr or the pri value in intc _cpr is lowered below this highest priority. this highest priority then becomes the new priority, which will be written to pri in intc_cpr when the interrupt request to the processor is acknowledged. interrupt requests whose pri n in intc_psr n are zero will not cause a preemption because their pri n will not be higher than pri in intc_cpr. 18.6.2.2 last-in first-out (lifo) the lifo stores the preempted pri values from the intc_cpr. therefore, becau se these priorities are stacked within the intc, if interrupt s need to be enabled during the isr, at the beginning of the interrupt exception handler the pri value in the intc_cpr does not need to be loaded from the intc_cpr and stored onto the context stack. likewise at the end of the interrupt exce ption handler, the priority does not need to be loaded from the context stack and stored in to the intc_cpr. the pri value in the intc_cpr is pushed onto the li fo when the intc_iackr is read in software vector mode or the interrupt acknowl edge signal from the processor is as serted in hardware vector mode. the priority is popped into pri in the in tc_cpr whenever the intc_eoir is written. although the intc supports 16 priorities, an isr execut ing with pri in the intc_cpr equal to 15 will not be preempted. therefore, the lifo supports the st acking of 15 priorities. ho wever, the lifo is only 14 entries deep. an entry for a priority of 0 is not needed because of how pushing onto a full lifo and popping an empty lifo are treat ed. if the lifo is pushed 15 or more times than it is popped, the priorities first pushed are overwritten. a priority of 0 woul d be an overwritten priority . however, the lifo will pop 0s if it is popped more times than it is pushed. ther efore, although a priority of 0 was overwritten, it is regenerated with the popping of an empty lifo. the lifo is not memory mapped.
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 330 freescale semiconductor 18.6.3 handshaking with processor 18.6.3.1 software vector mode handshaking this section describes handshaki ng in software vector mode. 18.6.3.1.1 acknowledging interrupt request to processor a timing diagram of the interrupt request and acknow ledge handshaking in software vector mode, along with the handshaking near the end of th e interrupt exception handler, is shown in figure 18-11 . the intc examines the peripheral and software configurable interrupt requests. when it finds an asserted peripheral or software configurable interrupt request with a higher priority than pri in the associated intc_cpr, it asserts the interrupt request to the processor. the intvec field in th e associated intc _iackr is updated with the preempting interrupt request?s vector when the interrupt request to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. the rest of the handshaking is described in section 18.4.1.1, software vector mode . 18.6.3.1.2 end of inte rrupt exception handler before the interrupt exception handli ng completes, intc end-of-interrupt register (intc_eoir) must be written.when written, the associated lifo is popped so th e preempted priority is restored into pri of the intc_cpr. before it is written, the peripheral or software configurable flag bit must be cleared so that the peripheral or software configur able interrupt request is negated. note to ensure proper operation across all power architecture mcus, execute an mbar or msync instruction between the access to clear the flag bit and the write to the intc_eoir. when returning from the preemption, the intc does not search for the periphe ral or software settable interrupt request whose isr was pr eempted. depending on how much the isr progressed, that interrupt request may no longer even be asserted. when pri in intc_cpr is lowered to the priority of the preempted isr, the interrupt reques t for the preempted isr or any othe r asserted peripheral or software settable interrupt request at or below that priority wi ll not cause a preemption. in stead, after the restoration of the preempted context, the processor will return to the instruction address that it was to next execute before it was preempted. this next instruction is part of the preempt ed isr or the interrupt exception handler?s prolog or epilog.
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 331 figure 18-11. software vector mode handshaking timing diagram 18.6.3.2 hardware vector mode handshaking a timing diagram of the in terrupt request and acknow ledge handshaking in hard ware vector mode, along with the handshaking near the end of the interrupt exception handler, is shown in figure 18-12 . as in software vector mode, the intc ex amines the peripheral and software settable interrupt requests, and when it finds an asserted one with a higher priority than pri in intc_cpr, it as serts the interrupt request to the processor. the intvec field in the intc_i ackr is updated with the preempting peripheral or software settable interrupt request?s vector when th e interrupt request to the processor is asserted. the intvec field retains that value until the next time the interrupt request to the processor is asserted. in addition, the value of the interrupt v ector to the processor matches the value of the intvec field in the intc_iackr. the rest of the handshaking is described in section 18.7.2.2, hardware vector mode . the handshaking near the end of the interrupt excepti on handler, that is the wri ting to the intc_eoir, is the same as in software vector mode. refer to section 18.6.3.1.2, end of interrupt exception handler . 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 108 0
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 332 freescale semiconductor figure 18-12. hardware vector mode handshaking timing diagram 18.7 initialization/application information 18.7.1 initialization flow after exiting reset, all of the pri n fields in intc priority select registers (intc_psr0?intc_psr233) will be zero, and pri in intc curr ent priority register (intc_cpr) wi ll be 15. these reset values will prevent the intc from asserting the interrupt request to the processor. the enable or mask bits in the peripherals are reset such that the peripheral interr upt requests are negated. an initialization sequence for allowing the peripheral and software settable interrupt reque sts to cause an interrupt request to the processor is: interrupt_request_initialization: configure vtes and hven in intc_mcr configure vtba in intc_iackr raise the pri n fields in intc_psr n set the enable bits or clear the mask bits for the peripheral interrupt requests lower pri in intc_cpr to zero enable processor recognition of interrupts 18.7.2 interrupt exception handler these example interrupt exception handlers use power architecture assembly code. 0 108 0 1 0 clock interrupt request to processor hardware vector enable interrupt vector interrupt acknowledge read intc_iackr write intc_eoir intvec in intc_iackr pri in intc_cpr peripheral interrupt request 100 0 108
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 333 18.7.2.1 software vector mode interrupt_exception_handler: code to create stack frame, save working register, and save srr0 and srr1 lis r3,intc_iackr@ha # form adjusted upper half of intc_iackr address lwz r3,intc_iackr@l(r3) # load intc_iackr, which clears request to processor lwz r3,0x0(r3) # load address of isr from vector table wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi mtlr r3 # move intc_iackr contents into link register blrl # branch to isr; link register updated with epilog # address epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi vector_table_base_address: address of isr for interrupt with vector 0 address of isr for interrupt with vector 1 . . . address of isr for interrupt with vector 510 address of isr for interrupt with vector 511 isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # return to epilog 18.7.2.2 hardware vector mode this interrupt exception handler is useful with processor and system bus implementations that support a hardware vector. this example assume s that each interrupt_exception_handler x only has space for four instructions, and therefore a branch to interrupt_exception_handler_continued x is needed. interrupt_exception_handler x : b interrupt_exception_handler_continued x # 4 instructions available, branch to continue
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 334 freescale semiconductor interrupt_exception_handler_continued x : code to create stack frame, save working register, and save srr0 and srr1 wrteei 1 # enable processor recognition of interrupts code to save rest of context required by e500 eabi bl isr x # branch to isr for interrupt with vector x epilog: code to restore most of context required by e500 eabi # popping the lifo after the restoration of most of the context and the disabling of processor # recognition of interrupts eases the calculation of the maximum stack depth at the cost of # postponing the servicing of the next interrupt request. mbar # ensure store to clear flag bit has completed lis r3,intc_eoir@ha # form adjusted upper half of intc_eoir address li r4,0x0 # form 0 to write to intc_eoir wrteei 0 # disable processor recognition of interrupts stw r4,intc_eoir@l(r3) # store to intc_eoir, informing intc to lower priority code to restore srr0 and srr1, restore working registers, and delete stack frame rfi isr x : code to service the interrupt event code to clear flag bit which drives interrupt request to intc blr # branch to epilog 18.7.3 isr, rtos, and task hierarchy the rtos and all of the tasks under it s control typically execute with pri in intc current priority register (intc_cpr) having a value of 0. the rtos will execute the tasks accord ing to whatever priority scheme that it may have, but that priority scheme is independent and has a lo wer priority of execution than the priority scheme of the intc. in other words, the isrs execute above intc_cpr priority 0 and outside the control of the rtos, the rtos executes at in tc_cpr priority 0, and while the tasks execute at different priorities under the control of the rtos , they also execute at intc_cpr priority 0. if a task shares a resource with an isr and the pcp is being used to mana ge that shared resource, then the task?s priority can be elevated in the intc _cpr while the shared resource is being accessed. an isr whose pri n in intc priority select registers (intc_psr0?intc_psr 233) has a value of 0 will not cause an interrupt request to the processor, even if its peripheral or software settable interrupt request is asserted. for a peripheral interrupt request, not setting its enable bit or disabling the mask bit will cause it to remain negated, which conseque ntly also will not cause an interrupt request to the processor. since the isrs are outside the control of the rtos, this isr will not run unless called by another isr or the interrupt exception handler, perh aps after executing another isr.
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 335 18.7.4 order of execution an isr with a higher priority can pr eempt an isr with a lower priority , regardless of the unique vectors associated with each of their periphe ral or software configur able interrupt requests. however, if multiple peripheral or software configurable interrupt requests are asserted, more than one has the highest priority, and that priority is high enough to cause preemption, the intc selects the one with the lowest unique vector regardless of the order in time that they assert ed. however, the ability to meet deadlines with this scheduling scheme is no less than if the isrs execute in the time order that their peripheral or software configurable interrupt requests asserted. the example in table 18-11 shows the order of execution of both is rs with different priorities and the same priority. table 18-11. order of isr execution example step no. step description code executing at end of step pri in intc_cpr at end of step rtos isr108 1 1 isr108 executes for peripheral interrupt request 100 because th e first eight isrs are for software configurable interrupt requests. isr208 isr308 isr408 interrupt exception handler 1 rtos at priority 0 is executing. x 0 2 peripheral interrupt request 100 at priority 1 asserts. interrupt taken. x1 3 peripheral interrupt request 400 at priority 4 is asserts. interrupt taken. x4 4 peripheral interrupt request 300 at priority 3 is asserts. x4 5 peripheral interrupt request 200 at priority 3 is asserts. x4 6 isr408 completes. interrupt exception handler writes to intc_eoir. x1 7 interrupt taken. isr208 starts to execute, even though peripheral interrupt request 300 asserted first. x3 8 isr208 completes. interrupt exception handler writes to intc_eoir. x1 9 interrupt taken. isr308 starts to execute. x 3 10 isr308 completes. interrupt exception handler writes to intc_eoir. x1 11 isr108 completes. interrupt exception handler writes to intc_eoir. x0 12 rtos continues execution. x 0
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 336 freescale semiconductor 18.7.5 priority ceiling protocol 18.7.5.1 elevating priority the pri field in intc_cpr is elevated in the osek pcp to the ceiling of all of the priorities of the isrs that share a resource. this protocol allows coherent accesses of the isrs to that shared resource. for example, isr1 has a priority of 1, isr2 has a priority of 2, and is r3 has a priority of 3. they share the same resource. before isr1 or isr2 can access that resource, they must raise the pri value in intc_cpr to 3, the ceiling of all of the isr priorities. after they rel ease the resource, the pri value in intc_cpr can be lowered. if they do not raise thei r priority, isr2 can preempt isr1, and isr3 can preempt isr1 or isr2, possibly co rrupting the shared resource. anot her possible failure mechanism is deadlock if the higher priority isr needs the lower pr iority isr to release the resource before it can continue, but the lower priority isr cannot release the resource until th e higher priority isr completes and execution returns to the lower priority isr. using the pcp instead of disabli ng processor recognition of all inte rrupts eliminates the time when accessing a shared resource that all higher priority interrupts are blocked. for ex ample, while isr3 cannot preempt isr1 while it is accessing the shared resource, all of the isrs with a priority higher than 3 can preempt isr1. 18.7.5.2 ensuring coherency a scenario can cause non-coherent accesses to the shared resource. fo r example, isr1 and isr2 are both running on the same core and both shar e a resource. isr1 has a lower prio rity than isr2. isr1 is executing and writes to the intc_cpr. the instru ction following this store is a stor e to a value in a shared coherent data block. either immediately before or at the same time as the first st ore, the intc asse rts the interrupt request to the processor be cause the peripheral interrupt request for isr2 has asse rted. as the processor is responding to the interrupt request from the intc, a nd as it is aborting tran sactions and flushing its pipeline, it is possible that both stor es will be executed. isr2 thereby th inks that it can access the data block coherently, but the data block has been corrupted. osek uses the getresource and rele aseresource system services to mana ge access to a shared resource. to prevent corruption of a coherent data block, modifications to pri in intc_cpr can be made by those system services with the code sequence: disable processor recognition of interrupts pri modification enable processor recognition of interrupts 18.7.6 selecting priorities accordi ng to request ra tes and deadlines the selection of the priorities for the isrs can be made using rate monotonic scheduling (rms) or a superset of it, deadline monotonic sc heduling (dms). in rms, the isrs th at have higher request rates have higher priorities. in dms, if the d eadline is before the next time th e isr is requested, then the isr is assigned a priority according to the time from the request for the isr to the deadline, not from the time of the request for the isr to the next request for it.
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 337 for example, isr1 executes every 100 s, isr2 executes every 200 s , and isr3 executes every 300 s. isr1 has a higher priority than isr, 2 which has a higher priority than isr3; however, if isr3 has a deadline of 150 s, then it has a higher priority than isr2. the intc has 16 priorities, which may be less than the number of isrs. in this case, the isrs should be grouped with other isrs that have si milar deadlines. for example, a prio rity could be allocated for every time the request rate doubles. isrs wi th request rates around 1 ms would sh are a priority, is rs with request rates around 500 s would share a pr iority, isrs with request rates around 250 s would share a priority, etc. with this approach, a ra nge of isr reque st rates of 2 16 could be included, rega rdless of the number of isrs. reducing the number of priorities reduc es the processor?s ability to meet its deadlines. however, reducing the number of priorities can reduce the size and latency through the in terrupt controller. it also allows easier management of isrs with si milar deadlines that share a resource. they do not need to use the pcp to access the shared resource. 18.7.7 software configur able interrupt requests the software configurable interrupt requests can be used in two ways. they can be used to schedule a lower priority portion of an isr, and they may also be used by processors to interrupt other processors in a multiple processor system. 18.7.7.1 scheduling a lower pr iority portion of an isr a portion of an isr needs to be executed at the pri x value in the intc priority select registers (intc_psr0_3?intc_psr232_233), which becomes the pr i value in intc_cpr with the interrupt acknowledge. the isr, however, can ha ve a portion that does not need to be executed at this higher priority. therefore, executi ng the later portion that does not need to be executed at this higher priority can prevent the execution of isrs that do not have a higher priority than the earlier portion of the isr, but do have a higher priority than what the later portion of the isr needs. this preemp tive scheduling inefficiency reduces the processor?s abi lity to meet its deadlines. one option is for the isr to complete the earlier higher priority portion, but then schedule through the rtos a task to execute the later lower priority por tion. however, some rtoss can require a large amount of time for an isr to schedule a task. therefore, a second option is fo r the isr, after co mpleting the higher priority portion, to set a set x bit in intc_sscir0_3?intc_sscir4_7. writing a 1 to set x causes a software configurable interrupt reque st. this software configurable in terrupt request will usually have a lower pri x value in the intc_psr x _ x and will not cause preemptive scheduling inefficiencies. after generating a software settable interru pt request, the higher priority isr completes. the lower priority isr is scheduled according to its priority. execution of the higher priority isr is not resumed after the completion of the lower priority isr. 18.7.7.2 scheduling an is r on another processor because the set x bits in the intc_sscir x _ x are memory mapped, processors in multiple-processor systems can schedule isrs on the other processors. one applicatio n is that one processor wants to command another processor to perform a piece of work and the initia ting processor does not need to use
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 338 freescale semiconductor the results of that work. if the in itiating processor is concerned that the processor execut ing the software configurable isr has not completed the work before asking it to again execute the isr, it can check if the corresponding clr x bit in intc_sscir x _ x is asserted before again writing a 1 to the set x bit. another application is the sharing of a block of data. for example, a first processor has completed accessing a block of data and wants a second processo r to then access it. furt hermore, after the second processor has completed accessing th e block of data, the first proce ssor again wants to access it. the accesses to the block of data must be done coherently. to do this, the first processo r writes a 1 to a set x bit on the second processor. after accessing the bl ock of data, the second processor clears the corresponding clr x bit and then writes 1 to a set x bit on the first processor, in forming it that it can now access the block of data. 18.7.8 lowering priority within an isr a common method for avoiding preemptive scheduling inefficiencies with an isr whose work spans multiple priorities (see section 18.7.7.1, scheduling a lower priority portion of an isr) is to lower the current priority. however, the intc has a lifo whose depth is determ ined by the number of priorities. note lowering the pri value in intc_cpr within an isr to below the isr?s corresponding pri value in the in tc priority select registers (intc_psr0_3?intc_psr232_233) allows more preemptions than the lifo depth can support. therefore, the intc does not support lowering the current pr iority within an isr as a way to avoid preemptive scheduling inefficiencies. 18.7.9 negating an interrupt request outside of its isr 18.7.9.1 negating an interrupt request as a side effect of an isr some peripherals have flag bits that can be cleared as a side effect of servicing a peripheral interrupt request. for example, reading a spec ific register can clear the flag bits and their corresponding interrupt requests. this clearing as a side effect of servicing a peripheral in terrupt request can cause the negation of other peripheral interrupt requests besides the peripheral interrupt request whose isr presently is executing. this negating of a periphe ral interrupt request outside of its isr can be a desired effect. 18.7.9.2 negating multiple in terrupt requests in one isr an isr can clear other flag bits besi des its own. one reason that an isr cl ears multiple flag bits is because it serviced those flag bits, and therefore the isrs for these flag bits do not need to be executed. 18.7.9.3 proper setting of interrupt request priority whether an interrupt request negates outside its own isr due to the side effect of an isr execution or the intentional clearing a flag bit, the pr iorities of the peripheral or software configurable interrupt requests for these other flag bits must be selected properly. their pri x values in the intc priority select registers
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 339 (intc_psr0_3?intc_psr232_233) must be se lected to be at or lower than the priority of the isr that cleared their flag bits. otherwise, t hose flag bits can cause the interrupt request to the processor to assert. furthermore, the clearing of these ot her flag bits also has the same ti ming relationship to the writing to intc_sscir0_3?intc_sscir4_7 as the clearing of the flag bit that caused the present isr to be executed (see section 18.6.3.1.2, end of inte rrupt exception handler ). a flag bit whose enable bit or mask bit negates its peripheral interrupt request can be clea red at any time, regardless of the periphera l interrupt request?s pri x value in intc_psr x _ x . 18.7.10 examining lifo contents in normal mode, the user does not need to know the contents of the lifo. he may not even know how deeply the lifo is nested. however, if he wants to read the contents, such as in debug mode, they are not memory mapped. the contents can be read by popping the lifo and reading the pri field in either intc_cpr. the code sequence is: pop_lifo: store to intc_eoir load intc_cpr, examine pri, and store onto stack if pri is not zero or value when interrupts were enabled, branch to pop_lifo when the examination is complete, the lifo can be restored using this code sequence: push_lifo: load stacked pri value and store to intc_cpr load intc_iackr if stacked pri values are not depleted, branch to push_lifo
chapter 18 interrupt controller (intc) MPC5606BK microcontroller reference manual, rev. 2 340 freescale semiconductor this page is intent ionally left blank.
chapter 19 crossbar switch (xbar) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 341 chapter 19 crossbar switch (xbar) 19.1 introduction this chapter describes the multi-por t crossbar switch (xbar), which supports simultane ous connections between three master ports and three slave ports. xb ar supports a 32-bit addres s bus width and a 32-bit data bus width at all master and slave ports. the crossbar of MPC5606BK is the same as the one of all other ppc55 xx and ppc56 xx products except that it cannot be configured by software a nd that it has a hard-wired configuration. 19.2 block diagram figure 19-1 shows a block diagram of the crossbar switch. figure 19-1. xbar block diagram table 19-1 gives the crossbar switch port for each master and slave, and the assigned and fixed id number for each master. the table shows the master id num bers as they relate to the master port numbers. table 19-1. xbar switch ports for MPC5606BK module port physical master id type logical number e200z0 core?cpu instructions master 0 0 e200z0 core?cpu data master 1 0 edma master 2 1 flash memory slave 0 ? internal sram slave 2 ? peripheral bridges slave 7 ? cpu crossbar switch flash master modules slave modules cpu data internal peripheral bridges instructions memory sram edma
chapter 19 crossbar switch (xbar) MPC5606BK microcontroller reference manual, rev. 2 342 freescale semiconductor 19.3 overview the xbar allows for concurre nt transactions to occur fr om any master port to any slave port. it is possible for all master ports and slave ports to be in use at the same time as a re sult of independent master requests. if a slave port is simultaneously requested by more th an one master port, arbitrat ion logic selects the higher priority master and grants it owne rship of the slave port. all other ma sters requesting that slave port are stalled until the higher priority ma ster completes its transactions. requesting masters are granted access based on a fixed priority. 19.4 features ? three master ports: ? core: e200z0 core instructions ? core: e200z0 core data ?edma ? three slave ports ? flash (refer to chapter 30, flash memory , for information on accessing flash memory) ? internal sram ? peripheral bridges ? 32-bit address, 32-bit data paths ? fully concurrent transfers betwee n independent master and slave ports ? fixed priority scheme and fixed parking strategy 19.5 modes of operation 19.5.1 normal mode in normal mode, the xbar provides the logic th at controls crossbar switch configuration. 19.5.2 debug mode the xbar operation in debug mode is identical to operation in normal mode. 19.6 functional description this section describes the functiona lity of the xbar in more detail. 19.6.1 overview the main goal of the xbar is to increase overall system performance by allowing multiple masters to communicate concurrently with mult iple slaves. to maximize data th roughput, it is esse ntial to keep arbitration delays to a minimum.
chapter 19 crossbar switch (xbar) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 343 this section examines data throughput from the point of view of mast ers and slaves, detailing when the xbar stalls masters, or in serts bubbles on the slave side. 19.6.2 general operation when a master makes an access to the xbar from an idle master state, the access is taken immediately by the xbar. if the targeted slave por t of the access is availabl e (that is, the requesting master is currently granted ownership of the slave port), the access is immediately presented on the slave port. it is possible to make single clock (zero wait state) accesses through the xbar by a granted master . if the targeted slave port of the access is busy or parked on a different master port, the reques ting master receives wait states until the targeted slave port can se rvice the master request. the latenc y in servicing the request depends on each master?s priority level a nd the responding slave?s access time. because the xbar appears to be simply another slav e to the master device, the master device has no indication that it owns the slave port it is targeting. while the master doe s not have control of the slave port it is targeting, it is wait-stated. a master is given control of a targ eted slave port only after a previous access to a different slave port has completed, regardless of its priority on the newly targeted slave port. this prevents deadlock from occurring when a master has the following conditions: ? outstanding request to slave por t a that has a long response time ? pending access to a different slave port b ? lower priority master also makes a request to the different slave port b. in this case, the lower priority mast er is granted bus owners hip of slave port b after a cycle of arbitration, assuming the higher priority master sl ave port a access is not terminated. after a master has control of the slav e port it is targeting, the master re mains in control of that slave port until it gives up the slave port by running an idle cycle, leaves that slave port for its next access, or loses control of the slave port to a higher pr iority master with a request to the same slave port. however, because all masters run a fixed-length burst transfer to a slave port, it retain s control of the slave port until that transfer sequence is completed. when a slave bus is idled by the xbar, it is pa rked on the master that did the last transfer. 19.6.3 master ports a master access is taken if the slave port to which the access decodes is either currently servicing the master or is parked on the master. in this case, the xbar is completely transpar ent and the master access is immediately transmitted on the slave bus and no arbitr ation delays are incurred. a master access stall if the access decodes to a slave port that is busy serving another master, parked on another master. if the slave port is currently parked on another master , and no other master is re questing access to the slave port, then only one clock of arbitrati on is incurred. if the slave port is currently serving another master of a lower priority and the master has a higher priority than all other requesting masters, then the master gains control over the slave port as soon as the data phase of the current access is completed. if the slave port is currently servicing another ma ster of a higher priority, then the mast er gains control of the slave port after
chapter 19 crossbar switch (xbar) MPC5606BK microcontroller reference manual, rev. 2 344 freescale semiconductor the other master releases control of the slave port if no other higher priority master is also waiting for the slave port. a master access is responded to with an error if th e access decodes to a locati on not occupied by a slave port. this is the only time the xbar directly responds with an error response. all other error responses received by the master are the result of error responses on the slave por ts being passed through the xbar. 19.6.4 slave ports the goal of the xbar with respect to the slave ports is to keep them 100% sa turated when masters are actively making requests. to do this the xbar must not insert any bubbles onto the slave bus unless absolutely necessary. there is only one instance when the xbar forces a bubble onto the slave bus when a master is actively making a request. this occurs when a handoff of bus ownership occurs and there are no wait states from the slave port. a requesting master that does not own the slave port is granted access after a one clock delay. 19.6.5 priority assignment each master port is assigned a fixe d 3-bit priority level (hard-wired priority). the following table shows the priority levels assigned to each ma ster (the lowest ha s highest priority). 19.6.6 arbitration xbar supports only a fixed-pr iority comparison algorithm. 19.6.6.1 fixed priority operation when operating in fixed-priority arbi tration mode, each master is assi gned a unique priority level in the xbar_mpr. if two masters both request access to a slave port, the master with the higher priority in the selected priority register ga ins control over the slave port. any time a master makes a request to a slave port, the slave port ch ecks to see if the new requesting master?s priority level is higher than that of the master that currently has control over the slave port (if any). the slave port does an arbitration check at every clock edge to ensure that the proper master (if any) has control of the slave port. table 19-2. hardwired bus master priorities module port priority level type master # e200z0 core?cpu instructions master 0 7 e200z0 core?cpu data master 1 6 edma master 2 5
chapter 19 crossbar switch (xbar) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 345 if the new requesting master?s priority level is higher than th at of the master that currently has control of the slave port, the higher priority master is grante d control at the terminati on of any currently pending access, assuming the pending transfer is not part of a burst transfer. a new requesting master must wait until the end of th e fixed-length burst transfer, before it is granted control of the slave port. but if the new requesting master ?s priority level is lower than that of the master that currently has control of the slav e port, the new requesting master is fo rced to wait until the master that currently has control of the slave port is finished accessing the current slave port. 19.6.6.1.1 parking if no master is currently requesting the slave port, the slave port is parked. the slave por t parks always to the last master (park-on-last). when parked on the last master, the slave port is passing that master?s signals through to the slave bus. when the ma ster accesses the slave port again, no other arbitration penalties are incurred except that a one clock arbitration penalt y is incurred for each access request to the slave port made by another master port. all ot her masters pay a one clock penalty.
chapter 19 crossbar switch (xbar) MPC5606BK microcontroller reference manual, rev. 2 346 freescale semiconductor this page is intent ionally left blank.
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 347 chapter 20 system integration unit lite (siul) 20.1 introduction this chapter describes the system integration unit lite (siul), which manages the pads and their configuration. it controls th e multiplexing of the alternate functions used on all pads and is responsible for the management of the extern al interrupts to the device. 20.2 overview the system integration unit lite (siul) contro ls the mcu pad configuration, ports, general-purpose input and output (gpio) signals, and external interrupts with trigge r event configuration. figure 20-1 provides a block diagram of the siul and its interfaces to othe r system components. the module provides the capability to configure, read, and wr ite to the device?s ge neral-purpose i/o pads that can be configured as either inputs or outputs. ? when a pad is configured as an input, the state of the pad (logic high or lo w) is obtained by reading an associated data input register. ? when a pad is configured as an output, the valu e driven onto the pad is determined by writing to an associated data output regist er. enabling the input buffers when a pad is configured as an output allows the actual state of the pad to be read. ? to enable monitoring of an output pad value, the pad can be configured as both output and input so the actual pad value can be read back and compared with the expected value.
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 348 freescale semiconductor figure 20-1. system integration unit lite block diagram ips bus data pad input io interrupt interrupt controller ips master ? configuration ? glitch filter pad config (iomuxc) pad cfg (pcrs) gpio functionality 149 (1) 149 (1) 149 (1) 24 (2) 3 mux pads 149 (1) siul module interrupt functionality notes: 1 149 gpios in 176-pin lqfp and 208 bga, as many as 121 gpios in 144-pin lqfp and as many as 77 gpios in 100-pin lqfp 2 24 eirqs in 144-pin lqfp, 176-pin lqfp and 208 bga; as many as 20 eirqs in 100-pin lqfp
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 349 20.3 features the system integration unit lite supports these distinctive features: ?gpio ? gpio function on as many as 149 i/o pins ? dedicated input and output registers for most gpio pins 1 ? external interrupts ? three interrupt vectors dedica ted to 24 external interrupts ? 24 programmable digi tal glitch filters ? independent interrupt mask ? edge detection ? system configuration ? pad configuration control 20.4 external signal description most device pads support multiple device functions. pad configuration registers are provided to enable selection between gpio and other signals. these other si gnals, also referred to as alternate functions, are typically peripheral functions. gpio pads are grouped in ports, with each port cont aining as many as 16 pads. with appropriate configuration, all pins in a port can be read or written to in parallel with a single r/w access. note in order to use gpio port functionalit y, all pads in the port must be configured as gpio rather than as alternate functions. table 20-1 lists the external pins configurable via the siul. ( 1.some device pins, e.g., analog pins, do no t have both input and output functionality. table 20-1. siul signal properties gpio[0:148] category name i/o direction function system configuration gpio[0:148] 1 1 gpio[0?26], gpio[28?59], and gpio[61?122] in 144- pin lqfp; gpio[0?26], gpi o[28?59], gpio[61?76], and gpio[121?122] in 100-pin lqfp i/o 2 2 most, but not all gpio pads can be configured as inputs or outputs but some, e.g., analog pins with gpio function, are only configurable as inputs. general-purpose input/output external interrupt pa[3], pa[6:8], pa[11:12], pa[14], pc[2:5], pc[12], pc[14:15], pe[2], pe[4], pe[6:7], pe[10], pe[12], pe[14], pf[15], pg[1], pg[8] 3 3 pe[14], pf[15], pg[1], and pg[8] not available in 100-pin lqfp input pins with external interrupt request functionality. please see chapter 4, signal description , for details.
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 350 freescale semiconductor 20.4.1 detailed signal descriptions 20.4.1.1 general-purpose i/o pins (gpio[0:148]) 1 the gpio pins provide general-purpose input and output functions. the gpio pins are generally multiplexed with other i/o pin functions. each gpio input and output is separately cont rolled by an input (gpdi n_n ) or output (gpdo n_n ) register. 20.4.1.2 external interrupt requ est input pins (eirq[0:23]) 2 the eirq[0:23] pins are connected to the siul inpu ts. rising- or falling-edge events are enabled by setting the corresponding bits in the siul _ireer or the siul _ifeer register. 1. gpio[0?26], gpio[28?59], and gpio[61?122] in 144-p in lqfp; gpio[0?26], gpio[ 28?59], gpio[61?76], and gpio[121?122] in 100-pin lqfp 2. eirq[0:11] plus eirq[16:23] in 100-pin lqfp
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 351 20.5 memory map and register description this section provides a detailed description of all registers accessibl e in the siul module. 20.5.1 siul memory map table 20-2 gives an overview of the siul registers implemented. table 20-2. siul memory map base address: 0xc3f9_0000 address offset register location 0x0000 reserved 0x0004 mcu id register #1 (midr1) on page 353 0x0008 mcu id register #2 (midr2) on page 354 0x000c?0x0013 reserved 0x0014 interrupt status flag register (isr) on page 355 0x0018 interrupt request enable register (irer) on page 356 0x001c?0x00 reserved 0x0028 interrupt rising-edge event enable register (ireer) on page 356 0x002c interrupt falling-edge event enable register (ifeer) on page 357 0x0030 interrupt filter enable register (ifer) on page 358 0x0034?0x003f reserved 0x0040?0x0168 pad configuration registers (pcr0?pcr148) 1 on page 359 0x016a?0x04ff reserved 0x0500?0x053c pad selection for multiplexed inputs registers (psmi0_3?psmi60_63) on page 361 0x0540?0x05ff reserved 0x0600?0x06a0 gpio pad data output registers (gpdo0_3?gpdo148_151) 2 on page 366 0x06a4?0x07ff reserved 0x0800?0x08a0 gpio pad data input registers (gpdi0_3?gpdi148_151) 3 on page 367 0x08a4?0x0bff reserved 0x0c00?0x0c10 parallel gpio pad data out registers (pgpdo0 ? pgpdo4) on page 367 0x0c14?0x0c3f reserved 0x0c40?0x0c50 parallel gpio pad da ta in registers (pgpdi0 ? pgpdi4) on page 368 0x0c54?0x0c7f reserved 0x0c80?0x0ca4 masked parallel gpio pad data out register (mpgpdo0?mpgpdo9) on page 369 0x0ca8?0x0fff reserved
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 352 freescale semiconductor note a transfer error will be issued when trying to access completely reserved register space. 20.5.2 register protection individual registers in system inte gration unit lite can be protecte d from accidental writes using the register protection module. the foll owing registers can be protected: ? interrupt request en able register (irer) ? interrupt rising-edge even t enable register (ireer) ? interrupt falling-edge even t enable register (ifeer) ? interrupt filter enab le register (ifer), ? pad configuration registers (pcr0?pcr148). note that only th e following registers can be protected: ? pcr[0:15] (port a) ? pcr[16:19] (port b[0:3]) ? pcr[34:47] (port c[2:15]) ? pad selection for multiplexed inputs registers (psmi0_3?psmi60_63) ? interrupt filter maximum count er registers (ifmc0?ifmc23). no te that only ifmc[0:15] can be protected. ? interrupt filter clock pr escaler register (ifcpr) see chapter 32, register protection , for more details. 0x1000?0x105c interrupt filter maximu m counter registers (ifmc0?ifmc23) 4 on page 371 0x1060?0x107c reserved 0x1080 interrupt filter clock prescaler register (ifcpr) on page 371 0x1084?0x3fff reserved 1 pcr0?26, pcr28?59, and pcr61?122 in 144-pin lqfp; pcr0?26, pcr28?59, pcr61?76, and pcr121?122 in 100-pin lqfp?all remaining registers are reserved. 2 gpdo0?26, gpdo28?59, and gpdo61?122 in 144-pin lqfp; gpdo0?26, gpdo28?59, gpdo61?76, and gpdo121?122 in 100-pin lqfp?all remaining registers are reserved. 3 gpdi0?26, gpdi28?59, and gpdi61?122 in 144-pi n lqfp; gpdi0?26, gp di28?59, gpdi61?76, and gpdi121?122 in 100-pin lqfp?all remaining registers are reserved. 4 ifmc0?11 plus ifmc16?23 in 100-pin lqfp ?all remaining registers are reserved. table 20-2. siul memory map (continued) base address: 0xc3f9_0000 address offset register location
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 353 20.5.3 register descriptions 20.5.3.1 mcu id register #1 (midr1) this register holds identificat ion information about the device. offset: 0x0004 access: read 0123456789101112131415 r partnum[15:0] w reset0101011000000100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r csp pkg 0 0 major_mask minor_mask w reset0011010000000000 figure 20-2. mcu id register #1 (midr1) table 20-3. midr1 field descriptions field description partnum[15:0] mcu part number, lower 16 bits device part number of the mcu. 0101_0110_0000_0001:128 kb 0101_0110_0000_0010: 256 kb 0101_0110_0000_0011: 320/384 kb 0101_0110_0000_0100: 512 kb 0101_0110_0000_0101: 768 kb 0101_0110_0000_0110: 1 mb 0101_0110_0000_0111: 1.5 mb for the full part number this field needs to be combined with midr2[partnum[23:16]]. csp always reads back 0 pkg package settings can be read by software to determine the package ty pe that is used for the particular device as described below. any values not explicitly specified are reserved. 0b01001: 100-pin lqfp 0b01101: 144-pin lqfp 0b10000: 208 bga 0b10001: 176-pin lqfp major_mask major mask revision counter starting at 0x0. incremented each time there is a resynthesis. minor_mask minor mask revision counter starting at 0x0. incremented each time a mask change is done.
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 354 freescale semiconductor 20.5.3.2 mcu id register #2 (midr2) 20.5.3.3 interrupt status flag register (isr) this register holds the interrupt flags. offset: 0x0008 access: read 0123456789101112131415 r sf flash_size_1 flash_size_2 0 0 0 0 0 0 0 w reset0010100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r partnum[23:16] 0 0 0 ee 0 0 0 0 w reset01000010/100010 1 1 static bit fixed in hardware 0 1 0 1 0 figure 20-3. mcu id register #2 (midr2) table 20-4. midr2 field descriptions field description sf manufacturer 0 freescale 1 reserved flash_size_1 coarse granularity for flash memory size total flash memory size = flash_size_1 + flash_size_2 0011 128 kb 0100 256 kb 0101 512 kb 0110 1 mb flash_size_2 fine granularity for flash memory size total flash memory size = flash_size_1 + flash_size_2 0000 0 (flash_size_1 / 8) 0010 2 (flash_size_1 / 8) 0100 4 (flash_size_1 / 8) pa rt n u m [23:16] mcu part number, upper 8 bits containing the ascii character within the mcu part number 0x42: character b (body controller) 0x43: character c (gateway) for the full part number this field needs to be combined with midr1[partnum[15:0]]. ee data flash present 0 no data flash is present 1 data flash is present
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 355 offset: 0x0014 access: user read/write 0123456789101112131415 r00000000 eif[23:16] 1 1 20 flags in 100-pin lqfp: eif[23:16] plus eif[11:0] (register bits 16?19 reserved). w w1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eif[15:0] 1 ww1c reset0000000000000000 figure 20-4. interrupt status flag register (isr) table 20-5. isr field descriptions field description eif[x] external interrupt status flag x this flag can be cleared only by writing a 1. writin g a 0 has no effect. if e nabled (irer[x]), eif[x] causes an interrupt request. 0 no interrupt event has occurred on the pad 1 an interrupt event as defined by ireer[x] and ifeer[x] has occurred
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 356 freescale semiconductor 20.5.3.4 interrupt request enable register (irer) this register is used to enable the inte rrupt messaging to the interrupt controller. 20.5.3.5 interrupt rising-edge event enable register (ireer) this register is used to enab le rising-edge triggered events on the corresponding interrupt pads. offset: 0x0018 access: user read/write 0123456789101112131415 r00000000 ire[23:16] 1 1 20 enable requests in 100-pin lqfp: ire[23:16] plus ire[11:0] (register bits 16?19 reserved). w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ire[15:0] 1 w reset0000000000000000 figure 20-5. interrupt request enable register (irer) table 20-6. irer field descriptions field description ire[x] external interrupt request enable x 0 interrupt requests from the corres ponding isr[eif[x]] bit are disabled. 1 interrupt requests from the corr esponding isr[eif[x]] bit are enabled. offset:0x0028 access: user read/write 0123456789101112131415 r00000000 iree[23:16] 1 1 20 enable events in 100-pin lqfp: iree[23:16] pl us iree[11:0] (register bits 16?19 reserved). w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r iree[15:0] 1 w reset0000000000000000 figure 20-6. interrupt rising-edge event enable register (ireer)
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 357 20.5.3.6 interrupt falling-edge ev ent enable register (ifeer) this register is used to enable falling-edge triggered events on the corresponding interrupt pads. note if both the ireer[iree] and ifeer[if ee] bits are cleared for the same interrupt source, the interrupt status flag for the corresponding external interrupt will never be set. if ireer [iree] and ifeer[ifee] bits are set for the same source the interrupts are triggered by both ri sing edge events and falling edge events. table 20-7. ireer field descriptions field description iree[x] enable rising-edge events to cause the isr[eif[x]] bit to be set. 0 rising-edge event is disabled 1 rising-edge event is enabled offset:0x002c access: user read/write 0123456789101112131415 r00000000 ifee[23:16] 1 1 20 enabling events in 100-pin lqfp: ifee[23:16] plus ifee[11:0] (register bits 16?19 reserved). w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ifee[15:0] 1 w reset0000000000000000 figure 20-7. interrupt falling-edge event enable register (ifeer) table 20-8. ifeer field descriptions field description ifee[x] enable falling-edge events to cause the isr[eif[x]] bit to be set. 0 falling-edge event is disabled 1 falling-edge event is enabled
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 358 freescale semiconductor 20.5.3.7 interrupt filter enable register (ifer) this register is used to enable a digital filter counter on the corresponding inte rrupt pads to filter out glitches on the inputs. 20.5.3.8 pad configuration registers (pcr0?pcr148) the pad configuration regist ers allow configuration of the static electrical and functional characteristics associated with i/o pads. each pcr cont rols the characteristics of a single pad. please note that input and outpu t peripheral muxing are separate. ? for output pads: ? select the appropriate alternate func tion in pad config register (pcr) ? obe is not required for functions other than gpio ? for input pads: ? select the feature locat ion from psmi register ? set the ibe bit in the appropriate pcr ? for normal gpio (not alternate function): ? configure pcr ? read from gpdi or write to gpdo offset:0x0030 access: user read/write 0123456789101112131415 r00000000 ife[23:16] 1 1 20 bits in 100-pin lqfp: ife[23:16] plus ife[11:0] (register bits 16?19 reserved). w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ife[15:0] 1 w reset0000000000000000 figure 20-8. interrupt filter enable register (ifer) table 20-9. ifer field descriptions field description ife[x] enable digital glitch filter on the interrupt pad input 0 filter is disabled 1 filter is enabled see the ifmc field descriptions in ta b l e 2 0 - 2 0 for details on how the filter works.
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 359 note 16- and 32-bit accesses to the pcr x registers are supported. in addition to the bit map above, the following table 20-11 describes the pcr de pending on the pad type (pad types are defined in the ?pad t ypes? section of this reference manua l). the bits in shaded fields are not implemented for the particular i/o type. the pa field selecting the number of alternate functions may or may not be present depending on the number of alternate functions actually mapped on the pad. offsets: base + 0x0040 (pcr0)(149 registers) base + 0x0042 (pcr1) ... base + 0x0168 (pcr148) access: user read/write 0123456789101112131415 r0 smc apc pa[1:0] obe ibe 00 ode 00 src wpe wps w reset 0 0 1 1 smc and pa[1] are 1 for jtag pads 000 1 00 2 2 obe is 1 for tdo 0 3 3 ibe and wpe are 1 for tck, tms, tdi, fab, and abs 0000000 3 1 4 4 wps is 0 for input only pad with analog feature and fab figure 20-9. pad configuration registers (pcrx) table 20-10. pcr bit implementation by pad type pad type pcr bit no. 0123456789101112131415 s, m, f (pad with gpio and digital alternate function) smc apc pa[1:0] obe ibe ode src wpe wps pad with slew rate control smc apc pa[1:0] obe ibe ode src wpe wps j (pad with gpio and analog functionality) smc apc pa[1:0] obe ibe ode src wpe wps i (pad dedicated to adc) smc apc pa[1:0] obe ibe ode src wpe wps table 20-11. pcrx field descriptions field description smc safe mode control. this bit supports the overriding of the automatic d eactivation of the output buffer of the associated pad upon entering safe mode of the device. 0 in safe mode, the output buffer of the pad is disabled. 1 in safe mode, the output buffer remains functional.
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 360 freescale semiconductor 20.5.3.9 pad selection for multiplexe d inputs registers (psmi0_3?psmi60_63) in some cases, a peripheral input signal can be se lected from more than one pin. for example, the can1_rxd signal can be selected on three different pins: pc[3], pc[11], and pf[15]. only one can be active at a time. to select the pad to be used as input to the peripheral: apc analog pad control. this bit enables the usage of the pad as analog input. 0 analog input path from the pa d is gated and cannot be used 1 analog input path switch can be enabled by the adc pa[1:0] pad output assignment this field is used to select the function that is allowed to drive the output of a multiplexed pad. 00 alternative mode 0 ? gpio 01 alternative mode 1 ? see chapter 4, signal description 10 alternative mode 2 ? see chapter 4, signal description 11 alternative mode 3 ? see chapter 4, signal description note: number of bits depends on the actual number of actual alternate functions. please see data sheet. obe output buffer enable this bit enables the output buffer of the pad in case the pad is in gpio mode. 0 output buffer of the pad is disabled when pa[1:0] = 00 1 output buffer of the pad is enabled when pa[1:0] = 00 ibe input buffer enable this bit enables the input buffer of the pad. 0 input buffer of the pad is disabled 1 input buffer of the pad is enabled ode open drain output enable this bit controls output driver configuration for th e pads connected to this signal. either open drain or push/pull driver configurations can be selected. this feature applies to output pads only. 0 pad configured for push/pull output 1 pad configured for open drain src slew rate control this field controls the slew rate of the associated pad when it is slew rate selectable. its usage is the following: 0 pad configured as slow (default) 1 pad is configured as medium or fast (depending on the pad) note: pc[1] (tdo pad) is medium only. by default src = 0, and writing 1 has no effect. wpe weak pull up/down enable this bit controls whether the weak pull up/down devices are enabled/disabled for the pad connected to this signal. 0 weak pull device disabled for the pad 1 weak pull device enabled for the pad wps weak pull up/down select this bit controls whether weak pull up or weak pull down devices are used for the pads connected to this signal when weak pull up/down devices are enabled. 0 weak pulldown selected 1 weak pullup selected table 20-11. pcrx field descriptions (continued) field description
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 361 ? select the signal via the pad?s pcr register using the pa field. ? specify the pad to be used via the appropriate psmi field. in order to multiplex different pads to the same peripheral input, the siul provides a register that controls the selection between the different sources. offsets:0x0500?0x053c (16 regist ers) access: user read/write 0123456789101112131415 r0000 padsel0 0000 pa d s e l 1 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 padsel2 0000 pa d s e l 3 w reset0000000000000000 figure 20-10. pad selection for multiplexed inputs register (psmi0_3) table 20-12. psmi0_3 field descriptions field description padsel0?3, padsel4?7, ... padsel60?63 pad selection bits each padsel field selects th e pad currently used for a certain input function. see table 20-13 . table 20-13. peripheral input pin selection psmi registers padsel fields siul address offset function / peripheral mapping 1 psmi0_3 padsel0 0x500 can1rx / flexcan_1 00: pcr[35] 01: pcr[43] 10: pcr[95] 2 padsel1 0x501 can2rx / flexcan_2 00: pcr[73] 01: pcr[89] 2 padsel2 0x502 can3rx / flexcan_3 00: pcr[36] 01: pcr[73] 10: pcr[89] 2 padsel3 0x503 can4rx / flexcan_4 00: pcr[35] 01: pcr[43] 10: pcr[95] 2
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 362 freescale semiconductor psmi4_7 padsel4 0x504 can5rx / flexcan_5 00: pcr[64] 01: pcr[97] 2 padsel5 0x505 sck_0 / dspi_0 00: pcr[14] 01: pcr[15] padsel6 0x506 cs0_0 / dspi_0 00: pcr[14] 01: pcr[15] 10: pcr[27] 3 padsel7 0x507 sck_1 / dspi_1 00: pcr[34] 01: pcr[68] 10: pcr[114] 2 psmi8_11 padsel8 0x508 sin_1 / dspi_1 00: pcr[36] 01: pcr[66] 10: pcr[112] 2 padsel9 0x509 cs0_1 / dspi_1 00: pcr[] 01: pcr[61] 10: pcr[69] 11: pcr[115] 2 padsel10 0x50a sck_2 / dspi_2 00: pcr[46] 01: pcr[78] 2 10: pcr[105] 2 padsel11 0x50b sin_2 / dspi_2 00: pcr[44] 01: pcr[76] psmi12_15 padsel12 0x50c cs0_2 / dspi_2 00: pcr[47] 01: pcr[79] 2 10: pcr[82] 2 11: pcr[104] 2 padsel13 0x50d e1uc[3] / emios_0 00: pcr[3] 01: pcr[27] 3 10: pcr[40] padsel14 0x50e e0uc[4] / emios_0 00: pcr[4] 01: pcr[28] padsel15 0x50f e0uc[5] / emios_0 00: pcr[5] 01: pcr[29] psmi16_19 padsel16 0x510 e0uc[6] / emios_0 00: pcr[6] 01: pcr[30] padsel17 0x511 e0uc[7] / emios_0 00: pcr[7] 01: pcr[31] 10: pcr[41] padsel18 0x512 e0uc[10] / emios_0 00: pcr[10] 01: pcr[80] 2 padsel19 0x513 e0uc[11] / emios_0 00: pcr[11] 01: pcr[81] 2 table 20-13. peripheral input pin selection (continued) psmi registers padsel fields siul address offset function / peripheral mapping 1
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 363 psmi20_23 padsel20 0x514 e0uc[12] / emios_0 00: pcr[44] 01: pcr[82] 2 padsel21 0x515 e0uc[13] / emios_0 00: pcr[45] 01: pcr[83] 2 10: pcr[0] padsel22 0x516 e0uc[14] / emios_0 00: pcr[46] 01: pcr[84] 2 10: pcr[8] padsel23 0x517 e0uc[22] / emios_0 00: pcr[70] 01: pcr[72] 10: pcr[85] 2 psmi24_27 padsel24 0x518 e0uc[23] / emios_0 00: pcr[71] 01: pcr[73] 10: pcr[86] 2 padsel25 0x519 e0uc[24] / emios_0 00: pcr[60] 01: pcr[106] 2 10: pcr[75] padsel26 0x51a e0uc[25] / emios_0 00: pcr[61] 01: pcr[107] 2 padsel27 0x51b e0uc[26] / emios_0 00: pcr[62] 01: pcr[108] 2 psmi28_31 padsel28 0x51c e0uc[27] / emios_0 00: pcr[63] 01: pcr[109] 2 padsel29 0x51d scl / f_0 00: pcr[11] 01: pcr[19] padsel30 0x51e sda / i2c__0 00: pcr[10] 01: pcr[18] padsel31 0x51f lin3rx / linflex_3 00: pcr[8] 01: pcr[75] psmi32_35 padsel32 0x520 sck_3 / dspi_3 00: pcr[100] 2 01: pcr[124] 3 padsel33 0x521 sin_3 / dspi_3 00: pcr[101] 2 01: pcr[139] 3 padsel34 0x522 cs0_3 / dspi_3 00: pcr[99] 2 01: pcr[125] 3 10: pcr[140] 3 padsel35 0x523 sck_4 / dspi_4 00: pcr[109] 2 01: pcr[126] 3 10: pcr[133] 3 table 20-13. peripheral input pin selection (continued) psmi registers padsel fields siul address offset function / peripheral mapping 1
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 364 freescale semiconductor psmi36_39 padsel36 0x524 sin_4 / dspi_4reserved 00: pcr[106] 2 01: pcr[142] 3 ? padsel37 0x525 cs0_4 / dspi_4reserved 00: pcr[107] 2 01: pcr[123] 3 10: pcr[134] 3 11: pcr[143] 3 ? padsel38 0x526 e0uc[0] / emios_0 00: pcr[0] 01: pcr[14] padsel39 0x527 e0uc[1] / emios_0 00: pcr[1] 01: pcr[15] psmi40_43 padsel40 0x528 e0uc[28] / emios_0 00: pcr[12] 01: pcr[128] 3 padsel41 0x529 e0uc[29] / emios_0 00: pcr[13] 01: pcr[129] 3 padsel42 0x52a e0uc[30] / emios_0 00: pcr[16] 01: pcr[18] 10: pcr[130] 3 padsel43 0x52b e0uc[31] / emios0 00: pcr[17] 01: pcr[19] 10: pcr[131] 3 psmi44_47 padsel44 0x52c e1uc[1] / emios_1 00: pcr[111] 2 01: pcr[89] 2 padsel45 0x52d e1uc[2] / emios_1 00: pcr[112] 2 01: pcr[90] 2 padsel46 0x52e e1uc[3] / emios_1 00: pcr[113] 2 01: pcr[91] 2 padsel47 0x52f e1uc[4] / emios_1 00: pcr[114] 2 01: pcr[95] 2 psmi48_51 padsel48 0x530 e1uc[5] / emios_1 00: pcr[115] 2 01: pcr[123] 3 padsel49 0x531 e1uc[17] / emios_1 00: pcr[104] 2 01: pcr[127] 3 padsel50 0x532 e1uc[18] / emios_1 00: pcr[105] 2 01: pcr[148] padsel51 0x533 e1uc[25] / emios_1 00: pcr[92] 2 01: pcr[124] 3 table 20-13. peripheral input pin selection (continued) psmi registers padsel fields siul address offset function / peripheral mapping 1
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 365 20.5.3.10 gpio pad data output registers (gpdo0_3?gpdo148_151) these registers are used to set or cl ear gpio pads. each pad data out bit can be cont rolled separately with a byte access. psmi52_55 padsel52 0x534 e1uc[26] / emios_1 00: pcr[93] 2 01: pcr[125] 3 padsel53 0x535 e1uc[27] / emios_1 00: pcr[94] 2 01: pcr[126] 3 padsel54 0x536 e1uc[28] / emios_1 00: pcr[38] 01: pcr[132] 3 padsel55 0x537 e1uc[29] / emios_1 00: pcr[39] 01: pcr[133] 3 psmi56_59 padsel56 0x538 e1uc[30] / emios_1reserved 00: pcr[74] 01: pcr[103] 2 10: pcr[134] 3 ? padsel57 0x539 e1uc[31] / emios_1reserved 00: pcr[36] 01: pcr[106] 2 10: pcr[135] 3 ? padsel58 0x53a lin2rx / linflex _2 00: pcr[41] 01: pcr[11] padsel59 0x53b lin4rx / linflex _4reserved 00: pcr[6] 01: pcr[91] 2 ? psmi60_63 4 padsel60 0x53c lin5rx / linflex _5 00: pcr[4] 01: pcr[93] 2 padsel61 0x53d reserved padsel62 0x53e lin0rx/linflexd_0 00: pcr[19] 01: pcr[17] 1 see chapter 4, signal description , for correspondence between pcr and pinout 2 not available in 100-pin lqfp 3 available only in 176-pin lqfp and 208 bga packages 4 padsel63 not implemented table 20-13. peripheral input pin selection (continued) psmi registers padsel fields siul address offset function / peripheral mapping 1
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 366 freescale semiconductor caution toggling several ios at the same ti me can significantly increase the cu rrent in a pad group. caution must be taken to avoid exceeding maximum curr ent thresholds. please see data sheet. 20.5.3.11 gpio pad data input re gisters (gpdi0_3?gpdi148_151) these registers are used to read th e gpio pad data with a byte access. offsets: 0x0600?0x06a0 (38 regi sters) access: user read/write 0123456789101112131415 r0000000 pdo[0] 0000000 pdo[1] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 pdo[2] 0000000 pdo[3] w reset0000000000000000 figure 20-11. port gpio pad data output register 0?3 (gpdo0_3) table 20-14. gpdo0_3 field descriptions field description pdo[x] pad data out this bit stores the data to be driven out on the external gpio pad controlled by this register. 0 logic low value is driven on the corresponding gp io pad when the pad is configured as an output 1 logic high value is driven on the corresponding gpio pad when the pad is configured as an output
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 367 20.5.3.12 parallel gpio pad data out registers (pgpdo0 ? pgpdo4) MPC5606BK devices ports are constructed such th at they contain 16 gpio pins, for example porta[0..15]. parallel port registers for input (pgp di) and output (pgpdo) ar e provided to allow a complete port to be written or read in one ope ration, dependent on the indi vidual pad configuration. writing a parallel pgpdo register di rectly sets the associated gpdo regi ster bits. there is also a masked parallel port output register allo wing the user to determine which pins within a port are written. while very convenient and fast, this approach does ha ve implications regarding current consumption for the device power segment containing the port gpio pads . toggling several gpio pins simultaneously can significantly increase current consumption. caution caution must be taken to avoid ex ceeding maximum current thresholds when toggling multiple gpio pins si multaneously. please see data sheet. table 20-16 shows the locations and structure of the pgpdo x registers. offsets: 0x0800?0x08a0 (38 registers) access: user read 0123456789101112131415 r 0000000 pdi[0] 0000000 pdi[1] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 pdi[2] 0000000 pdi[3] w reset0000000000000000 figure 20-12. port gpio pad data input register 0?3 (gpdi0_3) table 20-15. gpdi0_3 field descriptions field description pdi[x] pad data in this bit stores the value of the external gpio pad associated with this register. 0 value of the data in signal for the corresponding gpio pad is logic low 1 value of the data in signal for the corresponding gpio pad is logic high
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 368 freescale semiconductor it is important to note the bit orderi ng of the ports in the parallel port regi sters. the most significant bit of the parallel port register corresponds to the least significant pin in the port. for example in table 20-16 , the pgpdo0 register contains fields for port a and port b. ? bit 0 is mapped to port a[0], bit 1 is mapped to port a[1] and so on, through bit 15, which is mapped to port a[15] ? bit 16 is mapped to port b[0], bit 17 is mapped to port b[1] and so on, through bit 31, which is mapped to port b[15]. 20.5.3.13 parallel gpio pad data in registers (pgpdi0 ? pgpdi4) the siu_pgpdi registers are similar in operation to the pgpdio regist ers, described in the previous section ( section 20.5.3.12, parallel gpio pad da ta out registers (pgpdo0 ? pgpdo4) ) but they are used to read port pins simultaneously. note the port pins to be read need to be c onfigured as inputs but even if a single pin within a port has ibe set, then you can still read that pin using the parallel port register. however, this doe s mean you need to be very careful. reads of pgpdi registers are equi valent to reading the corresponding gpdi registers but significantly faster since as many as two ports can be read si multaneously with a single 32-bit read operation. table 20-17 shows the locations and structure of the pgpdi x registers. each 32-bit pgpdi x register contains two 16-bit fields, each field c ontaining the values for a separate port. table 20-16. pgpdo0 ? pgpdo4 register map offset 1 1 siu base address is 0xc3f9_0000. to calculate register address add offset to base address register field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0c00 pgpdo0 port a port b 0x0c04 pgpdo1 port c port d 0x0c08 pgpdo2 port e port f 0x0c0c pgpdo3 port g port h 0x0c10 pgpdo4 port i port j reserved table 20-17. pgpdi0 ? pgpdi4 register map offset 1 register field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0c40 pgpdi0 port a port b 0x0c44 pgpdi1 port c port d 0x0c48 pgpdi2 port e port f 0x0c4c pgpdi3 port g port h
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 369 it is important to note the bit orderi ng of the ports in the parallel port regi sters. the most significant bit of the parallel port register corresponds to the least significant pin in the port. for example in table 20-17 , the pgpdi0 register contains fields for port a and port b. ? bit 0 is mapped to port a[0], bit 1 is mapped to port a[1] and so on, through bit 15, which is mapped to port a[15] ? bit 16 is mapped to port b[0], bit 17 is mapped to port b[1] and so on, through bit 31, which is mapped to port b[15]. 20.5.3.14 masked parallel gpio pad data out regi ster (mpgpdo0?mpgpdo9) the mpgpdo x registers are similar in operation to the pgpdo x ports described in section 20.5.3.12, parallel gpio pad data out registers (pgpdo0 ? pgpdo4) , but with two significant differences: ? the mpgpdo x registers support masked port-wide changes to the da ta out on the pads of the respective port. masking effectively allows se lective bitwise writes to the full 16-bit port. ? each 32-bit mpgpdo x register is associ ated to only one port. note the mpgpdo x registers may only be accessed with 32-bit writes. 8-bit or 16-bit writes will not modify any bits in the register and wi ll cause a transfer error response by the module. read accesses return 0. table 20-18 shows the locations and structure of the mpgpdo x registers. each 32-bit mpgpdo x register contains two 16-bit fields (mask x and mppdo x ). the mask field is a bitwise mask for its associated port. the mppdo0 field contains the data to be written to the port. 0x0c50 pgpdi4 port i port j reserved 1 siu base address is 0xc3f9_0000. to calculate register address add offset to base address table 20-18. mpgpdo0 ? mpgpdo9 register map offset 1 register field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x0c80 mpgpdo0 mask0 (port a) mppdo0 (port a) 0x0c84 mpgpdo1 mask1 (port b) mppdo1 (port b) 0x0c88 mpgpdo2 mask2 (port c) mppdo2 (port c) 0x0c8c mpgpdo3 mask3 (port d) mppdo3 (port d) 0x0c90 mpgpdo4 mask4 (port e) mppdo4 (port e) 0x0c94 mpgpdo5 mask5 (port f) mppdo5 (port f) 0x0c98 mpgpdo6 mask6 (port g) mppdo6 (port g) table 20-17. pgpdi0 ? pgpdi4 register map (continued) offset 1 register field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 370 freescale semiconductor it is important to note the bit orderi ng of the ports in the parallel port regi sters. the most significant bit of the parallel port register corresponds to the least significant pin in the port. for example in table 20-18 , the mpgpdo0 register contains field mask0, which is the bitwise mask for port a and field mppdo0, which contai ns data to be written to port a. ? mpgpdo0[0] is the mask bit for port a[0], mpgp do0[1] is the mask bit fo r port a[1] and so on, through mpgpdo0[15], which is the mask bit for port a[15] ? mpgpdo0[16] is the data bit mapped to port a[ 0], mpgpdo0[17] is mapped to port a[1] and so on, through mpgpdo0[31], which is mapped to port a[15]. caution toggling several ios at the same time can significantly increase the current in a pad group. caution must be take n to avoid exceeding maximum current thresholds. please see data sheet. 20.5.3.15 interrupt filter maximum counter registers (ifmc0?ifmc23) these registers are used to confi gure the filter counter associated with each digita l glitch filter. note for the pad transition to trigger an interr upt it must be stea dy for at least the filter period. 0x0c9c mpgpdo7 mask7 (port h) mppdo7 (port h) 0x0ca0 mpgpdo8 mask8 (port i) mppdo8 (port i) 0x0caf mpgpdo9 mask9 (port j) reserved mppdo9 (port j) reserved 1 siu base address is 0xc3f9_0000. to calculate register address add offset to base address table 20-19. mpgpdo0..mpg pdo9 field descriptions field description mask x [15:0] mask field each bit corresponds to one data bit in the mppdo x register at the same bit location. 0 associated bit value in the mppdo x field is ignored 1 associated bit value in the mppdo x field is written mppdo x [15:0] masked parallel pad data out write the data register that stores the value to be dr iven on the pad in output mode. accesses to this register locati on are coherent with accesses to th e bitwise gpio pad data output registers (gpdo0_3?gpdo148_151). the x and bit index define which mppdo register bit is equivalent to which pdo register bit according to the following equation: mppdo[ x ][ y ] = pdo[( x * 16) + y ] table 20-18. mpgpdo0 ? mpgpdo9 register map (continued) offset 1 register field 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 371 20.5.3.16 interrupt filter cloc k prescaler register (ifcpr) this register is used to configure a clock prescaler that selects the clock for all digital filter counters in the siul. offset: 0x1000?0x105c) (24 regist ers) access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 maxcntx w reset0000000000000000 figure 20-13. interrupt filter maximu m counter registers (ifmc0?ifmc23) table 20-20. ifmc field descriptions field description maxcntx maximum interrupt filter counter setting filter period = t(ck) maxcnt x + n t(ck) where ( n can be 1 to 3) maxcnt x can be 0 to 15 t(ck): prescaled filter clock period, which is the firc clock prescaled to ifcp value t(firc): basic filter clock period: 62.5 ns (f firc = 16 mhz) offsets:0x1080 access: user read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000 ifcp w reset0000000000000000 figure 20-14. interrupt filter clock prescaler register (ifcpr)
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 372 freescale semiconductor table 20-21. ifcpr field descriptions 20.6 functional description 20.6.1 pad control the siul controls the configurat ion and electrical characteristic of the device pads. it provides a consistent interface for all pads, both on a by-port a nd a by-bit basis. the pad configuration registers (pcr n , see section 20.5.3.8, pad configurat ion registers (pcr0?pcr148) ) allow software control of the static electrical char acteristics of external pins with a single write. these are used to configure the following pad features: ? open drain output enable ? slew rate control ? pull control ? pad assignment ? control of analog path switches ? safe mode behavi or configuration 20.6.2 general purpose input and output pads (gpio) the siul manages as many as 149 gpio pads organize d as ports that can be accessed for data reads and writes as 32-, 16-, or 8-bit 1 . note ports are organized as groups of 16 gpio pads, with the exception of port j, which has 5. a 32-bit r/w operation acc esses two ports simultaneously. a 16-bit operation accesses a full port and an 8-bit access either the upper or lower byte of a port. as shown in figure 20-15 , all port accesses are identical with each read or write being performed only at a different location to access a different port width. field description ifcp interrupt filter clock prescaler setting prescaled filter clock period = t(firc) (ifcp + 1) t(firc) is the fast internal rc oscillator period. ifcp can be 0 to 15. 1.there are exceptions. some pads, e.g., precision analog pa ds, are input only.
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 373 figure 20-15. data port example arrangement showing configuration for different port width accesses the siul has separate data input (gpdi n_n , see section 20.5.3.11, gpio pad data input registers (gpdi0_3?gpdi148_151) ) and data output (gpdo n_n , see section 20.5.3.10, gpio pad data output registers (gpdo0_3?gpdo148_151) ) registers for all pads , allowing the possibility of reading back an input or output value of a pa d directly. this supports the ability to validate what is present on the pad rather than simply confirming the value that was written to the data register by accessing the data input registers. data output registers allow an output pad to be driv en high or low (with the op tion of push-pull or open drain drive). input registers are read-onl y and reflect the respective pad value. when the pad is configured to use one of its alternate functions, the data input value reflects the respective value of the pad. if a write operation is performed to the data output regi ster for a pad configured as an alternate function (non-gpio), this wr ite will not be reflected by the pad value until reconfigured to gpio. the allocation of what i nput function is connected to the pin is defined by the psmi registers (pcr n , see section 20.5.3.9, pad selection for multiple xed inputs registers (psmi0_3?psmi60_63) ). 20.6.3 external interrupts the siul supports 24 external interrupts, eirq0?eir q23. mapping is shown for external interrupts to pads in chapter 4, signal description . the siul supports three interrupt v ectors to the interrupt controller. each vector interrupt has eight external interrupts combined together with the presence of flag generating an interrupt for that vector if enabled. all of the external interrupt pads within a si ngle group have equal priority. see figure 20-16 for an overview of the external interrupt implementation. 31 23 siul base+ 0x0c00 15 7 0 siul base+ 15 7 0 siul base+ 15 7 0 siul base+ 70 0x0c03 siul base+ 70 0x0c02 siul base+ 70 0x0c01 siul base+ 70 0x0c00 0x0c02 0x0c00 32-bit access (2 ports) 16-bit access (full port) 16-bit access (full port) 8-bit access (half port) 8-bit access (half port) 8-bit access (half port) 8-bit access (half port)
chapter 20 system integration unit lite (siul) MPC5606BK microcontroller reference manual, rev. 2 374 freescale semiconductor figure 20-16. external interrupt pad diagram 3 20 interrupts in 100-pin lqfp. each interrupt can be enabled or disabled independently. this can be performed using the irer. a pad defined as an external in terrupt can be configured to recognize interrupts with an active rising edge, an active falling edge or both edges bei ng active. a setting of having both e dge events disabled is reserved and should not be configured. the active eirq edge is controlled through th e configuration of the registers ireer and ifeer. each external interrupt supports an i ndividual flag in the interrupt status flag register (isr ). the bits in the isr[eif] field are cleared by writing a 1 to them; this prevents inadvertent overwriting of other flags in the register. 20.7 pin muxing for pin muxing, please see chapter 4, signal description . eif[23:16] eif[15:8] eif[7:0] ire[23:0] (1) pads iree[23:0] (1) interrupt edge enable ifee[23:0] (1) falling rising edge detection glitch filter interrupt enable or or or irq_23_16 irq_15_08 irq_07_00 interrupt vectors ife[23:0] maxcount[x] irq glitch filter enable glitch filter counter_n ifcp[3:0] glitch filter prescaler interrupt controller
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 375 chapter 21 memory protection unit (mpu) 21.1 introduction the memory protection unit (mpu) provides hard ware access control for all memory references generated in the device. using preprogrammed region descriptors that define memory spaces and their associated access rights, the mpu concurrently monito rs all system bus transactions and evaluates the appropriateness of each transfer. me mory references that have sufficie nt access control rights are allowed to complete, while references that are not mapped to any region descriptor or have insufficient rights are terminated with a protection error response. the mpu module provides the following capabilities: ? support for 8 program-visible 128-bi t (4-word) region descriptors ? each region descriptor defi nes a modulo-32 byte space, al igned anywhere in memory ? region sizes can vary from a minimum of 32 bytes to a maximum of 4 gbytes ? two types of access control permissi ons defined in single descriptor word ? processors have separate {read, write, execute } attributes for supervisor and user accesses ? non-processor masters have {read, write} attributes ? hardware-assisted maintenance of the desc riptor valid bit minimi zes coherency issues ? alternate programming model view of the access control permissions word ? memory-mapped platform device ? interface to three slave xbar ports: flash cont roller, system sram cont roller and peripherals bus ? connections to the address phase address and attributes ? typical location is immediately downstream of the platform?s crossbar switch a simplified block diagram of the mpu module is shown in figure 21-1 .
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 376 freescale semiconductor figure 21-1. mpu block diagram 21.2 features the memory protection unit implemen ts a two-dimensional hardware ar ray of memory region descriptors and the crossbar slave xbar ports to continuously monitor the legality of every memory reference generated by each bus master in th e system. the feature set includes: ? support for eight memory region descriptors, each 128 bits in size ? specification of start and end addresses provide gran ularity for region sizes from 32 bytes to 4gb ? access control definitions: two bus masters (pro cessor cores) support the traditional {read, write, execute} permissions with independent definitions for superv isor and user mode accesses ? automatic hardware maintenance of the region de scriptor valid bit rem oves issues associated with maintaining a coherent image of the descriptor ? alternate memory view of the access control wo rd for each descriptor provides an efficient mechanism to dynamically alter only the access rights of a descriptor ? for overlapping region descript ors, priority is given to permission granting over access denying as this approach provides more flexibility to sy stem software. see section 21.6.2, putting it all together a nd ahb error terminations, for details and section 21.8, application information, for an example. pflash pram pbridge0 core (z0hn2p) xbar mpu s0 s2 s7 m0 m1 platform m2 edma
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 377 ? support for three xbar slave port connections: flash controller, system sram controller and peripherals bus: ? mpu hardware continuously monitors every xbar slave port access using the preprogrammed memory region descriptors. ? an access protection error is det ected if a memory reference doe s not hit in any memory region or the reference is flagged as il legal in all memory regions where it does hit. in the event of an access error, the xbar reference is terminated with an error response and the mpu inhibits the bus cycle being sent to the targeted slave device. ? 64-bit error registers, one for each xbar sl ave port, capture the last faulting address, attributes, and detail information. ? global mpu enable/disable control bit provides a mechanism to easily load region descriptors during system startup or allow complete acces s rights during debug with the module disabled. 21.3 modes of operation the mpu module does not support any special modes of operation. as a memory-mapped device located on the platform?s high-speed system bus, it responds based strictly on the memory addresses of the connected system buses. the peripheral bus is us ed to access the mpu?s programming model and the memory protection functions are evaluated on a reference-by-referen ce basis using the addresses from the xbar system bus port(s). power dissipation is minimized when the mp u?s global enable/disable bit is cleared (mpu_cesr[vld] = 0). 21.4 external signal description the mpu module does not include any external inte rface. the mpu?s internal interfaces include a peripheral bus connection fo r accessing the programming model and multiple conn ections to the address phase signals of the platform cro ssbar?s slave ahb ports. from a pl atform topology viewpoint, the mpu module appears to be directly conn ected downstream from the crossbar switch with interfaces to the xbar slave ports. 21.5 memory map and register description the mpu module provides an ips programming model ma pped to an spp-standard on-platform 16 kb space. the programming model is partitioned into three groups: control/status regist ers, the data structure containing the region descriptors an d the alternate view of the regi on descriptor access control values. the programming model can onl y be referenced using 32- bit (word) accesses. atte mpted references using different access sizes, to undefined (r eserved) addresses, or with a non- supported access type (for example, a write to a read-only regi ster or a read of a write-only regist er) generate an ips error termination. finally, the programming model allocates space for an mpu definition w ith 8 region desc riptors and as many as three xbar slave ports, like flash contro ller, system sram controller and peripheral bus.
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 378 freescale semiconductor 21.5.1 memory map the mpu programming model map is shown in table 21-1 . table 21-1. mpu memory map base address: 0xfff1_1000 address offset register location 0x000 mpu control/error status register (mpu_cesr) on page 379 0x004?0x00f reserved 0x010 mpu error address register, slave port 0 (mpu_ear0) on page 380 0x014 mpu error detail register, slave port 0 (mpu_edr0) on page 381 0x018 mpu error address register, slave port 1 (mpu_ear1) on page 380 0x01c mpu error detail register, slave port 1 (mpu_edr1) on page 381 0x020 mpu error address register, slave port 2 (mpu_ear2) on page 380 0x024 mpu error detail register, slave port 2 (mpu_edr2) on page 381 0x028?0x3ff reserved 0x400 mpu region descriptor 0 (mpu_rgd0) on page 382 0x410 mpu region descriptor 1 (mpu_rgd1) on page 382 0x420 mpu region descriptor 2 (mpu_rgd2) on page 382 0x430 mpu region descriptor 3 (mpu_rgd3) on page 382 0x440 mpu region descriptor 4 (mpu_rgd4) on page 382 0x450 mpu region descriptor 5 (mpu_rgd5) on page 382 0x460 mpu region descriptor 6 (mpu_rgd6) on page 382 0x470 mpu region descriptor 7 (mpu_rgd7) on page 382 0x480?0x7ff reserved 0x800 mpu rgd alternate access control 0 (mpu_rgdaac0) on page 387 0x804 mpu rgd alternate access control 1 (mpu_rgdaac1) on page 387 0x808 mpu rgd alternate access control 2 (mpu_rgdaac2) on page 387 0x80c mpu rgd alternate access control 3 (mpu_rgdaac3) on page 387 0x810 mpu rgd alternate access control 4 (mpu_rgdaac4) on page 387 0x814 mpu rgd alternate access control 5 (mpu_rgdaac5) on page 387 0x818 mpu rgd alternate access control 6 (mpu_rgdaac6) on page 387 0x81c mpu rgd alternate access control 7 (mpu_rgdaac7) on page 387
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 379 21.5.2 register description 21.5.2.1 mpu control/error st atus register (mpu_cesr) the mpu_cesr provides one byte of error status plus three bytes of configur ation information. a global mpu enable/disable bit is also included in this register. offset: 0x000 access: read/partial write 0123456789101112131415 r sperr[0:2] 000001000 hrl w w1c w1c w1c reset0000000010000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rnsp nrgd 00 00 0 0 0 vld w reset0011000000000000 figure 21-2. mpu control/error status register (mpu_cesr) table 21-2. mpu_cesr field descriptions field description sperr n slave port n error, where the slave port number matches the bit number. see ta bl e 2 1 - 3 . each bit in this field represents a flag maintained by the mpu for signaling the presence of a captured error contained in the mpu_ear n and mpu_edr n registers. the individual bit is set when the hardware detects an error and records the faulting address and attributes. it is cleared when the corresponding bit is written as a lo gical one. if another error is ca ptured at the exact same cycle as a write of a logical one, this flag remains set. a ?fi nd first one? instruction (or equivalent) can be used to detect the presence of a captured error. 0 the corresponding mpu_ear n /mpu_edr n registers do not contain a captured error. 1 the corresponding mpu_ear n /mpu_edr n registers do contain a captured error. hrl hardware revision level this field specifies the mpu?s hardware and definition revision level. it can be read by software to determine the functional definition of the module. nsp number of slave ports this field specifies the number of sl ave ports [1?8] connected to the mpu. nrgd number of region descriptors this field specifies the number of region descript ors implemented in the mpu. the defined encodings include: 0000 8 region descriptors 0001 12 region descriptors 0010 16 region descriptors
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 380 freescale semiconductor 21.5.2.2 mpu error address register, slave port n (mpu_ear n ) when the mpu detects an access error on slave port n , the 32-bit reference address is captured in this read-only register and the corresponding bit in the mpu_cesr[sperr] field set. additional information about the faulting acces s is captured in the corresponding mpu_edr n register at the same time. note this register and the corresponding mpu_edr n register contain the most r ecent access error; there are no hardware interlocks with the mpu_ cesr[sperr] field as the error re gisters are always loaded upon the occurrence of each pr otection violation. vld valid this bit provides a global enable/disable for the mpu. 0 the mpu is disabled. 1 the mpu is enabled. while the mpu is disabled, all accesses from all bus masters are allowed. table 21-3. sperr implementation sperr bit corresponding port sperr[0] flash memory controller slave port sperr[1] system ram controller slave port sperr[2] ips peripheral bus slave port offsets: 0x010?0x020 (3 registers) access: read 0123456789101112131415 r eaddr [31:16] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eaddr [15:0] w reset???????????????? figure 21-3. mpu error address register, slave port n (mpu_earn) table 21-4. mpu_ear n field descriptions field description eaddr error address this field is the reference address from sl ave port n that generated the access error. table 21-2. mpu_cesr field descriptions (continued) field description
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 381 21.5.2.3 mpu error detail register, slave port n (mpu_edr n ) when the mpu detects an access error on slave port n , 32 bits of error detail ar e captured in this read-only register and the corresponding bit in the mpu_cesr [sperr] field set. information on the faulting address is captured in the corresponding mpu_ear n register at the same time. note that this register and the corresponding mpu_ear n register contain the most recent access error; ther e are no hardware interlocks with the mpu_cesr[sperr] field as the er ror registers are always loaded upon the occurrence of each protection violation. offsets: 0x014?0x024 (3 registers) access: read 0123456789101112131415 r eacd 00000000 w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r epid emn eattr erw w reset???????????????? figure 21-4. mpu error detail register, slave port n (mpu_edr n ) table 21-5. mpu_edrn field descriptions field description eacd error access control detail this field implements one bit per region descriptor and is an indication of the region descriptor hit logically anded with the access error indication. the mpu performs a reference-by-reference evaluation to determine the presence/absence of an access error. when an error is detected, the hit-qualified access control vector is captured in this field. if the mpu_edr n register contains a captured error and the eacd field is all zeroes, this signals an access that did not hit in any region descriptor. all non-zero eacd values signal references that hit in a region descriptor(s), but failed due to a protection erro r as defined by the specific set bits. if only a single eacd bit is set, then the protection erro r was caused by a single non-overlapping region descriptor. if two or more eacd bits are set, then the protection error was caused in an overlapping set of region descriptors. epid error process identification this field records the process identifier of the faulting reference. the process identifier is typically driven only by processor cores; for other bus masters, this field is cleared. emn error master number this field records the logical master number of the faulting reference. this field is used to determine the bus master that generated the access error.
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 382 freescale semiconductor 21.5.2.4 mpu region descriptor n (mpu_rgd n ) each 128-bit (16-byte) region descri ptor specifies a given memory space and the access attributes associated with that space. the desc riptor definition is the very esse nce of the operation of the memory protection unit. the region descriptors ar e organized sequentially in the mpu?s pr ogramming model and each of the four 32-bit words are detailed in the subsequent sections. 21.5.2.4.1 mpu region descriptor n , word 0 (mpu_rgdn .word0) the first word of the mpu region descriptor define s the 0-modulo-32 byte start address of the memory region. writes to this word clear th e region descriptor?s valid bit (see section 21.5.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). eattr error attributes this field records attribute information about the faulting reference. the supported encodings are defined as: 000 user mode, instruction access 001 user mode, data access 010 supervisor mode, instruction access 011 supervisor mode, data access all other encodings are reserved. for non-core bus ma sters, the access attribute information is typically wired to supervisor, data (0b011). erw error read/write this field signals the access type (read, write) of the faulting reference. 0read 1write offset: 0x400 + (16 n) + 0x0 (mp u_rgdn.word0) access: read/write 0123456789101112131415 r srtaddr[26:11] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r srtaddr[10:0] 00000 w reset???????????00000 figure 21-5. mpu region descript or, word 0 register (mpu_rgd n .word0) table 21-5. mpu_edrn field descriptions (continued) field description
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 383 21.5.2.4.2 mpu region descriptor n , word 1 (mpu_rgd n .word1) the second word of the mpu region descriptor defines the 31-modulo-32 byte end address of the memory region. writes to this word clear th e region descriptor?s valid bit (see section 21.5.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). 21.5.2.4.3 mpu region descriptor n , word 2 (mpu_rgd n .word2) the third word of the mpu region de scriptor defines the access control rights of the memory region. the access control privileges are depende nt on two broad classifications of bus masters. bus masters 0?3 are typically reserved for processor cores and the corresponding access c ontrol is a 6-bit field defining separate privilege rights for user and supervisor mode accesses as we ll as the optional inclusion of a process identification field within th e definition. bus masters 4?7 are typically reserv ed for data movement engines, and their capabilit ies are limited to separate read and wr ite permissions. for these fields, the bus master number refers to the l ogical master number defined as the xbar hmaster[3:0] signal. for the processor privilege rights, there are three flags associated with this functi on: {read, write, execute}. in this context, these flags follow the traditional definition: table 21-6. mpu_rgdn.word0 field descriptions field description srtaddr start address this field defines the most significant bits of the 0-modulo-32 byte start address of the memory region. offset: 0x400 + (16 n) + 0x4 (mp u_rgdn.word1) access: read/write 0123456789101112131415 r endaddr[26:11] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r endaddr[10:0] 11111 w reset???????????11111 figure 21-6. mpu region descript or, word 1 register (mpu_rgd n .word1) table 21-7. mpu_rgd n .word1 field descriptions field description endaddr end address this field defines the most sign ificant bits of the 31-modulo-32 byte end address of the memory region. there are no hardware checks to verify that endaddr ? srtaddr; it is software?s responsibility to properly load these region descriptor fields.
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 384 freescale semiconductor ? read ( r ) permission refers to the ability to access th e referenced memory address using an operand (data) fetch. ?write ( w ) permission refers to the ability to update the referenced memory address using a store (data) instruction. ? execute ( x ) permission refers to the ability to read the referenced memory address using an instruction fetch. the evaluation logic defines the processor access t ype based on multiple ahb signals, as hwrite and hprot[1:0]. for non-processor data movement engi nes (bus masters 4?7), the evaluati on logic simply uses hwrite to determine if the access is a read or write. writes to this word clear the re gion descriptor?s valid bit (see section 21.5.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) for more information). since it is al so expected that system software may adjust only the access controls with in a region descriptor (mpu_rgdn.wo rd2) as different tasks execute, an alternate programming view of th is 32-bit entity is provided. if only the access controls are being updated, this operation should be pe rformed by writing to mpu_rgdaacn (alternate access control n) as stores to these locations do not affect the descri ptor?s valid bit. offset: 0x400 + (16 n) + 0x8 (mpu_rgdn.word2) access: r/w 0123456789101112131415 r m7re m7we m6re m6we m5re m5we m4re m4we m3pe m3sm m3um m2pe m2sm[1] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m2sm[0] m2um 0000000 m0pe m0sm m0um w reset???0000000?????? figure 21-7. mpu region descript or, word 2 register (mpu_rgd n .word2) table 21-8. mpu_rgd n .word2 field descriptions field description m7re bus master 7 read enable if set, this flag allows bus master 7 to perform read operations. if cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. m7we bus master 7 write enable if set, this flag allows bus master 7 to perform wr ite operations. if cleared, any attempted write by bus master 7 terminates with an access error and the write is not performed. m6re bus master 6 read enable if set, this flag allows bus master 6 to perform read operations. if cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed.
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 385 m6we bus master 6 write enable if set, this flag allows bus master 6 to perform wr ite operations. if cleared, any attempted write by bus master 6 terminates with an access error and the write is not performed. m5re bus master 5 read enable if set, this flag allows bus master 5 to perform read operations. if cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. m5we bus master 5 write enable if set, this flag allows bus master 5 to perform wr ite operations. if cleared, any attempted write by bus master 5 terminates with an access error and the write is not performed. m4re bus master 4 read enable if set, this flag allows bus master 4 to perform read operations. if cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. m4we bus master 4 write enable if set, this flag allows bus master 4 to perform wr ite operations. if cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed. m3pe bus master 3 process identifier enable if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m3sm bus master 3 supervis or mode access control this field defines the access controls for bus master 3 when operating in supervisor mode. the m3sm field is defined as: 00 r, w, x = read, write and execute allowed 01 r, ?, x = read and execute allowed, but no write 10 r, w, ? = read and write allowed, but no execute 11 same access controls as that defined by m3um for user mode m3um bus master 3 user mode access control this field defines the access controls for bus mast er 3 when operating in user mode. the m3um field consists of three independent bits, enabling read, writ e and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. m2pe bus master 2 process identifier enable if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m2sm bus master 2 supervis or mode access control this field defines the access controls for bus master 2 when operating in supervisor mode. the m2sm field is defined as: 00 r, w, = read and write allowed 01 r = read allowed, but no write 10 r, w = read and write allowed 11 same access controls as that defined by m2um for user mode m2um bus master 2 user mode access control this field defines the access controls for bus mast er 2 when operating in user mode. the m2um field consists of two independent bits, enabling read and wr ite permissions: {r,w}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. table 21-8. mpu_rgd n .word2 field descriptions (continued) field description
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 386 freescale semiconductor 21.5.2.4.4 mpu region descriptor n , word 3 (mpu_rgd n .word3) the fourth word of the mpu region descriptor contains the optional process identi fier and mask, plus the region descriptor?s valid bit. since the region descriptor is a 128-bi t entity, there are potential coherency issues as this structure is being updated since multiple writes are required to update the entire descriptor. ac cordingly, the mpu hardware assists in the operation of the descri ptor valid bit to preven t incoherent region desc riptors from generating spurious access errors. in pa rticular, it is expected th at a complete update of a re gion descriptor is typically done with sequential writes to mpu_rgd n .word0, then mpu_rgd n .word1,... and finally mpu_rgd n .word3. the mpu hardware automatically clears the valid bit on any writes to words {0,1,2} of the descriptor. writes to this word set/clear the valid bit in a normal manner. since it is also expected that system software may ad just only the access controls within a region descriptor (mpu_rgd n .word2) as different tasks execute, an altern ate programming view of this 32-bit entity is provided. if only the access controls are being updated, this operation s hould be performed by writing to mpu_rgdaac n (alternate access control n) as stores to these locations do not affect the descriptor?s valid bit. m0pe bus master 0 process identifier enable if set, this flag specifies that the process identifier and mask (defined in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m0sm bus master 0 supervis or mode access control this field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 00 r, w, x = read, write and execute allowed 01 r, ?, x = read and execute allowed, but no write 10 r, w, ? = read and write allowed, but no execute 11 same access controls as that defined by m0um for user mode m0um bus master 0 user mode access control this field defines the access controls for bus mast er 0 when operating in user mode. the m0um field consists of three independent bits, enabling read, writ e and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. table 21-8. mpu_rgd n .word2 field descriptions (continued) field description
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 387 21.5.2.5 mpu region descriptor alternate access control n (mpu_rgdaac n ) as noted in section 21.5.2.4.3, mpu region descript or n, word 2 (mpu_rgdn.word2) , it is expected that since system software may adjust only the access controls within a region descriptor (mpu_rgd n .word2) as different tasks execute, an altern ate programming view of this 32-bit entity is desired. if only the access controls are being update d, this operation should be performed by writing to mpu_rgdaac n (alternate access control n) as stores to th ese locations do not affect the descriptor?s valid bit. the memory address therefore provides an alternate location for updating mpu_rgd n .word2. offset: 0x400 + (16 n) + 0xc (m pu_rgdn.word3) access: read/write 0123456789101112131415 r pid pidmask w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 00000000 00 0 0 0 vld w reset0000000000000000 figure 21-8. mpu region descript or, word 3 register (mpu_rgd n .word3) table 21-9. mpu_rgd n .word3 field descriptions field description pid process identifier this field specifies that the optional process identifi er is to be included in the determination of whether the current access hits in the re gion descriptor. this field is co mbined with the pidmask and included in the region hit determination if mpu_rgd n .word2[m x pe] is set. pidmask process identifier mask this field provides a masking capability so that mult iple process identifiers can be included as part of the region hit determination. if a bit in the pidmask is set, then the corresponding bit of the pid is ignored in the comparison. this field is combined with the pid and included in the region hit determination if mpu_rgd n .word2[m x pe] is set. for more information on the handling of the pid and pidmask, see section 21.6.1.1, access ev aluation ? hit determination . vld valid this bit signals the region descriptor is valid. any write to mpu_rgd n .word{0,1,2} clears this bit, while a write to mpu_rgd n .word3 sets or clears this bit depending on bit 31 of the write operand. 0 region descriptor is invalid 1 region descriptor is valid
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 388 freescale semiconductor since the mpu_rgdaac n register is simply another memory mapping for mpu_rgd n .word2, the field definitions shown in table 21-10 are identical to those presented in table 21-8 . offset: 0x800 + (4 n) (mpu_r gdaacn) access: read/write 0123456789101112131415 r m7re m7we m6re m6we m5re m5we m4re m4we m3pe m3sm m3um m2pe m2sm[1] w reset???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r m2sm[0] m2um 0000000 m0pe m0sm m0um w reset???0000000?????? figure 21-9. mpu rgd alternate access control n (mpu_rgdaac n ) table 21-10. mpu_rgdaac n field descriptions field description m7re bus master 7 read enable. if set, this flag allows bus master 7 to perform read operations. if cleared, any attempted read by bus master 7 terminates with an access error and the read is not performed. m7we bus master 7 write enable if set, this flag allows bus master 7 to perform writ e operations. if cleared, any attempted write by bus master 7 terminates with an access error and the write is not performed. m6re bus master 6 read enable if set, this flag allows bus master 6 to perform read operations. if cleared, any attempted read by bus master 6 terminates with an access error and the read is not performed. m6we bus master 6 write enable if set, this flag allows bus master 6 to perform writ e operations. if cleared, any attempted write by bus master 6 terminates with an access error and the write is not performed. m5re bus master 5 read enable if set, this flag allows bus master 5 to perform read operations. if cleared, any attempted read by bus master 5 terminates with an access error and the read is not performed. m5we bus master 5 write enable if set, this flag allows bus master 5 to perform writ e operations. if cleared, any attempted write by bus master 5 terminates with an access error and the write is not performed. m4re bus master 4 read enable if set, this flag allows bus master 4 to perform read operations. if cleared, any attempted read by bus master 4 terminates with an access error and the read is not performed. m4we bus master 4 write enable if set, this flag allows bus master 4 to perform writ e operations. if cleared, any attempted write by bus master 4 terminates with an access error and the write is not performed.
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 389 m3pe bus master 3 process identifier enable if set, this flag specifies that th e process identifier and mask (defin ed in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m3sm bus master 3 supervisor mode access control this field defines the access controls for bus master 3 when operating in supervisor mode. the m3sm field is defined as: 00 r, w, x = read, write and execute allowed 01 r, ?, x = read and execute allowed, but no write 10 r, w, ? = read and write allowed, but no execute 11 same access controls as that defined by m3um for user mode m3um bus master 3 user mode access control this field defines the access controls for bus mast er 3 when operating in user mode. the m3um field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. m2pe bus master 2 process identifier enable if set, this flag specifies that th e process identifier and mask (defin ed in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m2sm bus master 2 supervisor mode access control this field defines the access controls for bus master 2 when operating in supervisor mode. the m2sm field is defined as: 00 r, w, = read and write allowed 01 r = read allowed, but no write 10 r, w = read and write allowed 11 same access controls as that defined by m2um for user mode m2um bus master 2 user mode access control this field defines the access controls for bus mast er 2 when operating in user mode. the m2um field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. m0pe bus master 0 process identifier enable if set, this flag specifies that th e process identifier and mask (defin ed in mpu_rgdn.word3) are to be included in the region hit evaluation. if cleared, then the region hit evaluation does not include the process identifier. m0sm bus master 0 supervisor mode access control this field defines the access controls for bus master 0 when operating in supervisor mode. the m0sm field is defined as: 00 r, w, x = read, write and execute allowed 01 r, ?, x = read and execute allowed, but no write 10 r, w, ? = read and write allowed, but no execute 11 same access controls as that defined by m0um for user mode m0um bus master 0 user mode access control this field defines the access controls for bus mast er 0 when operating in user mode. the m0um field consists of three independent bits, enabling read, write and execute permissions: {r,w,x}. if set, the bit allows the given access type to occur; if cleared, an attempted access of that mode may be terminated with an access error (if not allowed by any other descriptor) and the access not performed. table 21-10. mpu_rgdaac n field descriptions (continued) field description
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 390 freescale semiconductor 21.6 functional description in this section, the functional operati on of the mpu is detailed. in partic ular, subsequent sections discuss the operation of the access evaluation macro as well as the handling of error-terminated bus cycles. 21.6.1 access evaluation macro as previously discussed, the basic operation of th e mpu is performed in the access evaluation macro, a hardware structure replicated in the two- dimensional connection matrix. as shown in figure 21-10 , the access evaluation macro inputs the syst em bus address phase si gnals and the contents of a region descriptor (rgdn) and performs two major functions: region hit de termination (hit_b) and detection of an access protection violation (error). figure 21-10. mpu access evaluation macro figure 21-10 is not intended to be a schematic of th e actual access evaluation macro, but rather a generalized block diagram showing the majo r functions included in this logic block. 21.6.1.1 access evaluation ? hit determination to evaluate the region hit determination, the mpu us es two magnitude comparators in conjunction with the contents of a region descriptor : the current access must be included between th e region's start and end addresses and simultaneously the region's valid bit must be active. recall there are no hardware checks to verify that region's end address is greater then region's start address, and it is software?s responsibility to properly load appropriate values into these fields of the region descriptor. in addition to this, the optional process identifier is examined against the region descriptor?s pid and pidmask fields. in order to generate the pid_hit i ndication: the current pid with its pidmask must be equal to the region's pid with its pidm ask. also the process identifier enab le is take into account in this comparison so that the mpu forces the pid_hit term to be asserted in the case of ahb bus master doesn't provide its process identifier. hit_b start end error > > rgdn system bus hit & error hit_b | error ? ? r,w,x address phase
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 391 21.6.1.2 access evaluation ? priv ilege violation determination while the access evaluation macro is making the region hit determinat ion, the logic is also evaluating if the current access is allowed by the permissions define d in the region descriptor . the protection violation logic then evaluates the access against the effect ive permissions using the specification shown in table 21-11 . as shown in figure 21-10 , the output of the protection viol ation logic is the error signal. the access evaluation macro then uses the hit_b and error signals to form two outputs. the combined (hit_b | error) signal is used to signa l the current access is not allowed a nd (~hit_b & error) is used as the input to mpu_edrn (error detail re gister) in the event of an error. 21.6.2 putting it all together and ahb error terminations for each xbar slave port being monitored, the mpu performs a reduction-and of all the individual (hit_b | error) terms from each acces s evaluation macro. this expression then terminat es the bus cycle with an error and reports a protect ion error for three conditions: ? if the access does not hit in any region descriptor, a protection error is reported. ? if the access hits in a single region descriptor a nd that region signals a pr otection violation, then a protection error is reported. ? if the access hits in multiple ( overlapping) regions and all regions signal protect ion violations, then a protection error is reported. the third condition reflects that priority is given to permission granting over access denying for overlapping regions as this approach provides more flexibility to syst em software in region descriptor assignments. for an example of the use of overlapping region descriptors, see section 21.8, application information . in event of a protection error, th e mpu requires two distinct actions: ? intercepting the error during the address phase (first cycle out of tw o) and cancelling the transaction before it is seen by the slave device table 21-11. protection violation definition description inputs output eff_rgd[r] eff_rgd[w] eff_rgd[x] protection violation? inst fetch read ? ? 0 yes, no x permission inst fetch read ? ? 1 no, access is allowed data read 0 ? ? yes, no r permission data read 1 ? ? no, access is allowed data write ? 0 ? yes, no w permission data write ? 1 ? no, access is allowed
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 392 freescale semiconductor ? performing the required logic functions to forc e the standard 2-cycle ahb error response to properly terminate the bus transact ion and then providing the right va lues to the crossbar switch to commit the transaction to ot her portions of the platform. if, instead, the access is allowed, then the mpu simply pa sses all original signals to the slave device. in this case, from a functionality point of view, the mpu is fully transparent. 21.7 initialization information the reset state of mpu_cesr[vld] disables the enti re module. recall that wh ile the mpu is disabled, all accesses from all bus masters are allowed. this st ate also minimizes the power dissipation of the mpu. the power dissipation of each access evaluation macro is minimized when the associated region descriptor is marked as invalid or when mpu_cesr[vld] = 0. typically the appropriate number of region descriptors (mpu_rgd n ) is loaded at system startup, including the setting of the mpu_rgdn.word3[vld] bi ts, before mpu_cesr[vld] is set, enabling the module. this approach allows all the loaded region de scriptors to be enabled si multaneously. recall if a memory reference does not hit in an y region descriptor, the attempted acc ess is terminated with an error. 21.8 application information in an operational system, interfacing with the mpu can generally be classi fied into the following activities: ? creation of a new memory region requires load ing the appropriate region descriptor into an available register location. when a ne w descriptor is loaded into a rgd n , it would typically be performed using four 32-bit wo rd writes. as discussed in section 21.5.2.4.4, mpu region descriptor n, word 3 (mpu_rgdn.word3) , the hardware assists in the maintenance of the valid bit, so if this approach is foll owed, there are no coherency issues associated with the multi-cycle descriptor writes. deletion/remova l of an existing memory region is performed simply by clearing mpu_rgd n .word3[vld]. ? if only the access rights for an existing region desc riptor need to change , a 32-bit write to the alternate version of the access control word (mpu_rgdaac n ) would typically be performed. recall writes to the region descriptor using this alternate access control location do not affect the valid bit, so there are, by de finition, no coherency issues invol ved with the update. the access rights associated with the memory region switch in stantaneously to the new value as the ips write completes. ? if the region?s start and end addresses are to be changed, this would typically be performed by writing a minimum of three words of the region descriptor: mpu_rgd n .word{0,1,3}, where the writes to word0 and word1 redefine the start a nd end addresses, respectively, and the write to word3 re-enables the region descri ptor valid bit. in many situati ons, all four words of the region descriptor would be rewritten. ? typically, references to the mpu?s programming m odel would be restricted to supervisor mode accesses from a specific processor(s) , so a region descriptor would be specifically allocated for this purpose with attempted accesses from other masters or while in user mode terminated with an error. when the mpu detects an access error, the current bus cycle is terminated with an error response, and information on the faulting reference is captured in the mpu_earn and mpu_edr n registers. the
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 393 error-terminated bus cycle typically in itiates some type of error response in the originating bus master. for example, the cpu errors generate a core exception, whereas the dma errors ge nerate a mpu (external) interrupt. it is important to highlight that in case of dma access violat ions, the core continues to run, but if a core violation occurs, the system stops. in any event, the processor can retrieve the captured error address and detail information by reading the mpu_e{a,d}r n registers. information on that error registers contain captured fault da ta is signaled by mpu_cesr[sperr].
chapter 21 memory protection unit (mpu) MPC5606BK microcontroller reference manual, rev. 2 394 freescale semiconductor this page is intent ionally left blank.
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 395 ??? communication modules ???
MPC5606BK microcontroller reference manual, rev. 2 396 freescale semiconductor this page is intent ionally left blank.
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 397 chapter 22 inter-integrated circuit bus controller module (i 2 c) 22.1 introduction 22.1.1 overview the inter-integrated circuit (i 2 c or iic) bus is a two wire bidirecti onal serial bus that provides a simple and efficient method of data excha nge between devices. it minimizes the number of external connections to devices and does not require an external address decoder. this bus is suitable for applicat ions requiring occasional communications over a short distance between a number of devices. it also provides flexibility, allowing additional device s to be connected to the bus for further expansion and system development. the interface is designed to operate as fast as 100 kbi t/s in standard mode a nd 400 kbit/s in fast mode. the device is capable of operating at higher baud rates, up to a maximum of module clock/20 with reduced bus loading. actual baud rate can be less than the programmed baud rate and is dependent on the scl rise time. scl rise time is dependent on the external pullup resistor value and bus loading. the maximum communication length and the number of devices that can be connected are li mited by a maximum bus capacitance of 400 pf. 22.1.2 features the i 2 c module has the following key features: ? compatible with i 2 c bus standard ? multi-master operation ? software programmable for one of 256 different serial clock frequencies ? software selectable acknowledge bit ? interrupt driven byte-by-byte data transfer ? arbitration lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection ? bus busy detection ? direct memory access features currently not supported: ? no support for general call address ? not compliant to 10-bit addressing
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 398 freescale semiconductor 22.1.3 block diagram the block diagram of the i 2 c module is shown in figure 22-1 . figure 22-1. i 2 c block diagram 22.2 external signal description the inter-integrated circuit (i 2 c) module has two external pins, scl and sda. 22.2.1 scl this is the bidirectional seri al clock line (scl) of the m odule, compatible with the i 2 c-bus specification. 22.2.2 sda this is the bidirectional seri al data line (sda) of the m odule, compatible with the i 2 c-bus specification. 22.3 memory map and register description 22.3.1 module memory map the memory map for the i 2 c module is given below in table 22-1 . the total address for each register is the sum of the base address for the i 2 c module and the address offset for each register. in/out data shift register address compare sda interrupt clock control start stop arbitration control scl bus_clock i 2 c registers
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 399 all registers are accessible via 8-, 16-, or 32-bit accesses. however, 16-bit accesses must be aligned to 16-bit boundaries, and 32-bit accesses mu st be aligned to 32-bit boundaries. as an example, the ibdf register for the frequency divi der is accessible by a 16-bit read/w rite to address base + 0x000, but performing a 16-bit access to base + 0x001 is illegal. 22.3.2 i 2 c bus address register (ibad) this register contains the address the i 2 c bus will respond to when addressed as a slav e; note that it is not the address sent on the bus during the address transfer. table 22-1. i2c memory map base address: 0xffe3_0000 address offset register location 0x0 i 2 c bus address register (ibad) on page 399 0x1 i 2 c bus frequency divider register (ibfd) on page 400 0x2 i 2 c bus control register (ibcr) on page 406 0x3 i 2 c bus status register (ibsr) on page 407 0x4 i 2 c bus data i/o register (ibdr) on page 408 0x5 i 2 c bus interrupt config register (ibic) on page 409 offset 0x0 access: read/write any time 76543210 r adr 0 w reset00000000 figure 22-2. i 2 c bus address register (ibad) table 22-2. ibad field descriptions field description adr slave address. specific slave address to be used by the i 2 c bus module. note: the default mode of i 2 c bus is slave mode for an address match on the bus.
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 400 freescale semiconductor 22.3.3 i 2 c bus frequency divider register (ibfd) offset 0x1 access: read/write any time 76543210 r ibc w reset00000000 figure 22-3. i 2 c bus frequency divider register (ibfd) table 22-3. ibfd field descriptions field description ibc i-bus clock rate. this field is used to prescale the clock for bit rate selection. the bit clock generator is implemented as a prescale divider. the ibc bits ar e decoded to give the tap and prescale values as follows: 7?6 select the prescaled shift register (see ta b l e 2 2 - 4 ) 5?3 select the prescaler divider (see ta b l e 2 2 - 5 ) 2?0 select the shift register tap point (see table 22-6 ) table 22-4. i-bus multiplier factor ibc7 ? 6mul 00 01 01 02 10 04 11 reserved table 22-5. i-bus prescaler divider values ibc5 ? 3 scl2start (clocks) scl2stop (clocks) scl2tap (clocks) tap2tap (clocks) 0002741 0012742 0102964 0116968 100 14 17 14 16 101 30 33 30 32 110 62 65 62 64 111 126 129 126 128
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 401 the number of clocks from the falling edge of scl to the first tap (tap[1 ]) is defined by the values shown in the scl2tap column of table 22-5 . all subsequent tap points are separated by 2 ibc5-3 as shown in the tap2tap column in table 22-5 . the scl tap is used to generate th e scl period and the sda tap is used to determine the delay from the falling edge of scl to the change of state of sda i.e. the sda hold time. figure 22-4. sda hold time table 22-6. i-bus tap and prescale values ibc2?0 scl tap (clocks) sda tap (clocks) 000 5 1 001 6 1 010 7 2 011 8 2 100 9 3 101 10 3 110 12 4 111 15 4 sda sda hold scl scl divider
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 402 freescale semiconductor figure 22-5. scl divider and sda hold the equation used to generate the divi der values from the ibfd bits is: scl divider = mul {2 (scl2tap + [(scl_tap ?1) tap2tap] + 2)} eqn. 22-1 the sda hold delay is equal to the cpu clock pe riod multiplied by the sda hold value shown in table 22-7 . the equation used to generate the sd a hold value from the ibfd bits is: sda hold = mul {scl2tap + [(sda_tap ? 1) tap2tap] + 3} eqn. 22-2 the equation for scl hold values to generate the start and stop conditions fr om the ibfd bits is: scl hold(start) = mul [scl2start + (scl_tap ? 1) tap2tap] eqn. 22-3 scl hold(stop) = mul [scl2stop + (scl_tap ? 1) tap2tap] eqn. 22-4 sda scl start condition stop condition scl hold(start) scl hold(stop)
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 403 table 22-7. i 2 c divider and hold values ibc7 ? 0 (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop) mul = 1 00 20 7 6 11 01 22 7 7 12 02 24 8 8 13 03 26 8 9 14 04 28 9 10 15 05 30 9 11 16 06 34 10 13 18 07 40 10 16 21 08 28 7 10 15 09 32 7 12 17 0a 36 9 14 19 0b 40 9 16 21 0c 44 11 18 23 0d 48 11 20 25 0e 56 13 24 29 0f 68 13 30 35 10 48 9 18 25 11 56 9 22 29 12 64 13 26 33 13 72 13 30 37 14 80 17 34 41 15 88 17 38 45 16 104 21 46 53 17 128 21 58 65 18 80 9 38 41 19 96 9 46 49 1a 112 17 54 57 1b 128 17 62 65 1c 144 25 70 73 1d 160 25 78 81 1e 192 33 94 97 1f 240 33 118 121 20 160 17 78 81 21 192 17 94 97 22 224 33 110 113 23 256 33 126 129 24 288 49 142 145 25 320 49 158 161 26 384 65 190 193 27 480 65 238 241 28 320 33 158 161 29 384 33 190 193 2a 448 65 222 225 2b 512 65 254 257 2c 576 97 286 289 2d 640 97 318 321 2e 768 129 382 385 2f 960 129 478 481 30 640 65 318 321 31 768 65 382 385 32 896 129 446 449 33 1024 129 510 513 34 1152 193 574 577 35 1280 193 638 641 36 1536 257 766 769 37 1920 257 958 961 38 1280 129 638 641 39 1536 129 766 769 3a 1792 257 894 897 3b 2048 257 1022 1025 3c 2304 385 1150 1153 3d 2560 385 1278 1281 3e 3072 513 1534 1537 3f 3840 513 1918 1921
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 404 freescale semiconductor mul = 2 40 40 14 12 22 41 44 14 14 24 42 48 16 16 26 43 52 16 18 28 44 56 18 20 30 45 60 18 22 32 46 68 20 26 36 47 80 20 32 42 48 56 14 20 30 49 64 14 24 34 4a 72 18 28 38 4b 80 18 32 42 4c 88 22 36 46 4d 96 22 40 50 4e 112 26 48 58 4f 136 26 60 70 50 96 18 36 50 51 112 18 44 58 52 128 26 52 66 53 144 26 60 74 54 160 34 68 82 55 176 34 76 90 56 208 42 92 106 57 256 42 116 130 58 160 18 76 82 59 192 18 92 98 5a 224 34 108 114 5b 256 34 124 130 5c 288 50 140 146 5d 320 50 156 162 5e 384 66 188 194 5f 480 66 236 242 60 320 28 156 162 61 384 28 188 194 62 448 32 220 226 63 512 32 252 258 64 576 36 284 290 65 640 36 316 322 66 768 40 380 386 67 960 40 476 482 68 640 28 316 322 69 768 28 380 386 6a 896 36 444 450 6b 1024 36 508 514 6c 1152 44 572 578 6d 1280 44 636 642 6e 1536 52 764 770 6f 1920 52 956 962 70 1280 36 636 642 71 1536 36 764 770 72 1792 52 892 898 73 2048 52 1020 1026 74 2304 68 1148 1154 75 2560 68 1276 1282 76 3072 84 1532 1538 77 3840 84 1916 1922 78 2560 36 1276 1282 79 3072 36 1532 1538 7a 3584 68 1788 1794 7b 4096 68 2044 2050 7c 4608 100 2300 2306 7d 5120 100 2556 2562 7e 6144 132 3068 3074 7f 7680 132 3836 3842 table 22-7. i 2 c divider and hold values (continued) ibc7 ? 0 (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 405 mul = 4 80 80 28 24 44 81 88 28 28 48 82 96 32 32 52 83 104 32 36 56 84 112 36 40 60 85 120 36 44 64 86 136 40 52 72 87 160 40 64 84 88 112 28 40 60 89 128 28 48 68 8a 144 36 56 76 8b 160 36 64 84 8c 176 44 72 92 8d 192 44 80 100 8e 224 52 96 116 8f 272 52 120 140 90 192 36 72 100 91 224 36 88 116 92 256 52 104 132 93 288 52 120 148 94 320 68 136 164 95 352 68 152 180 96 416 84 184 212 97 512 84 232 260 98 320 36 152 164 99 384 36 184 196 9a 448 68 216 228 9b 512 68 248 260 9c 576 100 280 292 9d 640 100 312 324 9e 768 132 376 388 9f 960 132 472 484 a0 640 68 312 324 a1 768 68 376 388 a2 896 132 440 452 a3 1024 132 504 516 a4 1152 196 568 580 a5 1280 196 632 644 a6 1536 260 760 772 a7 1920 260 952 964 a8 1280 132 632 644 a9 1536 132 760 772 aa 1792 260 888 900 ab 2048 260 1016 1028 ac 2304 388 1144 1156 ad 2560 388 1272 1284 ae 3072 516 1528 1540 af 3840 516 1912 1924 30 2560 260 1272 1284 b1 3072 260 1528 1540 b2 3584 516 1784 1796 b3 4096 516 2040 2052 b4 4608 772 2296 2308 b5 5120 772 2552 2564 b6 6144 1028 3064 3076 b7 7680 1028 3832 3844 b8 5120 516 2552 2564 b9 6144 516 3064 3076 ba 7168 1028 3576 3588 bb 8192 1028 4088 4100 bc 9216 1540 4600 4612 bd 10240 1540 5112 5124 be 12288 2052 6136 6148 bf 15360 2052 7672 7684 table 22-7. i 2 c divider and hold values (continued) ibc7 ? 0 (hex) scl divider (clocks) sda hold (clocks) scl hold (start) scl hold (stop)
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 406 freescale semiconductor 22.3.4 i 2 c bus control register (ibcr) offset 0x2 access: read/write any time 76543210 r mdis ibie mssl txrx noack 0 dmaen 0 wrsta reset10000000 figure 22-6. i 2 c bus control re gister (ibcr) table 22-8. ibcr field descriptions field description mdis module disable. this bit controls the software reset of the entire i 2 c bus module. 1 the module is reset and disabled. this is the power-on reset situation. when high, the interface is held in reset, but registers can st ill be accessed. status register bits (ibsr) are not valid when module is disabled. 0the i 2 c bus module is enabled. this bit must be cleared before any other ibcr bits have any effect note: if the i 2 c bus module is enabled in the middle of a byte transfer, the interface behaves as follows: slave mode ignores the current transfer on t he bus and starts operating whenever a subsequent start condition is detected. master mode will not be aware that the bus is busy, hence if a start cycle is initiated then the curre nt bus cycle may become corrupt. th is would ultimately result in either the current bus master or the i 2 c bus module losing arbitration, after which, bus operation would return to normal. ibie i-bus interrupt enable. 1 interrupts from the i 2 c bus module are enabled. an i 2 c bus interrupt occurs provided the ibif bit in the status register is also set. 0 interrupts from the i 2 c bus module are disabled. note that this does not clear any currently pending interrupt condition mssl master/slave mode select. upon reset, this bit is cl eared. when this bit is changed from 0 to 1, a start signal is generated on the bus and th e master mode is selected. when this bit is changed from 1 to 0, a stop signal is generated and the operation mode changes from master to slave. a stop signal should be generated only if the ibif flag is set. m ssl is cleared without generating a stop signal when the master loses arbitration. 1 master mode 0 slave mode txrx transmit/receive mode select. this bit selects the direction of master and slave transfers. when addressed as a slave this bit should be set by software according to the srw bit in the status register. in master mode this bit should be set according to t he type of transfer required. therefore, for address cycles, this bit will always be high. 1transmit 0 receive noack data acknowledge disable. this bit specifies the value driven onto sda during data acknowledge cycles for both master and slave receivers. the i 2 c module will always acknowledge address matches, provided it is enabled, regardless of the value of no ack. note that values written to this bit are only used when the i 2 c bus is a receiver, not a transmitter. 1 no acknowledge signal response is sent (i.e., acknowledge bit = 1) 0 an acknowledge signal will be sent out to the bus at the 9th clock bit after receiving one byte of data
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 407 22.3.5 i 2 c bus status register (ibsr) rsta repeat start. writing a 1 to this bit will generate a repeated start condition on the bus, provided it is the current bus master. this bit will always be read as a low. attempting a repeated start at the wrong time, if the bus is owned by another master, will result in loss of arbitration. 1 generate repeat start cycle 0 no effect dmaen dma enable. when this bit is set, the dma tx and rx lines will be asserted when the i 2 c module requires data to be read or written to the data r egister. no transfer done interrupts will be generated when this bit is set, however an interrupt will be generated if the loss of arbitration or addressed as slave conditions occur. the dma mode is only valid when the i 2 c module is configured as a master and the dma transfer still requires cpu intervention at the st art and the end of each frame of data. see the dma application information section for more details. 1 enable the dma tx/rx request signals 0 disable the dma tx/rx request signals offset 0x3 access: read-write 76543210 r tcf iaas ibb ibal 0 srw ibif rxak w w1c w1c reset10000000 figure 22-7. i 2 c bus status register (ibsr) table 22-9. ibsr field descriptions field description tcf transfer complete. while one byte of data is being transferred, this bit is cleared. it is set by the falling edge of the 9th clock of a byte transfer. note that th is bit is only valid during or immediately following a transfer to the i 2 c module or from the i 2 c module. 1 transfer complete 0 transfer in progress iaas addressed as a slave. when its own specific ad dress (i-bus address register) is matched with the calling address, this bit is set. the cpu is interrup ted provided the ibie is set. then the cpu needs to check the srw bit and set its tx/rx mode accordingly. writing to the i-bus control register clears this bit. 1 addressed as a slave 0 not addressed ibb bus busy. this bit indicates the status of the bus. when a start signal is detected, the ibb is set. if a stop signal is detected, ibb is cl eared and the bus enters idle state. 1bus is busy 0 bus is idle table 22-8. ibcr field descriptions (continued) field description
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 408 freescale semiconductor 22.3.6 i 2 c bus data i/o register (ibdr) in master transmit mode, when data is written to ibdr , a data transfer is initia ted. the most significant bit is sent first. in master receive mode, reading this re gister initiates next byte data receiving. in slave mode, the same functions are available after an address ma tch has occurred. note th at the ibcr[txrx] field must correctly reflect the desired direction of transf er in master and slave m odes for the transmission to begin. for instance, if the i 2 c is configured for master transmit but a master receive is desired, then reading the ibdr will not initiate the receive. ibal arbitration lost. the arbitration lost bit (ibal) is set by hardware when the arbitration procedure is lost. arbitration is lost in th e following circumstances: ? sda is sampled low when the master drives a high during an address or data transmit cycle. ? sda is sampled low when the master drives a high during the acknowledge bit of a data receive cycle. ? a start cycle is attempted when the bus is busy. ? a repeated start cycle is requested in slave mode. ? a stop condition is detected when the master did not request it. srw slave read/write. when iaas is set, this bit indi cates the value of the r/w command bit of the calling address sent from the master. this bit is only valid when the i-bus is in slave mode, a complete address transfer has occurred with an address match and no other transfers have been initiated. by programming this bit, the cpu can select slave tran smit/receive mode according to the command of the master. 1 slave transmit, master reading from slave 0 slave receive, master writing to slave ibif i-bus interrupt flag. the ibif bit is set when one of the following conditions occurs: ? arbitration lost (ibal bit set) ? byte transfer complete (tcf bit set) ? addressed as slave (iaas bit set) ? noack from slave (ms & tx bits set) ?i 2 c bus going idle (ibb high-low transition and enabled by biie) a processor interrupt request will be caused if the ibie bit is set. rxak received acknowledge. this is the value of sda during the acknowledge bit of a bus cycle. if the received acknowledge bit (rxak) is low, it indicate s an acknowledge signal ha s been received after the completion of 8 bits data transmission on the bus. if rxak is high, it means no acknowledge signal is detected at the 9th clock. this bit is valid only after transfer is complete. 1 no acknowledge received 0 acknowledge received offset 0x4 access: read/write any time 76543210 r data w reset00000000 figure 22-8. i 2 c bus data i/o register (ibdr) table 22-9. ibsr field descriptions (continued) field description
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 409 reading the ibdr will return th e last byte received while the i 2 c is configured in eith er master receive or slave receive modes. the ibdr does not refl ect every byte that is transmitted on the i 2 c bus, nor can software verify that a byte has been writte n to the ibdr correctly by reading it back. in master transmit mode, the first byte of data written to ibdr follow ing assertion of ms/sl is used for the address transfer and should comprise the calling address (in position d7?d1) concatenated with the required r/w bit (in position d0). 22.3.7 i 2 c bus interrupt configur ation register (ibic) 22.4 dma interface a simple dma interface is implemented so that the i 2 c can request data transf ers with minimal support from the cpu. dma mode is enabled by setting bit 1 in the control register. the dma interface is only valid when the i 2 c module is configured for master mode. offset 0x5 access: read/write any time 76543210 rbiie 1 1 this bit cannot be set in reset state, when i2c is in slave mode. it can be set to 1 only when i2c is in master mode. this information is missing from the spec. 0000000 w reset00000000 figure 22-9. i 2 c bus interrupt configuration register (ibic) table 22-10. ibic field descriptions field description biie bus idle interrupt enable bit. this configuration bit can be used to enable the generation of an interrupt once the i 2 c bus becomes idle. once this bit is set, an ibb high-low transition will set the ibif bit. this feature can be used to signal to the cpu the completion of a stop on the i 2 c bus. 1 bus idle interrupts enabled 0 bus idle interrupts disabled note:
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 410 freescale semiconductor figure 22-10. i 2 c module dma interface block diagram at least 3 bytes of data per fram e must be transferred from/to the slave when using dma mode, although in practice it will only be worthwhi le using the dma mode when there is a large number of data bytes to transfer per frame. two internal signals, tx request and rx request, ar e used to signal to a dma controller when the i 2 c module requires data to be written or read from the data register. input sync in/out data shift register address compare sda irq address clock control start stop arbitration control ctrl_reg freq_reg addr_reg status_reg data_reg addr_decode data_mux data bus scl dma request
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 411 22.5 functional description 22.5.1 i-bus protocol the i 2 c bus system uses a serial data line (sda) and a serial clock li ne (scl) for data transfer. all devices connected to it must have open drain or open collector outputs. a logical and function is exercised on both lines with external pullup resistors. the value of th ese resistors is system dependent. normally, a standard communication is composed of four parts: start signal, slave addr ess transmission, data transfer and stop signal. they are described briefly in the following sect ions and illustrated in figure 22-11 . figure 22-11. i 2 c bus transmission signals 22.5.1.1 start signal when the bus is free, that is, no ma ster device is engaging the bus (both scl and sd a lines are at logical high), a master may initiate communicati on by sending a start signal. as shown in figure 22-11 , a start signal is defined as a high-to-low transition of sda while scl is high. this signal denotes the beginning of a new data transf er (each data transfer may contain several bytes of da ta) and brings all slaves out of their idle states. scl sda start signal ack bit 12345678 msb lsb 12345678 msb lsb stop signal no scl sda 1234567 8 msb lsb 1 2 5 678 msb lsb repeated 34 9 9 ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w xxx d7 d6 d5 d4 d3 d2 d1 d0 calling address read/ data byte ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w ad7 ad6 ad5 ad4 ad3 ad2 ad1 r/w new calling address 99 xx ack bit write start signal start signal ack bit calling address read/ write stop signal no ack bit read/ write
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 412 freescale semiconductor figure 22-12. start and stop conditions 22.5.1.2 slave address transmission the first byte of data transfer im mediately after the start signal is the slave address transmitted by the master. this is a 7-bit calling address followed by a r/w bit. the r/w bit tells the slave the desired direction of data transfer. 1 = read transfer?the slave transmits data to the master 0 = write transfer?the master transmits data to the slave only the slave with a calling address that matche s the one transmitted by the master will respond by sending back an acknowledge bit. this is done by pul ling the sda low at the 9th clock (see figure 22-11 ). no two slaves in the system may have the same address. if the i 2 c bus is master, it must not transmit an address that is equal to it s own slave address. the i 2 c bus cannot be master and slave at the same time. however, if arbitration is lost during an address cycle the i 2 c bus will revert to slave mode and operate correctly, even if it is being addressed by another master. 22.5.1.3 data transfer once successful slave addressing is achieved, the data transfer can proceed byte-by-byte in a direction specified by the r/w bit sent by the calling master. all transfers that come after an addres s cycle are referred to as data transf ers, even if they carry sub-address information for the slave device. each data byte is 8 bits long. data may be changed only while scl is lo w and must be held stable while scl is high as shown in figure 22-11 . there is one clock pulse on scl fo r each data bit, the msb being transferred first. each data byte must be followed by an acknowledge bit, which is signaled from the receiving device by pulling the sda lo w at the ninth clock. therefore, one complete data byte transfer needs 9 clock pulses. sda scl start condition stop condition
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 413 if the slave receiver does not acknowledge the master, the sda line must be left high by the slave. the master can then generate a stop signal to abort the da ta transfer or a start signal (repeated start) to commence a new calling. if the master receiver doe s not acknowledge the slave transmitter after a byte transmission, it means 'end of data' to the slave, so the slave releases the sda li ne for the master to genera te a stop or start signal. 22.5.1.4 stop signal the master can terminate the comm unication by generating a stop signa l to free the bus. however, the master may generate a start signal followed by a calling command without generating a stop signal first. this is called repeated start. a stop signal is defined as a low-to-hi gh transition of sda while scl is at logical 1 (see figure 22-11 ). the master can generate a stop even if the slave has generated an acknowledge, at which point the slave must release the bus. 22.5.1.5 repeated start signal as shown in figure 22-11 , a repeated start signal is a start signal generate d without first generating a stop signal to terminate the communication. this is used by the master to communicate with another slave or with the same slave in different mode (transmit/receive mode) without releasing the bus. 22.5.1.6 arbitration procedure the inter-ic bus is a true multi-master bus that allows more than one master to be connected on it. if two or more masters try to control the bus at the same time, a clock sync hronization procedur e determines the bus clock, for which the low period is equal to the longest clock low pe riod and the high is equal to the shortest one among the masters. the relative priority of the contending masters is determined by a data arbitration procedure. a bus master loses arbitration if it transmits logic 1 whil e another master transmits logic 0. the losing masters immedi ately switch over to slave receiv e mode and stop driving the sda output. in this case, the transitio n from master to slave mode doe s not generate a stop condition. meanwhile, a status bit is set by hard ware to indicate loss of arbitration. 22.5.1.7 clock synchronization since wire-and logic is performed on the scl line, a high-to-low tran sition on the scl line affects all the devices connected on the bus. the devices start counting their low pe riod and once a device's clock has gone low, it holds the scl line lo w until the clock high state is reache d. however, the change of low to high in this device clock may not cha nge the state of the scl line if anot her device clock is still within its low period. therefore, synchronized clock scl is he ld low by the device with the longest low period. devices with shorter low periods enter a high wait state during this time (see figure 22-13 ). when all devices concerned have counted off their low period, the synchronized clock scl line is released and pulled high. there is then no difference between the de vice clocks and the state of the scl line and all the devices start counting their high peri ods. the first device to complete its high period pulls the scl line low again.
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 414 freescale semiconductor figure 22-13. i 2 c bus clock synchronization 22.5.1.8 handshaking the clock synchronization mechanism can be used as a handshake in data transf er. slave devices may hold the scl low after completion of one byt e transfer (9 bits). in such cases , it halts the bus clock and forces the master clock into wait state un til the slave releases the scl line. 22.5.1.9 clock stretching the clock synchronization mechanism can be used by slaves to slow down the bit rate of a transfer. after the master has driven scl low, the slave can drive scl low for the required period and then release it. if the slave scl low period is greater than the master scl low period then the resulting scl bus signal low period is stretched. 22.5.2 interrupts 22.5.2.1 general the i 2 c uses only one interrupt vector. table 22-11. interrupt summary interrupt offset vector pr iority source description i 2 c interrupt ???ibal, tcf, iaas, ibb bits in ibsr register when any of ibal, tcf or iaas bi ts is set an interrupt may be caused based on arbitration lost, transfer complete or address detect conditions. if enabled by biie, the deassertion of ibb can also cause an interrupt, indicating that the bus is idle. scl1 scl2 scl internal counter reset wait start counting high period
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 415 22.5.2.2 interrupt description there are five types of internal interrupts in the i 2 c. the interrupt service routine can determine the interrupt type by reading the status register. the i 2 c interrupt can be generated on ? arbitration lost condition (ibal bit set) ? byte transfer condition (tcf bit set and dmaen bit not set) ? address detect condition (iaas bit set) ? no acknowledge from slave received when expected ? bus going idle (ibb bit not set) the i 2 c interrupt is enabled by the ibie bit in the i 2 c control register. it must be cleared by writing 1 to the ibif bit in the interrupt servi ce routine. the bus going idle interr upt needs to be additionally enabled by the biie bit in the ibic register. 22.6 initialization/application information 22.6.1 i 2 c programming examples 22.6.1.1 initialization sequence reset will put the i 2 c bus control register to its default state. before the in terface can be used to transfer serial data, an initializ ation procedure must be carried out, as follows: 1. update the frequency divider re gister (ibfd) and sel ect the required divisi on ratio to obtain scl frequency from system clock. 2. update the i 2 c bus address register (ibad) to define its slave address. 3. clear the ibcr[mdis] field to enable the i 2 c interface system. 4. modify the bits of the i 2 c bus control register (ibcr) to select master/slave mode, transmit/receive mode and interr upt enable or not. op tionally also modify the bits of the i 2 c bus interrupt configuration register (ibic) to further refine the interrupt behavior. 22.6.1.2 generation of start after completion of the initialization procedure, seri al data can be transmitte d by selecting the 'master transmitter' mode. if the device is connected to a multi-master bus system, the state of the i 2 c bus busy bit (ibb) must be tested to check whether the serial bus is free. if the bus is free (ibb=0), the start condition and the fi rst byte (the slave address) can be sent. the data written to the data register comprises the slave calli ng address and the lsb, which is set to indicate the direction of transfer required from the slave. the bus free time (i.e., the time between a stop condition and the fo llowing start condition) is built into the hardware that generates the start cycle. depending on the relative fr equencies of the system
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 416 freescale semiconductor clock and the scl period, it may be necessary to wait until the i 2 c is busy after writi ng the calling address to the ibdr before proceeding with the following instru ctions. this is illustrated in the following example. an example of the sequence of events that generates the start signal a nd transmits the fi rst byte of data (slave address) is shown below: while (bit 5, ibsr ==1)// wait in loop for ibb flag to clear bit4 and bit 5, ibcr = 1// set transmit and master mode, i.e. generate start condition ibdr = calling_address// send the calling address to the data register while (bit 5, ibsr ==0)// wait in loop for ibb flag to be set 22.6.1.3 post-transfer software response transmission or reception of a byte will set the data transferring bit (tcf) to 1, which indicates one byte communication is finished. the i 2 c bus interrupt bit (ibif) is set also; an interrupt will be generated if the interrupt function is enabled during in itialization by setting the ibie bit. the ibif (i nterrupt flag) can be cleared by writing 1 (in the interrupt service routine, if interrupts are used). the tcf bit will be cleared to indica te data transfer in progress whenever data register is written to in transmit mode, or during reading out from data register in receive mode. the tcf bit should not be used as a data transfer complete flag as the flag timi ng is dependent on a number of factors including the i 2 c bus frequency. this bit may not conclu sively provide an indica tion of a transfer complete situation. it is recommended that transfer complete situ ations are detected using the ibif flag software may service the i 2 c i/o in the main program by monitoring the ibif bit if the interrupt function is disabled. note that polling should monitor the ibif bit rather than the tcf bit since their operation is different when arbitration is lost. note that when a transfer complete interrupt occurs at the end of the a ddress cycle, the master will always be in transmit mode, i.e. the address is transmitted. if master r eceive mode is requir ed, indicated by r/w bit sent with slave calling address, then the tx/rx bit at master side should be t oggled at this stage. if master does not receive an ack from slave, then transmission must be re-i nitiated or terminated. in slave mode, iaas bit will get set in ibsr if sl ave address (ibad) matches the master calling address. this is an indication that mast er-slave data communication can no w start. during address cycles (iaas=1), the srw bit in the status re gister is read to determine the di rection of the subsequent transfer and the tx/rx bit is programmed accordingly. for slav e mode data cycles (iaas=0), the srw bit is not valid. the tx/rx bit in the control regi ster should be read to determine th e direction of the current transfer. 22.6.1.4 transmit/receive sequence follow this sequence in case of master transmit (address/data): 1. clear ibsr[ibif]. 2. write data in data register (ibdr). 3. ibsr[tcf] bit will get cleared when transfer is in progress. 4. ibsr[tcf] bit will get set when transfer is complete. 5. wait for ibsr[ibif] to get set, then r ead ibsr register to determine its source: ? tcf = 1, transfer is complete.
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 417 ? no acknowledge condition (rxak = 1) is found. ? ibb = 0, bus has transitioned from busy to idle state. ? if ibb = 1, ignore check of arbitration loss (ibal = 1). ? ignore address detect (iaas = 1) for ma ster mode (valid only for slave mode). 6. f) check rxak in ibsr for an acknowledge from slave. follow this sequence in case of slave receive (address/data): 1. clear ibsr[ibif]. 2. ibsr[tcf] will get cleared when transf er is in progress for address transfer. 3. ibsr[tcf] will get set when transfer is complete. 4. wait for ibsr[ibif] to get set. then re ad ibsr register to determine its source: ? address detect has occurred (iaas = 1)?determination of slave mode. 5. clear ibif. 6. wait until ibsr[tcf] bit gets cleared (that is, ?trans fer under progress? condition is reached for data transfer). 7. wait until ibsr[tcf] bit gets cleared (proof that transfer completes from ?transfer under progress? state). 8. wait until ibsr[ibif] bit gets set. to find its source, check if: ? tcf = 1 i.e. reception is complete ? ibsr[ibb] = 0, that is, bus has transitioned from busy to idle state ? ignore arbitration loss (ibal = 1) for ibb = 1 ? ignore no acknowledge condition (rxak = 1) for receiver 9. read the data register (ibdr) to determine data received from master. sequence followed in case of slav e transmit (steps 1?4 of slave r eceive for address detect, followed by 1?6 of master transmit for data transmit). sequence followed in case of master receive (ste ps 1?6 of master transmit for address dispatch, followed by 5?8 of slave receive for data receive). 22.6.1.5 generation of stop a data transfer ends with a stop signal generated by the 'master' devi ce. a master transmitter can simply generate a stop signal afte r all the data has been transmitted. th e following is an example showing how a stop condition is generated by a master transmitter. if (tx_count == 0) or// check to see if all data bytes have been transmitted (bit 0, ibsr == 1) {// or if no ack generated clear bit 5, ibcr// generate stop condition } else { ibdr = data_to_transmit// write byte of data to data register tx_count --// decrement counter }// return from interrupt
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 418 freescale semiconductor if a master receiver wants to te rminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data, which can be done by setting the transmit acknowledge bit (txak) before reading the 2nd last byte of data. before readi ng the last byte of data, a stop signal must first be generated. the following is an example showing ho w a stop signal is generated by a master receiver. rx_count --// decrease the rx counter if (rx_count ==1)// 2nd last byte to be read ? bit 3, ibcr = 1// disable ack if (rx_count == 0)// last byte to be read ? bit 5, ibcr = 0// generate stop signal else data_received = ibdr// read rx data and store 22.6.1.6 generation of repeated start at the end of data transfer, if the master still wa nts to communicate on the bus , it can generate another start signal followed by another slave address wi thout first generating a stop signal. a program example is as shown. bit 2, ibcr = 1// generate another start ( restart) ibdr == calling_address// transmit the calling address 22.6.1.7 slave mode in the slave interrupt service routin e, the module addressed as slave bit (iaas) shoul d be tested to check if a calling of its own address has just been re ceived. if iaas is set, software should set the transmit/receive mode sel ect bit (tx/rx bit of ib cr) according to the r/w co mmand bit (srw). writing to the ibcr clears iaas automatically. note that the onl y time iaas is read as set is from the interrupt at the end of the address cycle wher e an address match occurred. interr upts resulting from subsequent data transfers will have iaas cleared. a data transfer may now be initiate d by writing information to ibdr for slave transmits or dummy readin g from ibdr in slave receive m ode. the slave will drive scl low in-between byte transfers scl is released when the ibdr is accessed in the required mode. in slave transmitter routine, the r eceived acknowledge bit (rxak) must be tested before transmitting the next byte of data. setting rxak means an 'end of data' signal from th e master receiver, after which it must be switched from transmitter mode to receiver mode by software. a dummy read then releases the scl line so that the master can generate a stop signal. 22.6.1.8 arbitration lost if several masters try to engage the bus simultan eously, only one master wins and the others lose arbitration. the devices that lost arbitration are immediately switch ed to slave receive mode by the hardware. their data output to the sda line is stopped, but scl is still generated until the end of the byte during which arbitration was lo st. an interrupt occurs at the falling e dge of the ninth cloc k of this transfer with ibal=1 and ms/sl=0. if one master attempts to start transmission, while the bus is being engaged by another master, the hardware will inhibit the transmission, switch th e ms/sl bit from 1 to 0 without generating a stop condition, generate an interrupt to cpu and set the ibal to indicate that the attempt to engage the bus is failed. when considering these cases, the slave service routine should test the ibal first and the software should clear the ibal bit if it is set.
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 419 figure 22-14. flow chart of typical i 2 c interrupt routine clear master mode ? tx/rx ? last byte transmitted ? rxak=0 ? end of addr cycle (master rx) ? write next byte to ibdr switch to rx mode dummy read from ibdr generate stop signal read data from ibdr and store set txak =1 generate stop signal 2nd last byte to be read ? last byte to be read ? arbitration lost ? clear ibal iaas=1 ? iaas=1 ? srw=1 ? tx/rx ? set tx mode write data to ibdr set rx mode dummy read from ibdr ack from receiver ? tx next byte read data from ibdr and store switch to rx mode dummy read from ibdr rti yn y y y y y y y y y n n n n n n n n n y tx rx rx tx (write) (read) n ibif address transfer data transfer
chapter 22 inter-integrated circuit bus controller module (i 2 c) MPC5606BK microcontroller reference manual, rev. 2 420 freescale semiconductor this page is intent ionally left blank.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 421 chapter 23 lin controller (linflex) 23.1 introduction the linflex (local interconnect network flexible) controller interfaces the lin network and supports the lin protocol versions 1.3; 2.0 and 2.1; and j2602 in both master a nd slave modes. linflex includes a lin mode that provides additiona l features (compared to standard uart) to ease lin implementation, improve system robustness, minimize cpu load and allow slave node resynchronization. 23.2 main features 23.2.1 lin mode features ? supports lin protocol versions 1.3, 2.0, 2.1, and j2602 ? master mode with aut onomous message handling ? classic and enhanced checksum calculation and check ? single 8-byte buffer for transmission/reception ? extended frame mode for in-app lication programming (iap) purposes ? wake-up event on dominant bit detection ? true lin field state machine ? advanced lin error detection ? header, response, and frame timeout ? slave mode ? autonomous header handling ? autonomous transmit/receive data handling ? lin automatic resynchronization, allowing operation with 16 mhz fast internal rc oscillator as clock source ? 16 identifier filters for autonom ous message handling in slave mode ? peripheral dma request sour ces possible from linflex 23.2.2 uart mode features ? full duplex communication ? 8- or 9-bit with parity ? 4-byte buffer for reception, 4-byte buffer for transmission ? 8-bit counter for timeout management 23.2.3 features common to lin and uart ? fractional baud rate generator
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 422 freescale semiconductor ? three operating modes for power saving and configuration registers lock: ? initialization ? normal ?sleep ? two test modes: ? loop back ?self test ? maskable interrupts 23.3 general description the increasing number of communicat ion peripherals embedded on microc ontrollers, for example can, lin, and spi, requires more and more cpu res ources for communication ma nagement. even a 32-bit microcontroller is overloaded if it s peripherals do not provide high-le vel features to autonomously handle the communication. even though the lin protocol with a maximum baud rate of 20 kbit/s is relatively slow, it still generates a non-negligible load on the cpu if the lin is im plemented on a standard uart, as usually the case. to minimize the cpu load in master mode, li nflex handles the lin messages autonomously. in master mode, once the software has triggered the header transm ission, linflex does not request any software intervention until the next header trans mission request in transmis sion mode or until the checksum reception in reception mode. to minimize the cpu load in slave mode, li nflex requires software intervention only to: ? trigger transmission or reception or data discard depending on the identifier ? write data into the buffer (tra nsmission mode) or read data fr om the buffer (reception mode) after checksum reception if filter mode is activated for sl ave mode, linflex requires software in tervention only to write data into the buffer (transmission mode) or read data from the buffer (reception mode) the software uses the control, stat us, and configuration registers to: ? configure lin parameters (for example, baud rate or mode) ? request transmissions ? handle receptions ? manage interrupts ? configure lin error and timeout detection ? process diagnostic information the message buffer stores transm itted or received lin frames.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 423 figure 23-1. lin topology network figure 23-2. linflex block diagram 23.4 fractional baud rate generation the baud rates for the receiver and transmitter are both set to the sa me value as programmed in the mantissa (linibrr) and fr action (linfbrr) registers . lin master node lin slave node 1 lin slave node n lin lin lin rx tx lin transceiver linflex controller mcu lin bus application lin protocol handler register model / application interface lin status baud rate filter configuration message slave lin control configuration message handler master message handler identifier filters (1) control status buffer interface 1. filter activation optional
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 424 freescale semiconductor eqn. 23-1 lfdiv is an unsigned fixed point num ber. the 12-bit mantissa is code d in the linibrr and the fraction is coded in the linfbrr. the following examples show how to derive lf div from linibrr and li nfbrr register values: example 23-1. deriving lfdiv from linibrr and linfbrr register values if linibrr = 27d and linfbrr = 12d, then mantissa (lfdiv) = 27d fraction (lfdiv) = 12/16 = 0.75d therefore lfdiv = 27.75d example 23-2. programming lfdiv from linibrr and linfbrr register values to program lfdiv = 25.62d, linfbrr = 16 0.62 = 9.92, nearest real number 10d = 0xa linibrr = mantissa (25.620d) = 25d = 0x19 note the baud counters are updated with the ne w value of the baud registers after a write to linibrr. hence the baud re gister value must not be changed during a transaction. the linfbrr (cont aining the fraction bits) must be programmed before the linibrr. note lfdiv must be greater than or equal to 1.5d, i.e. linibrr = 1 and linfbrr = 8. therefore, the ma ximum possible baudrate is fperiph_set_1_clk / 24. table 23-1. error calculation for programmed baud rates baud rate f periph_set_1_clk = 64 mhz f periph_set_1_clk = 16 mhz actual value programmed in the baud rate register % error = (calculated ? desired) baud rate / desired baud rate actual value programmed in the baud rate register % error = (calculated ? desired) baud rate / desired baud rate linibrr linfbrr linibrr linfbrr 2400 2399.97 1666 11 ?0.001 2399.88 416 11 ?0.005 9600 9599.52 416 11 ?0.005 9598.08 104 3 ?0.02 10417 10416.7 384 0 ?0.003 10416.7 96 0 ?0.003 tx/ rx baud = f periph_set_1_clk (16 lfdiv)
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 425 23.5 operating modes linflex has three main operating mo des: initialization, no rmal, and sleep. after a hardware reset, linflex is in sleep mode to reduce power consum ption. the software instructs linflex to enter initialization mode or sleep mode by setting the init bit or sleep bit in the lincr1. figure 23-3. linflex operating modes 19200 19201.9 208 5 0.01 19207.7 52 1 0.04 57600 57605.8 69 7 0.01 57554 17 6 ?0.08 115200 115108 34 12 ?0.08 115108 8 11 ?0.08 230400 230216 17 6 ?0.08 231884 4 5 0.644 460800 460432 8 11 ?0.08 457143 2 3 ?0.794 921600 927536 4 5 0.644 941176 1 1 2.124 table 23-1. error calculation for programmed baud rates (continued) baud rate f periph_set_1_clk = 64 mhz f periph_set_1_clk = 16 mhz actual value programmed in the baud rate register % error = (calculated ? desired) baud rate / desired baud rate actual value programmed in the baud rate register % error = (calculated ? desired) baud rate / desired baud rate linibrr linfbrr linibrr linfbrr sleep initialization normal s l e e p s l e e p * i n i t reset s l e e p l i n r x d o m i n a n t s l e e p * i n i t sl eep * i n i t
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 426 freescale semiconductor 23.5.1 initialization mode the software can be initialized while the hardware is in initialization mode. to enter this mode the software sets the init bit in the lincr1. to exit initialization mode, the software clears the init bit. while in initialization mode, all message transfers to and from the lin bus are stopped and the status of the lin bus output lintx is recessive (high). entering initialization mode does not cha nge any of the configuration registers. to initialize the linflex controller, the software sel ects the mode (lin master, lin slave or uart), sets up the baud rate register a nd, if lin slave mode with fi lter activation is selected, initializes the identifier list. 23.5.2 normal mode once initilization is complete, software clears the init bit in the lincr1 to put the hardware into normal mode. 23.5.3 low power mode (sleep) to reduce power consumption, linfle x has a low power mode called sl eep mode. to enter sleep mode, software sets the sleep bit in the lincr1. in this mode, the linflex clock is stopped. consequently, the linflex will not update the stat us bits but software can still access the linflex registers. linflex can be awakened (exit slee p mode) either by software clearing the sleep bit or on detection of lin bus activity if automatic wake-up mode is enabled (awum bit is set). on lin bus activity detection, hardware automatical ly performs the wake-up sequence by clearing the sleep bit if the awum bit in the lincr1 is set. to exit from sleep mode if the awum bit is cleared, software clears the sleep bit when a wake-up event occurs. 23.6 test modes two test modes are available to the user: loop back mode and self test mode. they can be selected by the lbkm and sftm bits in the lincr 1. these bits must be configured while linflex is in initialization mode. once one of the two test m odes has been selected, linflex mu st be started in normal mode. 23.6.1 loop back mode linflex can be put in loop back mo de by setting the lbkm bit in th e lincr. in loop back mode, the linflex treats its own transmitted messages as received messages.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 427 figure 23-4. linflex in loop back mode this mode is provided for self test functions. to be independent of external events, the lin core ignores the linrx signal. in this mode, the linflex performs an internal feedback from its tx output to its rx input. the actual value of the linrx input pin is disregarded by the linflex. the transmitted messages can be monitored on the lintx pin. 23.6.2 self test mode linflex can be put in self test mode by setting the lbkm and sft m bits in the lincr. this mode can be used for a hot self test, meanin g the linflex can be tested as in loop back mode but without affecting a running lin system connected to the lintx and linrx pins. in this mode, the linrx pin is disconnected from the linflex and the lintx pin is held recessive. figure 23-5. linflex in self test mode 23.7 memory map and registers description 23.7.1 memory map see chapter 3, memory map , of this reference manual for the ba se addresses for the linflex modules. table 23-2 shows the linflex memory map. lintx linrx linflex tx rx linflex lintx linrx tx rx =1
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 428 freescale semiconductor table 23-2. linflex memory map address offset register location 0x0000 lin control register 1 (lincr1) on page 429 0x0004 lin interrupt enable register (linier) on page 432 0x0008 lin status register (linsr) on page 433 0x000c lin error status register (linesr) on page 436 0x0010 uart mode control register (uartcr) on page 437 0x0014 uart mode status register (uartsr) on page 438 0x0018 lin timeout control status register (lintcsr) on page 440 0x001c lin output compare register (linocr) on page 441 0x0020 lin timeout control register (lintocr) on page 442 0x0024 lin fractional baud rate register (linfbrr) on page 442 0x0028 lin integer baud rate register (linibrr) on page 443 0x002c lin checksum field register (lincfr) on page 444 0x0030 lin control register 2 (lincr2) on page 444 0x0034 buffer identifier register (bidr) on page 445 0x0038 buffer data register lsb (bdrl) 1 on page 446 0x003c buffer data register msb (bdrm) 2 on page 447 0x0040 identifier filter enable register (ifer) on page 448 0x0044 identifier filter match index (ifmi) on page 449 0x0048 identifier filter mode register (ifmr) on page 450 0x004c identifier filter c ontrol register 0 (ifcr0) on page 451 0x0050 identifier filter c ontrol register 1 (ifcr1) on page 452 0x0054 identifier filter c ontrol register 2 (ifcr2) on page 452 0x0058 identifier filter c ontrol register 3 (ifcr3) on page 452 0x005c identifier filter c ontrol register 4 (ifcr4) on page 452 0x0060 identifier filter c ontrol register 5 (ifcr5) on page 452 0x0064 identifier filter c ontrol register 6 (ifcr6) on page 452 0x0068 identifier filter c ontrol register 7 (ifcr7) on page 452 0x006c identifier filter c ontrol register 8 (ifcr8) on page 452 0x0070 identifier filter c ontrol register 9 (ifcr9) on page 452 0x0074 identifier filter c ontrol register 10 (ifcr10) on page 452 0x0078 identifier filter c ontrol register 11 (ifcr11) on page 452 0x007c identifier filter c ontrol register 12 (ifcr12) on page 452 0x0080 identifier filter c ontrol register 13 (ifcr13) on page 452
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 429 23.7.1.1 lin control register 1 (lincr1) 0x0084 identifier filter c ontrol register 14 (ifcr14) on page 452 0x0088 identifier filter c ontrol register 15 (ifcr15) on page 452 0x008c?0x000f reserved 1 lsb: least significant byte 2 msb: most significant byte offset: 0x0000 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ccd cfd lase awum mbl bf sftm lbkm mme sbdt rblm sleep init w reset0000000010000010 figure 23-6. lin control register 1 (lincr1) table 23-3. lincr1 field descriptions field description ccd checksum calculation disable this bit disables the checksum calculation (see table 23-4 ). 0 checksum calculation is done by hardware. when this bit is 0, the lincfr is read-only. 1 checksum calculation is disabled. when this bi t is set the lincfr is read/write. user can program this register to send a software-calculated crc (provided cfd is 0). note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. cfd checksum field disable this bit disables the checksum field transmission (see ta bl e 2 3 - 4 ). 0 checksum field is sent after the required number of data bytes is sent. 1 no checksum field is sent. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. lase lin slave automatic resynchronization enable 0 automatic resynchronization disable. 1 automatic resynchronization enable. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. table 23-2. linflex memory map (continued) address offset register location
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 430 freescale semiconductor awum automatic wake-up mode this bit controls the behavior of the linflex hardware during sleep mode. 0 the sleep mode is exited on software request by clearing the sleep bit of the lincr. 1 the sleep mode is exited automatically by hardware on linrx dominant state detection. the sleep bit of the lincr is cleared by hardware whenever wuf bit in the linsr is set. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. mbl lin master break length this field indicates the break length in master mode (see ta b l e 2 3 - 5 ). note: this field can be written in initialization mode onl y. it is read-only in normal or sleep mode. bf bypass filter 0 no interrupt if identifier does not match any filter. 1 an rx interrupt is generated on identifier not matching any filter. note: ? if no filter is activated, this bit is reserved and always reads 1. ? this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sftm self test mode this bit controls the self te st mode. for more details, see section 23.6.2, self test mode. 0 self test mode disable. 1 self test mode enable. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. lbkm loop back mode this bit controls the loop back mode. for more details see section 23.6.1, loop back mode. 0 loop back mode disable. 1 loop back mode enable. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode mme master mode enable 0 slave mode enable. 1 master mode enable. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. sbdt slave mode break detection threshold 0 11-bit break. 1 10-bit break. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. rblm receive buffer locked mode 0 receive buffer not locked on overrun. once the slave receive buffer is full the next incoming message overwrites the previous one. 1 receive buffer locked against overrun. once the receive buffer is full the next incoming message is discarded. note: this bit can be written in initialization mode on ly. it is read-only in normal or sleep mode. sleep sleep mode request this bit is set by software to request linflex to enter sleep mode. this bit is cleared by software to exit sleep mode or by hardware if the awum bit in lincr1 and the wuf bit in linsr are set (see ta b l e 2 3 - 6 ). init initialization request the software sets this bit to switch hardware into initializati on mode. if the sleep bit is reset, linflex enters normal mode when clearing the init bit (see table 23-6 ). table 23-3. lincr1 field descriptions (continued) field description
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 431 table 23-4. checksum bits configuration cfd ccd lincfr checksum sent 1 1 read/write none 1 0 read-only none 0 1 read/write programmed in lincfr by bits cf[0:7] 0 0 read-only hardware calculated table 23-5. lin master break length selection mbl length 0000 10-bit 0001 11-bit 0010 12-bit 0011 13-bit 0100 14-bit 0101 15-bit 0110 16-bit 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit 1111 50-bit table 23-6. operating mode selection sleep init operating mode 1 0 sleep (reset value) x 1 initialization 00normal
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 432 freescale semiconductor 23.7.1.2 lin interrupt enable register (linier) offset: 0x0004 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szie ocie beie ceie heie 00 feie boie lsie wuie dbfie dbeie drie dtie hrie w reset0000000000000000 figure 23-7. lin interrupt enable register (linier) table 23-7. linier field descriptions field description szie stuck at zero interrupt enable 0 no interrupt when szf bit in linesr or uartsr is set. 1 interrupt generated when szf bit in linesr or uartsr is set. ocie output compar e interrupt enable 0 no interrupt when ocf bit in linesr or uartsr is set. 1 interrupt generated when ocf bit in linesr or uartsr is set. beie bit error in terrupt enable 0 no interrupt when bef bit in linesr is set. 1 interrupt generated when bef bit in linesr is set. ceie checksum error interrupt enable 0 no interrupt on checksum error. 1 interrupt generated when checksum error flag (cef) in linesr is set. heie header error interrupt enable 0 no interrupt on break delimiter error, synch field error, identifier field error. 1 interrupt generated on break delimiter error, synch field error, identifier field error. feie framing error interrupt enable 0 no interrupt on framing error. 1 interrupt generated on framing error. boie buffer overrun interrupt enable 0 no interrupt on buffer overrun. 1 interrupt generated on buffer overrun. lsie lin state interrupt enable 0 no interrupt on lin state change. 1 interrupt generated on lin state change. this interrupt can be used for debugging purposes. it has no status flag but is reset when writing 1111 into lins[0:3] in the linsr.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 433 23.7.1.3 lin status register (linsr) wuie wake-up interrupt enable 0 no interrupt when wuf bit in linsr or uartsr is set. 1 interrupt generated when wuf bit in linsr or uartsr is set. dbfie data buffer full interrupt enable 0 no interrupt when buffer data register is full. 1 interrupt generated when dat a buffer register is full. dbeie data buffer empty interrupt enable 0 no interrupt when buffer data register is empty. 1 interrupt generated when data buffer register is empty. drie data reception complete interrupt enable 0 no interrupt when data reception is completed. 1 interrupt generated when data received fl ag (drf) in linsr or uartsr is set. dtie data transmitted interrupt enable 0 no interrupt when data transmission is completed. 1 interrupt generated when dat a transmitted flag (dtf) is set in linsr or uartsr. hrie header received interrupt enable 0 no interrupt when a valid lin header has been received. 1 interrupt generated when a valid lin header has be en received, that is, hrf bit in linsr is set. offset: 0x0008 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rlins 00rmb0 rbsy rps wuf dbff dbef drf dtf hrf ww1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000001000000 figure 23-8. lin status register (linsr) table 23-7. linier field descriptions (continued) field description
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 434 freescale semiconductor t table 23-8. linsr field descriptions field description lins lin modes / normal mode states 0000: sleep mode linflex is in sleep mode to save power consumption. 0001: initialization mode linflex is in initialization mode. normal mode states 0010: idle this state is entered on several events: ? sleep bit and init bit in lincr1 have been cleared by software, ? a falling edge has been received on rx pin and awum bit is set, ? the previous frame reception or transmission has been completed or aborted. 0011: break in slave mode, a falling edge followed by a dominant state has been detected. receiving break. note: in slave mode, in case of error new lin state can be either idle or break depending on last bit state. if last bit is dominan t new lin state is break, otherwise idle. in master mode, break transmission ongoing. 0100: break delimiter in slave mode, a valid break has been detected. see section 23.7.1.1, lin control register 1 (lincr1) for break length configuration (10-bit or 11-bit). waiting for a rising edge. in master mode, break transmission has been completed. break delimiter transmission is ongoing. 0101: synch field in slave mode, a valid break delimiter has been detected (recessive state for at least one bit time). receiving synch field. in master mode, synch field transmission is ongoing. 0110: identifier field in slave mode, a valid synch field has been received. receiving identifier field. in master mode, identifier transmission is ongoing. 0111: header reception/transmission completed in slave mode, a valid header has been received and identifier field is available in the bidr. in master mode, header transmission is completed. 1000: data reception/transmission response reception/transmission is ongoing. 1001: checksum data reception/transmission completed. checksum reception/transmission ongoing. in uart mode, only the following stat es are flagged by the lin state bits: ?init ? sleep ?idle ? data transmission/reception rmb release message buffer 0 buffer is free. 1 buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. rbsy receiver busy flag 0 receiver is idle 1 reception ongoing note: in slave mode, after header reception, if bidr [dir] = 0 and reception starts then this bit is set. in this case, user cannot program lincr2[dtrq] = 1.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 435 rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes. wuf wake-up flag this bit is set by hardware and indicates to the software that linflex has detected a falling edge on the linrx pin when: ? slave is in sleep mode ? master is in sleep mode or idle state this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if wuie bit in linier is set. dbff data buffer full flag this bit is set by hardware and indicates the buffer is full. it is set only when receiving extended frames (dfl > 7). this bit must be cleared by software. it is reset by hardware in initialization mode. dbef data buffer empty flag this bit is set by hardware and indicates the buffer is empty. it is set only when transmitting extended frames (dfl > 7). this bit must be cleared by software, once buffer has been filled again, in order to start transmission. this bit is reset by hardwa re in initialization mode. drf data reception completed flag this bit is set by hardware and indi cates the data reception is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error or framing error. dtf data transmission completed flag this bit is set by hardware and indicates the data transmission is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error if iobe bit is reset. hrf header reception flag this bit is set by hardware and indicates a valid header reception is completed. this bit must be cleared by software. this bit is reset by hardware in initialization mode and at end of completed or aborted frame. note: if filters are enabled, this bit is set only when i dentifier software filteri ng is required, that is to say: ? all filters are inactive and bf bit in lincr1 is set ? no match in any filter and bf bit in lincr1 is set ? tx filter match table 23-8. linsr field descriptions (continued) field description
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 436 freescale semiconductor 23.7.1.4 lin error status register (linesr) offset: 0x000c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf bef cef sfef bdef idpef fef bof 0 0 0 000nf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 23-9. lin error status register (linesr) table 23-9. linesr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is domina nt for more than a 100-bit time. if the dominant state continues, szf flag is set again afte r 87-bit time. it is cleared by software. ocf output compare flag 0 no output compare event occurred 1 the content of the counter has matched the conten t of oc1[0:7] or oc2[0:7] in linocr. if this bit is set and iot bit in lintcsr is set, linflex moves to idle state. if ltom bit in lintcsr is set, then ocf is cleare d by hardware in initialization mode. if ltom bit is cleared, then ocf maintains its status whatever the mode is. bef bit error flag this bit is set by hardware and indicates to the so ftware that linflex has detected a bit error. this error can occur during response field transmission (slave and master modes) or during header transmission (in master mode). this bit is cleared by software. cef checksum error flag this bit is set by hardware and indicates that the received checksum does not match the hardware calculated checksum. this bit is cleared by software. note: this bit is never set if ccd or cfd bit in lincr1 is set. sfef synch field error flag this bit is set by hardware and indicates that a sy nch field error occurred (inconsistent synch field). bdef break delimiter error flag this bit is set by hardware and indicates that the received break delimiter is too short (less than one bit time). idpef identifier parity error flag this bit is set by hardware and indicate s that a identifier parity error occurred. note: header interrupt is triggered when sfef or bdef or idpef bit is set and heie bit in linier is set.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 437 23.7.1.5 uart mode control register (uartcr) fef framing error flag this bit is set by hardware and indicates to the software that linflex has detected a framing error (invalid stop bit). this error can occur during reception of any data in the response field (master or slave mode) or during reception of synch field or identifier field in slave mode. bof buffer overrun flag this bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. if rblm in lincr1 is set then the new byte received is discarded. if rblm is reset then the new byte overwrites the buffer. it can be cleared by software. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. offset: 0x0010 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 tdfl 0 rdfl 00 00 rxen txen op pce wl uart w reset0000000000000000 figure 23-10. uart mode control register (uartcr) table 23-10. uartcr field descriptions field description tdfl transmitter data field length this field sets the number of bytes to be transm itted in uart mode. it can be programmed only when the uart bit is set. tdfl[0:1] = transmit buffer size ? 1. 00 transmit buffer size = 1. 01 transmit buffer size = 2. 10 transmit buffer size = 3. 11 transmit buffer size = 4. rdfl receiver data field length this field sets the number of bytes to be re ceived in uart mode. it can be programmed only when the uart bit is set. rdfl[0:1] = receive buffer size ? 1. 00 receive buffer size = 1. 01 receive buffer size = 2. 10 receive buffer size = 3. 11 receive buffer size = 4. table 23-9. linesr field descriptions (continued) field description
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 438 freescale semiconductor 23.7.1.6 uart mode status register (uartsr) rxen receiver enable 0 receiver disable. 1 receiver enable. this bit can be programmed only when the uart bit is set. txen transmitter enable 0 transmitter disable. 1 transmitter enable. this bit can be programmed only when the uart bit is set. note: transmission starts when this bit is set and when writing data0 in the bdrl register. op odd parity 0 sent parity is even. 1 sent parity is odd. this bit can be programmed in initialization mode only when the uart bit is set. pce parity control enable 0 parity transmit/check disable. 1 parity transmit/check enable. this bit can be programmed in initialization mode only when the uart bit is set. wl word length in uart mode 0 7-bit data + parity bit. 1 8-bit data (or 9-bit if pce is set). this bit can be programmed in initialization mode only when the uart bit is set. uart uart mode enable 0lin mode. 1uart mode. this bit can be programmed in initialization mode only. offset: 0x0014 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf pe3 pe2 pe1 pe0 rmb fef bof rps wuf 0 0drfdtfnf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 23-11. uart mode status register (uartsr) table 23-10. uartcr field descriptions (continued) field description
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 439 table 23-11. uartsr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. it is cleared by software. ocf ocf output compare flag 0 no output compare event occurred. 1 the content of the counter has matched the content of oc1[0:7] or oc2[0:7] in linocr. an interrupt is generated if the ocie bit in linier register is set. pe3 parity error flag rx3 this bit indicates if there is a parity error in the corresponding received byte (rx3). see section 23.8.1.1, buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. pe2 parity error flag rx2 this bit indicates if there is a parity error in the corresponding received byte (rx2). see section 23.8.1.1, buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. pe1 parity error flag rx1 this bit indicates if there is a parity error in the corresponding received byte (rx1). see section 23.8.1.1, buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. pe0 parity error flag rx0 this bit indicates if there is a parity error in the corresponding received byte (rx0). see section 23.8.1.1, buffer in uart mode. no interrupt is generated if this error occurs. 0 no parity error. 1 parity error. rmb release message buffer 0 buffer is free. 1 buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. fef framing error flag this bit is set by hardware and indicates to the software that linflex has detected a framing error (invalid stop bit). bof buffer overrun flag this bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. if rblm in lincr1 is set then the new byte receiv ed is discarded. if rblm is reset then the new byte overwrites buffer. it can be cleared by software. rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes. wuf wake-up flag this bit is set by hardware and indicates to t he software that linflex has detected a falling edge on the linrx pin in sleep mode. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt i generated if wuie bit in linier is set.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 440 freescale semiconductor 23.7.1.7 lin timeout control status register (lintcsr) drf data reception completed flag this bit is set by hardware and indicates the data reception is co mpleted, that is , the number of bytes programmed in rdfl[0:1] in uartcr have been received. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if drie bit in linier is set. note: in uart mode, this flag is set in case of framing error, parity error or overrun. dtf data transmission completed flag this bit is set by hardware and indicates the data transmission is completed, that is, the number of bytes programmed in tdfl[0:1] have been transmitted. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt is generated if dtie bit in linier is set. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. offset: 0x0018 access: user read/write 01234 5 6 7 89101112131415 r 0000 000 0 0000 0000 w reset000000 0 0 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0 lto m iot toce cnt w reset000000 0 0 00100000 figure 23-12. lin timeout control status register (lintcsr) table 23-12. lintcsr field descriptions field description ltom lin timeout mode 0 lin timeout mode (header, response and frame timeout detection). 1 output compare mode. this bit can be set/cleared in initialization mode only. iot idle on timeout 0 lin state machine not reset to idle on timeout event. 1 lin state machine reset to idle on timeout event. this bit can be set/cleared in initialization mode only. table 23-11. uartsr field descriptions (continued) field description
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 441 23.7.1.8 lin output compare register (linocr) toce timeout counter enable 0 timeout counter disable. ocf bit in linesr or uartsr is not set on an output compare event. 1 timeout counter enable. ocf bit is set if an output compare event occurs. toce bit is configurable by software in initialization mode. if lin state is not init and if timer is in lin timeout mode, then hardware takes control of toce bit. cnt counter value this field indicates the li n timeout counter value. offset: 0x001c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r oc2 1 oc1 1 w reset11111111 11111111 1 if lintcsr[ltom] = 0, this field is read-only. figure 23-13. lin output compare register (linocr) table 23-13. linocr field descriptions field description oc2 output compare 2 value these bits contain the value to be compared to the value of bits cnt[0:7] in lintcsr. oc1 output compare 1 value these bits contain the value to be compared to the value of bits cnt[0:7] in lintcsr. table 23-12. lintcsr field descriptions (continued) field description
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 442 freescale semiconductor 23.7.1.9 lin timeout cont rol register (lintocr) 23.7.1.10 lin fracti onal baud rate re gister (linfbrr) offset: 0x0020 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 rto 0 hto w reset0000111000101100 figure 23-14. lin timeout control register (lintocr) table 23-14. lintocr field descriptions field description rto response timeout value this field contains the response timeout duration (in bit time) for 1 byte. the reset value is 0xe = 14, corresponding to t response_maximum =1.4t response_nominal hto header timeout value this field contains the header timeout duration (in bit time). this value does not include the break and the break delimiter. the reset value is the 0x2c = 44, corresponding to t header_maximum. programming linsr[mme] = 1 changes the hto value to 0x1c = 28. this field can be written only in slave mode. offset: 0x0024 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 0000 div_f w reset0000000000000000 figure 23-15. lin fractional ba ud rate register (linfbrr)
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 443 23.7.1.11 lin integer baud rate register (linibrr) table 23-15. linfbrr field descriptions field description div_f fraction bits of lfdiv the 4 fraction bits define the value of th e fraction of the linflex divider (lfdiv). fraction (lfdiv) = decimal value of div_f / 16. this field can be written in initialization mode only. offset: 0x0028 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 div_m w reset0000000000000000 figure 23-16. lin integer ba ud rate register (linibrr) table 23-16. linibrr field descriptions field description div_m lfdiv mantissa this field defines the linflex divider (lfdiv) mantissa value (see table 23-17 ). this field can be written in initialization mode only. table 23-17. integer baud rate selection div_m[0:12] mantissa 0x0000 lin clock disabled 0x0001 1 ... ... 0x1ffe 8190 ox1fff 8191
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 444 freescale semiconductor 23.7.1.12 lin checksum fi eld register (lincfr) 23.7.1.13 lin control register 2 (lincr2) offset: 0x002c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 cf w reset0000000000000000 figure 23-17. lin checksum field register (lincfr) table 23-18. lincfr field descriptions field description cf checksum bits when lincr1[ccd] = 0, this field is read-only. when lincr1[ccd] = 1, this field is read/write. see table 23-4 . offset: 0x0030 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 iobe iope 0 0 0 0 0 0 0 0 0 0 0 0 0 w wurq ddrq dtrq abrq htrq reset0110000000000000 figure 23-18. lin control register 2 (lincr2) table 23-19. lincr2 field descriptions field description iobe idle on bit error 0 bit error does not reset lin state machine. 1 bit error reset lin state machine. this bit can be set/cleared in initialization mode only.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 445 23.7.1.14 buffer identifier register (bidr) iope idle on identifier parity error 0 identifier parity error does not reset lin state machine. 1 identifier parity error reset lin state machine. this bit can be set/cleared in initialization mode only. wurq wake-up generation request setting this bit generates a wake-up pulse. it is reset by hardware when the wake-up character has been transmitted. the character sent is copied from data0 in bdrl buffer. note that this bit cannot be set in sleep mode. software has to exit sleep mode before requesting a wake-up. bit error is not checked when transmitting the wake-up request. ddrq data discard request set by software to stop data reception if the fram e does not concern the node. this bit is reset by hardware once linflex has moved to idle state. in slave mode, this bit can be set only when hrf bit in linsr is set and identifier did not match any filter. dtrq data transmission request set by software in slave mode to request the transmi ssion of the lin data field stored in the buffer data register. this bit can be set only when hrf bit in linsr is set. cleared by hardware when the request has been completed or aborted or on an error condition. in master mode, this bit is set by hardware when bidr[dir] = 1 and header transmission is completed. abrq abort request set by software to abort the current transmission. cleared by hardware when the transmission has been aborted. linflex aborts the transmission at the end of the current bit. this bit can also abort a wake-up request. it can also be used in uart mode. htrq header transmission request set by software to request the transmission of the lin header. cleared by hardware when the request has been completed or aborted. this bit has no effect in uart mode. offset: 0x0034 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dfl dir ccs 00 id w reset0000000000000000 figure 23-19. buffer identifier register (bidr) table 23-19. lincr2 field descriptions (continued) field description
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 446 freescale semiconductor 23.7.1.15 buffer data register lsb (bdrl) table 23-20. bidr field descriptions field description dfl data field length this field defines the number of data by tes in the response part of the frame. dfl = number of data bytes ? 1. normally, lin uses only dfl[2:0] to manage fram es with a maximum of 8 bytes of data. identifier filters are compatible with df l[2:0] only. dfl[5:3] are prov ided to manage extended frames. dir direction this bit controls the direction of the data field. 0 linflex receives the data and copies them in the bdr registers. 1 linflex transmits the data from the bdr registers. ccs classic checksum this bit controls the type of checksum applied on the current message. 0 enhanced checksum covering identifier and da ta fields. this is compatible with lin specification 2.0 and higher. 1 classic checksum covering data fields only. th is is compatible with lin specification 1.3 and earlier. in lin slave mode (mme bit cleared in lincr1), this bit must be configured before the header reception. if the slave has to manage frames with 2 types of checksum, filters must be configured. id identifier identifier part of the identifier field without the identifier parity. offset: 0x0038 access: user read/write 0123456789101112131415 r data3 data2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data1 data0 w reset0000000000000000 figure 23-20. buffer data register lsb (bdrl) table 23-21. bdrl field descriptions field description data3 data byte 3 data byte 3 of the data field. data2 data byte 2 data byte 2 of the data field.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 447 23.7.1.16 buffer data register msb (bdrm) data1 data byte 1 data byte 1 of the data field. data0 data byte 0 data byte 0 of the data field. offset: 0x003c access: user read/write 0123456789101112131415 r data7 data6 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data5 data4 w reset0000000000000000 figure 23-21. buffer data register msb (bdrm) table 23-22. bdrm field descriptions field description data7 data byte 7 data byte 7 of the data field. data6 data byte 6 data byte 6 of the data field. data5 data byte 5 data byte 5 of the data field. data4 data byte 4 data byte 4 of the data field. table 23-21. bdrl field de scriptions (continued) field description
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 448 freescale semiconductor 23.7.1.17 identifier filter enable register (ifer) offset: 0x0040 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 fact w reset0000000000000000 figure 23-22. identifier filter enable register (ifer) table 23-23. ifer field descriptions field description fact filter activation (see table 23-24 ) 0 filters 2 n and 2 n + 1 are deactivated. 1 filters 2 n and 2 n + 1 are activated. this field can be set/cleared in initialization mode only. table 23-24. ifer[fact] configuration bit value result fact[0] 0 filters 0 and 1 are deactivated. 1 filters 0 and 1 are activated. fact[1] 0 filters 2 and 3 are deactivated. 1 filters 2 and 3 are activated. fact[2] 0 filters 4 and 5 are deactivated. 1 filters 4 and 5 are activated. fact[3] 0 filters 6 and 7 are deactivated. 1 filters 6 and 7 are activated. fact[4] 0 filters 8 and 9 are deactivated. 1 filters 8 and 9 are activated. fact[5] 0 filters 10 and 11 are deactivated. 1 filters 10 and 11 are activated. fact[6] 0 filters 12 and 13 are deactivated. 1 filters 12 and 13 are activated.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 449 23.7.1.18 identifier filter match index (ifmi) fact[7] 0 filters 14 and 15 are deactivated. 1 filters 14 and 15 are activated. address: base + 0x0044 access: user read-only 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0000 0000 ifmi[0:4] w reset0000000000000000 figure 23-23. identifier filter match index (ifmi) table 23-25. ifmi field descriptions field description 0:26 reserved ifmi[0:4] 27:31 filter match index this register contains the index corresponding to t he received identifier. it can be used to directly write or read the data in sram (see section 23.8.2.2, slave mode for more details). when no filter matches, if mi[0:4] = 0. when filter n is matching, ifmi[0:4] = n +1. table 23-24. ifer[fact] configuration (continued) bit value result
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 450 freescale semiconductor 23.7.1.19 identifier filter mode register (ifmr) offset: 0x0048 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 0 0000 0 ifm w reset0000000000000000 figure 23-24. identifier filter mode register (ifmr) table 23-26. ifmr field descriptions field description ifm filter mode (see table 23-27 ). 0 filters 2 n and 2 n + 1 are in identifier list mode. 1 filters 2 n and 2 n + 1 are in mask mode (filter 2 n + 1 is the mask for the filter 2 n ). table 23-27. ifmr[ifm] configuration bit value result ifm[0] 0 filters 0 and 1 are in identifier list mode. 1 filters 0 and 1 are in mask mode (filt er 1 is the mask for the filter 0). ifm[1] 0 filters 2 and 3 are in identifier list mode. 1 filters 2 and 3 are in mask mode (filt er 3 is the mask for the filter 2). ifm[2] 0 filters 4 and 5 are in identifier list mode. 1 filters 4 and 5 are in mask mode (filt er 5 is the mask for the filter 4). ifm[3] 0 filters 6 and 7 are in identifier list mode. 1 filters 6 and 7 are in mask mode (filt er 7 is the mask for the filter 6). ifm[4] 0 filters 8 and 9 are in identifier list mode. 1 filters 8 and 9 are in mask mode (filt er 9 is the mask for the filter 8). ifm[5] 0 filters 10 and 11 are in identifier list mode. 1 filters 10 and 11 are in mask mode (filter 11 is the mask for the filter 10). ifm[6] 0 filters 12 and 13 are in identifier list mode. 1 filters 12 and 13 are in mask mode (filter 13 is the mask for the filter 12).
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 451 23.7.1.20 identifier filter control register (ifcr2 n ) note this register can be writte n in initialization mode only. ifm[7] 0 filters 14 and 15 are in identifier list mode. 1 filters 14 and 15 are in mask mode (filter 15 is the mask for the filter 14). offsets: 0x004c?0x0084 (8 regist ers) access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 dfl dir ccs 00 id w w1c reset0000000000000000 figure 23-25. identifier filter control register (ifcr2 n ) table 23-28. ifcr2 n field descriptions field description dfl data field length this field defines the number of data by tes in the response part of the frame. dir direction this bit controls the direction of the data field. 0 linflex receives the data and copies them in the bdrl and bdrm registers. 1 linflex transmits the data from the bdrl and bdrm registers. ccs classic checksum this bit controls the type of checksum applied on the current message. 0 enhanced checksum covering identifier and data fiel ds. this is compatible with lin specification 2.0 and higher. 1 classic checksum covering data fields only. this is compatible with li n specification 1.3 and earlier. id identifier identifier part of the id entifier field without the identifier parity. table 23-27. ifmr[ifm] configuration (continued) bit value result
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 452 freescale semiconductor 23.7.1.21 identifier filter control register (ifcr2 n +1) note this register can be writte n in initialization mode only. offsets: 0x0050?0x0088 (8 regist ers) access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000 dfl dir ccs 00 id w w1c reset0000000000000000 figure 23-26. identifier filter control register (ifcr2 n +1) table 23-29. ifcr2 n + 1 field descriptions field description dfl data field length this field defines the number of data bytes in the response part of the frame. dfl = number of data bytes ? 1. dir direction this bit controls the direction of the data field. 0 linflex receives the data and copies them in the bdrl and bdrm registers. 1 linflex transmits the data from the bdrl and bdrm registers. ccs classic checksum this bit controls the type of ch ecksum applied on the current message. 0 enhanced checksum covering identifier and data fields. this is compatible with lin specification 2.0 and higher. 1 classic checksum covering data field only. this is compatible with lin specification 1.3 and earlier. id identifier identifier part of the identifier field without the identifier parity
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 453 23.8 functional description 23.8.1 uart mode the main features in the uart mode are ? full duplex communication ? 8- or 9-bit data with parity ? 4-byte buffer for reception, 4-byte buffer for transmission ? 8-bit counter for timeout management 8-bit data frames : the 8th bit can be a data or a parity bit. even/odd parity can be selected by the odd parity bit in the uartcr. an even pa rity is set if th e modulo-2 sum of the 7 data bits is 1. an odd parity is cleared in this case. figure 23-27. uart mode 8-bit data frame 9-bit frames : the 9th bit is a parity bit. even/odd parity can be selected by the odd parity bit in the uartcr. an even parity is set if th e modulo-2 sum of the 8 data bits is 1. an odd par ity is cleared in this case. figure 23-28. uart mode 9-bit data frame 23.8.1.1 buffer in uart mode the 8-byte buffer is divided into two parts: one fo r receiver and one for transmitter, as shown in table 23-30 . start bit d0 d7 stop bit byte field ? data bit ? parity bit d1 d2 d3 d4 d5 d6 start bit d0 d7 stop bit byte field ? parity bit d1 d2 d3 d4 d5 d6 d8
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 454 freescale semiconductor 23.8.1.2 uart transmitter in order to start transmission in uart mode, you mu st program the uart bit a nd the transmitter enable (txen) bit in the uartcr to 1. transmission starts when data0 (least significant data byte) is programmed. the number of bytes tran smitted is equal to the value c onfigured by uartcr[tdfl] (see table 23-10 ). the transmit buffer is 4 bytes, hence a 4-byte maximum transmission can be triggered. once the programmed number of bytes has b een transmitted, the uartsr[dtf] bit is set. if uartcr[txen] is reset during a transmission then the current transmission is completed and no further tran smission can be invoked. 23.8.1.3 uart receiver the uart receiver is active as soon as the user exits initialization mode and programs uartcr[rxen] = 1. there is a dedicated 4-byte data buffer for received data bytes. once the programmed number (rdfl bits) of bytes has been received, the uartsr[drf] bit is set. if the rxen bit is reset during a reception th en the current reception is completed and no further reception can be invoked until rxen is set. if a parity error occurs during recepti on of any byte, then the corresponding pe x bit in the uartsr is set. no interrupt is generated in this case. if a frami ng error occurs in any byte (uartsr[fe] = 1) then an interrupt is generated if th e linier[feie] bit is set. if the last received frame ha s not been read from the buffer (that is , rmb bit is not rese t by the user) then upon reception of the next byte an overrun error o ccurs (uartsr[bof] = 1) and one message will be lost. which message is lost depends on the configuration of lincr1[rblm]. ? if the buffer lock function is disabled (lincr1[ rblm] = 0), the last message stored in the buffer is overwritten by the new incoming message. in this case the latest message is always available to the application. ? if the buffer lock function is enabled (lincr1[rb lm] = 1), the most recent message is discarded and the previous message is available in the buffer. table 23-30. message buffer buffer data register lin mode uart mode bdrl[0:31] transmit/receive buffer data0[0:7] transmit buffer tx0 data1[0:7] tx1 data2[0:7] tx2 data3[0:7] tx3 bdrm[0:31] data4[0:7] receive buffer rx0 data5[0:7] rx1 data6[0:7] rx2 data7[0:7] rx3
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 455 an interrupt is generated if the linier[boie] bit is set. 23.8.1.4 clock gating the linflex clock can be gated from the mode en try module (mc_me). in uart mode, the linflex controller acknowledges a clock ga ting request once the data transm ission and data reception are completed, that is, once the transmit buffer is empty and the receive buffer is full. 23.8.2 lin mode lin mode comprises four submodes: ? master mode ? slave mode ? slave mode with identifier filtering ? slave mode with automatic resynchronization these submodes are described in the following pages. 23.8.2.1 master mode in master mode the application uses the message buffer to handle the lin me ssages. master mode is selected when the lincr1[mme] bit is set. 23.8.2.1.1 lin header transmission according to the lin protocol any communication on the lin bus is triggered by the master sending a header. the header is transmitted by the master task while the data is transmitted by the slave task of a node. to transmit a header with linflex, the application must set up the identi fier and the data field length, and configure the message (direction and checksum t ype) in the bidr before requesting the header transmission by set ting lincr2[htrq]. 23.8.2.1.2 data transmission (transceiver as publisher) when the master node is publisher of the data corresponding to the identif ier sent in the header, then the slave task of the master has to send the data in the response part of the lin frame. therefore, the application must provide the data to linflex before requesting the header transmission. the application stores the data in the message buffer bdr. according to the data field length, li nflex transmits the data and the checksum. the application uses the bdr[ccs] bit to configure the ch ecksum type (classic or enhanced) for each message. if the response has been sent successfu lly, the linsr[dtf] bit is set. in ca se of error, the dtf flag is not set and the corresponding error flag is set in the linesr (see section 23.8.2.1.6, error handling ). it is possible to handle frames with a response size larg er than 8 bytes of data (extended frames). if the data field length in the bidr is c onfigured with a value higher than 8 data bytes, the linsr[dbef] bit is
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 456 freescale semiconductor set after the first 8 bytes have be en transmitted. the application ha s to update the buffer bdr before resetting the dbef bit. the transmission of the next bytes starts when the dbef bit is reset. after the last data byte (or the checksum byte) has been sent, the dtf flag is set. the direction of the message buffer is controlled by the bidr[dir] bit. wh en the application sets this bit the response is sent by linflex (publis her). resetting this b it configures the messag e buffer as subscriber. 23.8.2.1.3 data reception (transceiver as subscriber) to receive data from a slave node, the master sends a header with the corresponding identifier. linflex stores the data received from the slave in the message buffer and stores the message status in the linsr. if the response has been received successfully, the linsr[dr f] is set. in case of error, the drf flag is not set and the corresponding error flag is set in the linesr (see section 23.8.2.1.6, error handling ). it is possible to handle frames with a response size larg er than 8 bytes of data (extended frames). if the data field length in the bidr is c onfigured with a value higher than 8 data bytes, the linsr[dbff] bit is set once the first 8 bytes ha ve been received. the appl ication has to read the buf fer bdr before resetting the dbff bit. once the last data byte (or the checks um byte) has been received, the drf flag is set. 23.8.2.1.4 data discard to discard data from a slave, the bidr[dir] bit mu st be reset and the lincr2[ddrq] bit must be set before starting the header transmission. 23.8.2.1.5 error detection linflex is able to detect and ha ndle lin communication errors. a code stored in the li n error status register (linesr) signals the errors to the software. in master mode, the follow ing errors are detected: ? bit error: during transm ission, the value read back from the bus differs from the transmitted value. ? framing error: a dominant state has been sampled on the stop bit of the currently received character (synch field, identi fier field or data field). ? checksum error: the computed chec ksum does not match the received one. ? response and frame timeout: see section 23.8.3, 8-bit timeout counter , for more details. 23.8.2.1.6 error handling in case of bit error detection duri ng transmission, linflex stops the tr ansmission of the frame after the corrupted bit. linflex returns to idle state a nd an interrupt is generated if linier[beie] = 1. during reception, a framing error leads linflex to discard the current frame. linflex returns immediately to idle state. an interr upt is generated if linier[feie] = 1. during reception, a checksum error leads linflex to dis card the received frame. li nflex returns to idle state. an interrupt is generated if linier[ceie] = 1.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 457 23.8.2.1.7 overrun after the message buffer is full, th e next valid message reception causes an overrun and a message is lost. the linflexd controller sets linsr[bof] to si gnal the overrun condition. which message is lost depends on the configuration of the rx message buffer: ? if the buffer lock function is di sabled (lincr1[rblm] cleared), th e last message stored in the buffer is overwritten by the new incoming message. in this case, the latest message is always available to the software. ? if the buffer lock function is enabled (lincr1[rblm] set), the most recent message is discarded and the previous message is available in the buffer. 23.8.2.2 slave mode in slave mode the application uses the message buffer to handle the lin messages. slave mode is selected when lincr1[mme] = 0. 23.8.2.2.1 data transmission (transceiver as publisher) when linflex receives the identifier, the linsr[hrf] is set and, if linier[h rie] = 1, an rx interrupt is generated. the software must read the received iden tifier in the bidr, fill the bdr registers, specify the data field length using the bidr[dfl], an d trigger the data transmission by setting the lincr2[dtrq] bit. one or several identifier filters can be c onfigured for transmi ssion by setting the ifcr x [dir] bit and activated by setting one or several bits in the ifer. when at least one identifier filter is configured in transmission and activated, and if the received identifier matches the filter, a specific tx interrupt (instead of an rx interrupt) is generated. typically, the application has to c opy the data from sram lo cations to the bdar. to copy the data to the right location, the application has to identify the data by means of the id entifier. to avoid this and to ease the access to the sram locations, the linflex controll er provides a filter matc h index. this index value is the number of the filter that matched the received identifier. the software can use the index in the ifmi register to directly access the pointer that points to the right data array in the sram area and copy this data to the bdar (see figure 23-30 ). using a filter avoids the software having to configure the direction, the data field length and the checksum type in the bidr. the software fills the bdar and triggers the data transmission by programming lincr2[dtrq] = 1. if linflex cannot provide enough tx id entifier filters to handle all identi fiers the software has to transmit data for, then a filter can be configured in mask mode (see section 23.8.2.3, slave mode with identifier filtering ) in order to manage several id entifiers with one filter only.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 458 freescale semiconductor 23.8.2.2.2 data reception (transceiver as subscriber) when linflex receives the identifier, the linsr[ hrf] bit is set and, if linier[hrie] = 1, an rx interrupt is generated. the software mu st read the received identifier in the bidr and specify the data field length using the bidr[dfl] field before receiving the stop bit of the first byte of data field. when the checksum reception is comp leted, an rx interrupt is generated to allow the software to read the received data in the bdr registers. one or several identifier filters can be configured for recep tion by programming ifcr x [dir] = 0 and activated by setting one or several bits in the ifer. when at least one identifier filter is configured in reception and activat ed, and if the received identifier matches the filter, an rx interrupt is ge nerated after the chec ksum reception only. typically, the application has to c opy the data from the bdar to sram locations. to copy the data to the right location, the application has to identify the data by means of the id entifier. to avoid this and to ease the access to the sram locations, the linflex controll er provides a filter matc h index. this index value is the number of the filter that matched the received identifier. the software can use the index in the ifmi register to directly access the pointer that points to the right data array in the sram area and copy this data from the bdar to the sram (see figure 23-30 ). using a filter avoids the so ftware reading the id valu e in the bidr and configur ing the direction, the data field length, and the checksum type in the bidr. if linflex cannot provide e nough rx identifier filters to handle all identifiers th e software has to receive the data for, then a filter can be configured in mask mode (see section 23.8.2.3, slave mode with identifier filtering ) in order to manage several id entifiers with one filter only. 23.8.2.2.3 data discard when linflex receives the identifier, the linsr[ hrf] bit is set and, if linier[hrie] = 1, an rx interrupt is generated. if the received identi fier does not concern the node, you must program lincr2[ddrq] = 1. linflex returns to idle state after bit ddrq is set. 23.8.2.2.4 error detection in slave mode, the following errors are detected: ? header error : an error occurred during header recepti on (break delimiter error, inconsistent synch field, header timeout). ? bit error : during transmission, the value r ead back from the bus differs from the transmitted value. ? framing error : a dominant state has been sampled on th e stop bit of the currently received character (synch field, identi fier field or data field). ? checksum error : the computed checksum does not match the received one. 23.8.2.2.5 error handling in case of bit error detection duri ng transmission, linflex stops the tr ansmission of the frame after the corrupted bit. linflex returns to idle state and an interrupt is generated if the beie bi t in the linier is set.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 459 during reception, a framing error leads linflex to discard the current frame. linflex returns immediately to idle state. an interr upt is generated if linier[feie] = 1. during reception, a checksum error leads linflex to dis card the received frame. li nflex returns to idle state. an interrupt is generated if linier[ceie] = 1. during header reception, a break delimiter error, an inconsistent synch field or a timeout error leads linflex to discard the header. an interrupt is gene rated if linier[heie] = 1. linflex returns to idle state. 23.8.2.2.6 valid header a received header is considered as valid when it has been received corr ectly according to the lin protocol. if a valid break field and br eak delimiter come before th e end of the current header or at any time during a data field, the current header or data is discarded and the state m achine synchronizes on this new break. 23.8.2.2.7 valid message a received or transmitted message is considered as valid when the data has been received or transmitted without error according to the lin protocol. 23.8.2.2.8 overrun once the message buffer is full, the next valid message reception leads to an overr un and a message is lost. the hardware sets the bof bit in the linsr to signal the overrun condition. which message is lost depends on the configuration of the rx message buffer: ? if the buffer lock function is disabled (lincr1[ rblm] = 0), the last message stored in the buffer is overwritten by the new incoming message. in this case the latest message is always available to the application. ? if the buffer lock function is enabled (lincr1[rb lm] = 0), the most recent message is discarded and the previous message is available in the buffer. 23.8.2.3 slave mode with identifier filtering in the lin protocol the identifier of a message is not associated with the address of a node but related to the content of the message. consequent ly a transmitter broadcasts its mess age to all receivers. on header reception a slave node decides ? depending on the identifier value ? whether the software needs to receive or send a response. if the message does not target the node, it must be discarded without software intervention. to fulfill this requirement, the linflex controller provides configurable filters in order to request software intervention only if needed. this ha rdware filtering saves cpu resources that would otherwise be needed by software for filtering.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 460 freescale semiconductor 23.8.2.3.1 filter mode usually each of the eight ifcr regi sters filters one dedicated identifi er, but this limits the number of identifiers linflex can handle to th e number of ifcr register s implemented in the device. therefore, in order to be able to handle more identifiers, the filters can be configured in mask mode. in identifier list mode (the default mode), both filter regi sters are used as identifier registers. all bits of the incoming identifier must match the bits specified in the filter register. in mask mode, the identifier registers are associated with mask registers specifying which bits of the identifier are handled as ?must ma tch? or as ?don?t care?. for the bit mapping and registers organization, please see figure 23-29 . figure 23-29. filter configur ation?register organization 23.8.2.3.2 identifier fi lter mode configuration the identifier filters ar e configured in the ifcr x registers. to configure an id entifier filter the filter must first be deactivated by programming ifer[fact] = 0. the id entifier list or identifier mask mode for the corresponding ifcr x registers is configured by the ifmr [ifm] bit. for each filter, the ifcr x register configures the id (or the mask), the direction (tx or rx), the data field lengt h, and the checksum type. if no filter is active, an rx interrupt is generated on any received identifier event. if at least one active filter is conf igured as tx, all received identifiers matching this filter generate a tx interrupt. if at least one active filter is conf igured as rx, all received identifiers matching this filter generate an rx interrupt. ifcr n identifier id bit mapping identifier filter register organization 15 0 dfl ccs dir identifier filter configuration ifcr2 n identifier identifier ifcr2 n +1 ifm = 0 identifier filter mode ifcr2 n identifier mask ifcr2 n +1 ifm = 1 identifier list mode mask mode
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 461 if no active filter is configured as rx, all received identi fiers not matching tx filter(s) generate an rx interrupt. figure 23-30. identifier match index 23.8.2.4 slave mode with au tomatic resynchronization automatic resynchronization must be enabled in slave mode if f periph_set_1_clk tolerance is greater than 1.5%. this feature compensates a f periph_set_1_clk deviation up to 14%, as specified in lin standard. this mode is similar to sl ave mode as described in section 23.8.2.2, slave mode , with the addition of automatic resynchroniza tion enabled by the lase bit. in this mode linflex adjusts the fractional baud rate generator after each synch field reception. table 23-31. filter to interrupt vector correlation number of active filters number of active filters configured as tx number of active filters configured as rx interrupt vector 0 0 0 rx interrupt on all identifiers a (a > 0) a 0 ? tx interrupt on identifiers matching the filters, ? rx interrupt on all other identifiers if bf bit is set, no rx interrupt if bf bit is reset n (n = a + b) a (a > 0) b (b > 0) ? tx interrupt on identifiers matching the tx filters, ? rx interrupt on identifiers matching the rx filters, ? all other identifiers discarded (no interrupt) b (b > 0) 0 b ? rx interrupt on identifiers matching the filters, ? tx interrupt on all other identifiers if bf bit is set, no tx interrupt if bf bit is reset ifmi message0 message1 message2 data pointers table sram @ +
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 462 freescale semiconductor 23.8.2.4.1 automatic resynchronization method when automatic resynchronization is enabled, after each lin break, the time durat ion between five falling edges on rdi is sampled on f periph_set_1_clk and the result of this measuremen t is stored in an internal 19-bit register called sm (not user accessible) (see figure 23-31 ). then the lfdiv value (and its associated registers linibrr and linf brr) is automatically updated at the end of the fifth fa lling edge. during lin synch field measurement, the li nflex state machine is stopped and no data is transferred to the data register. figure 23-31. lin synch field measurement lfdiv is an unsigned fixed point number. the mantis sa is coded on 12 bits in the linibrr and the fraction is coded on 4 bits in the linfbrr. if lase bit = 1 then lfdiv is automatically updated at the end of each lin synch field. three internal registers (not user -accessible) manage the auto-update of the linflex divider (lfdiv): ? lfdiv_nom (nominal value written by soft ware at linibrr a nd linfbrr addresses) ? lfdiv_meas (results of the field synch measurement) ? lfdiv (used to genera te the local baud rate) on transition to idle, break or break delimiter state due to any error or on rece ption of a complete frame, hardware reloads lfdiv with lfdiv_nom. 23.8.2.4.2 deviation erro r on the synch field the deviation error is checke d by comparing the current baud rate (relative to the slave oscillator) with the received lin synch field (relative to the master os cillator). two checks ar e performed in parallel. the first check is based on a measurement between the fi rst falling edge and the last falling edge of the synch field: ? if d1 > 14.84%, lhe is set. ? if d1 < 14.06%, lhe is not set. ? if 14.06% < d1 < 14.84%, lhe can be either set or rese t depending on the de phasing between the signal on linflex_rx pin the f periph_set_1_clk clock. the second check is based on a meas urement of time between each fa lling edge of the synch field: lin break break bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin synch field measurement = 8.t br =sm.t periph_set_1_clk lfdiv(n) lfdiv(n+1) lfdiv = t br / (16.t periph_set_1_clk ) = rounding (sm / 128) t periph_set_1_clk = clock period t br = baud rate period t br t br = 16.lfdiv.t periph_set_1_clk sm = synch measurement register (19 bits) delim.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 463 ? if d2 > 18.75%, lhe is set. ? if d2 < 15.62%, lhe is not set. ? if 15.62% < d2 < 18.75%, lhe can be either set or rese t depending on the de phasing between the signal on linflex_rx pin the f periph_set_1_clk clock. note that the linflex does not need to check if the next edge occurs slow er than expected. this is covered by the check for deviation er ror on the full synch byte. 23.8.2.5 clock gating the linflex clock can be gated from the mode entry module (mc_me). in lin mode, the linflex controller acknowledges a clock gati ng request once the frame transmis sion or reception is completed. 23.8.3 8-bit timeout counter 23.8.3.1 lin timeout mode clearing the ltom bit (setting its value to 0) in the lintcsr enables the lin timeout mode. the linocr becomes read-only, and oc 1 and oc2 output compare values in the linocr are automatically updated by hardware. this configuration detects header time out, response timeout, and frame timeout. depending on the lin mode (selected by the lincr1[m me] bit), the 8-bit timeout counter will behave differently. lin timeout mode must not be enab led during lin extended fr ames transmission or reception (that is, if the data field length in the bidr is configur ed with a value higher than 8 data bytes). 23.8.3.1.1 lin master mode the lintocr[rto] field can be used to tune response timeout and fram e timeout values. header timeout value is fixed to hto = 28-bit time. field oc1 checks t header and t response and field oc2 checks t frame (see figure 23-32 ). when linflex moves from break delimi ter state to synch field state (see section 23.7.1.3, lin status register (linsr) ): ? oc1 is updated with the value of oc header (oc header = cnt + 28), ? oc2 is updated with the value of oc frame (oc frame = cnt + 28 + rto 9 (frame timeout value for an 8-byte frame), ? the toce bit is set. on the start bit of the fi rst response data byte (and if no error occurred during th e header reception), oc1 is updated with the value of oc response (oc response = cnt + rto 9 (response timeout value for an 8-byte frame)). on the first response byte is received, oc1 and oc2 are automatically updated to check t response and t frame according to rto (tolerance) and dfl.
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 464 freescale semiconductor on the checksum reception or in case of error in the header or response, the toce bit is reset. if there is no response, frame timeout value does not take into account the dfl value, and an 8-byte response (dfl = 7) is always assumed. 23.8.3.1.2 lin slave mode the lintocr[rto] field can be used to tune response timeout and fram e timeout values. header timeout value is fixed to hto. oc1 checks t header and t response and oc2 checks t frame (see figure 23-32 ). when linflex moves from break stat e to break delimiter state (see section 23.7.1.3, lin status register (linsr) ): ? oc1 is updated with the value of oc header (oc header =cnt+hto), ? oc2 is updated with the value of oc frame (oc frame =cnt+hto +rto9 (frame timeout value for an 8-byte frame)), ? the toce bit is set. on the start bit of the fi rst response data byte (and if no error occurred during th e header reception), oc1 is updated with the value of oc response (oc response = cnt + rto 9 (response timeout value for an 8-byte frame)). once the first response byte is received, oc1 a nd oc2 are automatically updated to check t response and t frame according to rto (tolerance) and dfl. on the checksum reception or in case of error in the header or data field, the toce bit is reset. figure 23-32. header and response timeout 23.8.3.2 output compare mode setting lintcsr[ltom] = 1 enables the output compar e mode. this mode allows the user to fully customize the use of the counter. oc1 and oc2 output compare values can be updated in the lintocr by software. oc frame oc header oc response header response break frame oc1 oc2 response space
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 465 23.8.4 interrupts table 23-32. linflex interrupt control interrupt event event flag bit enable control bit interrupt vector header received interrupt hrf hrie rxi 1 1 in slave mode, if at least one filter is configured as tx and enabled, header received interrupt vector is rxi or txi depending on the value of identifier received. data transmitted interrupt dtf dtie txi data received interrupt drf drie rxi data buffer empty interrupt dbef dbeie txi data buffer full interrupt dbff dbfie rxi wake-up interrupt wupf wupie rxi lin state interrupt 2 2 for debug and validation purposes lsf lsie rxi buffer overrun interrupt bof boie err framing error interrupt fef feie err header error interrupt hef heie err checksum error interrupt cef ceie err bit error interrupt bef beie err output compare interrupt ocf ocie err stuck at zero interrupt szf szie err
chapter 23 lin controller (linflex) MPC5606BK microcontroller reference manual, rev. 2 466 freescale semiconductor this page is intent ionally left blank.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 467 chapter 24 lin controller (linflexd) 24.1 introduction the linflexd (local interconnect network flexible with dma support) controller inte rfaces the lin network and supports the lin prot ocol versions 1.3, 2.0, 2.1 and j2602 in both master and slave modes. linflexd includes a lin mode that provides additional features (compa red to standard uart) to ease lin implementation, improve system robustness, minimize cpu load, and allow slave node resynchronization. figure 24-1 shows the linflexd block diagram. figure 24-1. linflexd block diagram 24.2 main features the linflexd controller can operate in several modes, each of which has a distinct set of features. these distinct features are descri bed in the following sections. in addition, the linflexd c ontroller has several featur es common to all modes: ? fractional baud rate generator lin protocol handler register model / application interface buffer interface lin status baud rate filter config. message slave lin control config control status message handler master message handler id filters (1) 1 filter activation optional
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 468 freescale semiconductor ? three operating modes for power savi ng and configuration registers lock ? initialization ?normal ?sleep ? two test modes ? loop back ?self test ? maskable interrupts 24.2.1 lin mode features ? supports lin protocol versions 1.3, 2.0, 2.1, and j2602 ? master mode with aut onomous message handling ? classic and enhanced checksum calculation and check ? single 8-byte buffer for transmission/reception ? extended frame mode for in -application programming purposes ? wake-up event on dominant bit detection ? true lin field state machine ? advanced lin error detection ? header, response, and frame timeout ? slave mode ? autonomous header handling ? autonomous transmit/receive data handling ? lin automatic resynchronization, allo wing operation with as clock source ? identifier filters for autonomous message handling in slave mode 24.2.2 uart mode features ? full-duplex communication ? selectable frame size: ? 8-bit frame ? 9-bit frame ? 16-bit frame ? 17-bit frame ? selectable parity: ? even ?odd ?0 ?1
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 469 ? 4-byte buffer for reception, 4-byte buffer for transmission ? 12-bit counter for timeout management 24.3 the lin protocol the lin (local interconnect networ k) is a serial communication prot ocol. the topology of a lin network is shown in figure 24-2 . a lin network consists of: ? one master ? several slave ? the lin bus a master node contains the master ta sk as well as a slave task, all ot her nodes contain a slave task only. the master node decides when and which frame shal l be transferred on the bus. the slave task provides the data to be transported by the frame. figure 24-2. lin network topology 24.3.1 dominant and recessive logic levels the lin bus defines two logic levels , dominant and recessive, as follows: ? dominant: logical low level (0) ? recessive: logical high level (1) 24.3.2 lin frames a frame consists of a header provided by the master task and a response provided by the slave task, as shown in figure 24-3 . lin master node lin slave node 1 lin slave node n lin lin lin rx tx lin transceiver linflexd controller mcu lin bus application
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 470 freescale semiconductor figure 24-3. lin frame structure 24.3.3 lin header the header consists of: ? a break field (described in section 24.3.3.1, break field ) ? a sync (described in section 24.3.3.2, sync ) ? an identifier (described in section 24.3.4.2, identifier ) the slave task associated with th e identifier provides the response. 24.3.3.1 break field the break field, shown in figure 24-4 , is used to signal the beginning of a new frame. it is always generated by the master and consists of: ? at least 13 dominant bits including the start bit ? at least one recessive bit that functions as break delimiter figure 24-4. break field 24.3.3.2 sync the sync pattern is a byte consisting of altern ating dominant and recessi ve bits as shown in figure 24-5 . it forms a data value of 0x55. header response header response master task slave task 1 slave task 2 frame slot frame header response space response start bit break delimiter
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 471 figure 24-5. sync pattern 24.3.4 response the response consists of: ? a data field (described in section 24.3.4.1, data field ) ? a checksum (described in section 24.3.4.3, checksum ) the slave task interested in the data associated with the identifier re ceives the response and verifies the checksum. 24.3.4.1 data field the structure of the data field tran smitted on the lin bus is shown in figure 24-6 . the lsb of the data is sent first and the msb last. the star t bit is encoded as a dominant bit and the stop bit is encoded as a recessive bit. figure 24-6. structure of the data field 24.3.4.2 identifier the identifier, shown in figure 24-7 , consists of two subfields: ? the identifier value (in bits 0?5) ? the identifier parity (in bits 6?7) the parity bits p0 and p1 are defined as follows: ? p0 = id0 xor id1 xor id2 xor id4 ? p1 = not(id1 xor id3 xor id4 xor id5) figure 24-7. identifier 24.3.4.3 checksum the checksum contains the inve rted 8-bit sum (with carry) ove r one of two possible groups: start bit stop bit start bit lsb msb stop bit byte field start bit id0 p1 stop bit id1 id2 id3 id4 id5 p0
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 472 freescale semiconductor ? the classic checksum sums all data bytes, and is used for communication with lin 1.3 slaves. ? the enhanced checksum sums all data bytes and th e identifier, and is used for communication with lin 2.0 (or later) slaves. 24.4 linflexd and software intervention the increasing number of communicat ion peripherals embedde d on microcontrollers (for example, can, lin, spi) requires more and more cpu resources for the communicat ion management. even a 32-bit microcontroller is overloade d if its peripherals do no t provide high level featur es to autonomously handle the communication. even though the lin prot ocol with a maximum baud rate of 20 kbit/s is relatively slow, it still generates a non-negligible load on the cpu if the lin is impl emented on a standard uart, as is usually the case. to minimize the cpu load in master mode, li nflexd handles the lin messages autonomously. in master mode, once the so ftware has triggered the header transm ission, linflexd doe s not request any software (that is, applicat ion) intervention until the next header transmission request in transmission mode or until the checksum r eception in reception mode. to minimize the cpu load in slave mode, linf lexd requires software intervention only to: ? trigger transmission or reception or data discard depending on the identifier ? write data into the buffer (tra nsmission mode) or read data fr om the buffer (reception mode) after checksum reception if filter mode is activated for sl ave mode, linflexd require s software intervention only to write data into the buffer (transmission mode) or read data from the buffer (reception mode) the software uses the control, stat us, and configuration registers to: ? configure lin parameters (for example, baud rate or mode) ? request transmissions ? handle receptions ? manage interrupts ? configure lin error and timeout detection ? process diagnostic information the message buffer stores transm itted or received lin frames. 24.5 summary of operating modes the linflexd controller has three operating modes: ? normal ? initialization ?sleep after a hardware reset, the linf lexd controller is in sleep m ode to reduce power consumption.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 473 the transitions between th ese modes are shown in figure 24-8 . the software instructs linflexd to enter initialization mode or sleep mode by setting lincr1[init] or lincr1 [sleep], respectively. figure 24-8. linflexd controller operating modes in addition to these controller-level operating mode s, the linflexd controller also supports several protocol-level modes: ? lin mode: ? master mode ? slave mode ? slave mode with identifier filtering ? slave mode with automatic resynchronization ? uart mode ? test modes: ? loop back mode ?self test mode these modes are discussed in de tail in subsequent sections. 24.6 controller-level operating modes 24.6.1 initialization mode the software initialization can be done while the hardware is in initiali zation mode. to enter or exit this mode, the software sets or cl ears lincr1[init], respectively. in initialization mode, all message transfers to and from the lin bus are stopped and the lin bus output (lintx) is recessive. entering initialization mode does not cha nge any of the configuration registers. to initialize the linflexd controller, the software must: sleep initialization normal s l e e p s l e e p * i n i t reset s l e e p l i n r x d o m i n a n t s l e e p * i n i t sl eep * i n i t
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 474 freescale semiconductor ? select the desired mode (master, slave or uart) ? set up the baud rate register ? if lin slave mode with filter activation is selected, initialize the identifier list 24.6.2 normal mode after initialization is complete, the software must clear lincr1[init] to put the linflexd controller into normal mode. 24.6.3 sleep (low-power) mode to reduce power consumption, linfle xd has a low-power mode called sleep mode. in this mode, the linflexd clock is st opped. consequently, the linfle xd will not update the stat us bits, but software can still access the li nflexd registers. to enter this mode, the software must set lincr1[sleep]. linflexd can be awakened (exit sleep mode) in one of two ways: ? the software clears lincr1[sleep] ? automatic wake-up is enabled (lincr1[awum] is set) and linflexd de tects lin bus activity (that is, if a wakeup pulse of 150 ? s is detected on the lin bus) on lin bus activity detection, hardware automati cally performs the wake-up sequence by clearing lincr1[sleep] if lincr1[a wum] is set. to exit from sleep m ode if lincr1[awum] is cleared, the software must clear lincr1[sleep ] when a wake-up event occurs. 24.7 lin modes 24.7.1 master mode in master mode, the software uses the me ssage buffer to handle the lin messages. master mode is selected when lincr1[mme] is set. 24.7.1.1 lin header transmission according to the lin protocol, a ny communication on the lin bus is triggered by the master sending a header. the header is transmitted by the master task while the data is transmitted by the slave task of a node. to transmit a header with linflexd the application must set up the identi fier and the data field length, and configure the message (direction and checksum type) in the bidr regist er before requesting the header transmission by set ting lincr2[htrq].
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 475 24.7.1.2 data transmission (tr ansceiver as publisher) when the master node is publisher of the data corresponding to the identif ier sent in the header, then the slave task of the master ha s to send the data in the re sponse part of the lin frame . therefore, the software must provide the data to linflexd before requesting the header transmi ssion. the software stores the data in the message buffer bdr. according to the data field length linflexd tran smits the data and the checksum. the software uses the bi dr[ccs] bit to configure the checksu m type (classic or enhanced) for each message. the direction of the message buffer is controlled by th e bidr[dir] bit. when the software sets this bit the response is sent by linflexd (publ isher). clearing this bit configures the message buffer as subscriber. 24.7.1.3 data reception (transceiver as subscriber) to receive data from a slave node, the master sends a header with the corres ponding identifier. linflexd stores the data received from the slave in the messag e buffer and stores the message status in the linsr. 24.7.1.4 error dete ction and handling linflexd is able to detect and handle lin communicat ion errors. a code stored in the lin error status register (linesr) signals the errors to the software. table 24-1 lists the errors detected in ma ster mode and the linflexd contro ller?s response to these errors. 24.7.1.5 overrun after the message buffer is full, th e next valid message reception causes an overrun and a message is lost. the linflexd controller sets linsr[bof] to si gnal the overrun condition. which message is lost depends on the configuration of the rx message buffer: table 24-1. errors in master mode error description linflexd response to error bit error during transmission, the value read back from the bus differs from the transmitted value ? stops the transmission of the frame after the corrupted bit ? generates an interrupt if linier[beie] is set ? returns to idle state framing error a dominant state has been sampled on the stop bit of the currently received character (sync field, identifier, or data field) if encountered during reception: ? discards the current frame ? generates an interrupt if linier[feie] is set ? returns immediately to idle state checksum error the computed checksum does not match the received checksum if encountered during reception: ? discards the current frame ? generates an interrupt if linier[ceie] is set ? returns to idle state response and frame timeout refer to section 24.12.1, 8-bit timeout counter, for more details
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 476 freescale semiconductor ? if the buffer lock function is di sabled (lincr1[rblm] cleared), th e last message stored in the buffer is overwritten by the new incoming message. in this case, the latest message is always available to the software. ? if the buffer lock function is enabled (lincr1[rblm] set), the most recent message is discarded and the previous message is available in the buffer. 24.7.2 slave mode in slave mode the software uses the me ssage buffer to handle the lin messages. slave mode is selected when the lincr1[mme] is cleared. 24.7.2.1 data transmission (tr ansceiver as publisher) when linflexd receives the identifier, an rx interrupt is generated. the software must: ? read the received id in the bidr register ? fill the bdr registers ? specify the data field lengt h using the bidr[dfl] field ? trigger the data transmi ssion by setting lincr2[dtrq] one or several identifier filters can be configur ed for transmission by sett ing the dir bits in the corresponding ifcr registers and ac tivated by setting one or severa l bits in the ifer register. when at least one identifier filter is configured in transmission and ac tivated. if the received id matches the filter, a specific tx interrupt is generated. typically, the software has to copy the data from ram locations to th e bdrl and bdrm registers. to copy the data to the right location, the software has to identify the data by means of the identifier. to avoid this and to ease the access to the ram locations, the linflexd controller provide s a filter match index. this index value is the number of the fi lter that matched the received identifier. the software can use the index in the ifmi register to directly access the pointer that points to the right data array in the ram area and copy this data to the bdrl and bdrm registers (see figure 24-10 ). using a filter avoids the software having to configure the direction, the data field length and the checksum type in the bdir register. the so ftware fills the bdrl and bdrm registers and triggers the data transmission by set ting lincr2[dtrq]. if linflexd cannot provide enough tx identifier filters to handle all identifiers the software has to transmit data for, then a filter can be configured in mask mode (refer to section 24.7.3, slave mode with identifier filtering ) in order to manage several identifiers with one filter only. 24.7.2.2 data reception (transceiver as subscriber) when linflexd receives the identifier, an rx interrupt is generated. the software must: ? read the received id in the bidr register ? specify the data field length using the bidr[dfl] field before the reception of the stop bit of the first byte of data field
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 477 when the checksum reception is comp leted, an rx interrupt is generated to allow the software to read the received data in the bdr registers. one or several identifier filters can be configured for reception by cl earing the dir bit in the corresponding ifcr registers and activated by clearing one or several b its in the ifer register. when at least one identifier filter is configured in reception and activat ed. if the received id matches the filter, an rx interrupt is genera ted after the checksum reception only. typically, the software has to copy the data from the bdrl and bdrm registers to ram locations. to copy the data to the right location, the software has to identify the data by means of the identifier. to avoid this and to ease the access to the ram locations, the linflexd controller provide s a filter match index. this index value is the number of the fi lter that matched the received identifier. the software can use the index in the ifmi register to directly access the pointer that points to the right data array in the ram area and c opy this data from the bdrl and bdrm registers to the ram (see figure 24-10 ). using a filter avoids the software reading the id value in the bidr re gister and configuring the direction, the data field length, and the checks um type in the bidr register. if linflexd cannot provide enough rx identifier filters to handle all identifiers the software has to receive the data for, then a filter can be configured in mask mode (refer to section 24.7.3, slav e mode with identifier filtering ) in order to manage several identifiers with one filter only. 24.7.2.3 data discard when linflexd receives the identifier, an rx interr upt is generated. if the re ceived identifier does not concern the node, the software must set lincr2[ddrq]. linfle xd returns to idle state. 24.7.2.4 error dete ction and handling table 24-2 lists the errors detected in sl ave mode and the linflexd contro ller?s response to these errors. table 24-2. errors in slave mode error description linflexd response to error bit error during transmission, the value read back from the bus differs from the transmitted value ? stops the transmission of the frame after the corrupted bit ? generates an interrupt if linier[beie] is set ? returns to idle state framing error a dominant state has been sampled on the stop bit of the currently received character (sync field, identifier, or data field) if encountered during reception: ? discards the current frame ? generates an interrupt if linier[feie] is set ? returns immediately to idle state
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 478 freescale semiconductor 24.7.2.5 valid header a received header is considered as valid when it has been received corr ectly according to the lin protocol. if a valid break field and break delim iter come before the end of the cu rrent header, or at any time during a data field, the current header or data is discarded and the state m achine synchronizes on this new break. 24.7.2.6 valid message a received or transmitted message is considered as valid when the data has been received or transmitted without error according to the lin protocol. 24.7.2.7 overrun after the message buffer is full, th e next valid message reception causes an overrun and a message is lost. the linflexd controller sets linsr[bof] to si gnal the overrun condition. which message is lost depends on the configuration of the rx message buffer: ? if the buffer lock function is di sabled (lincr1[rblm] cleared), th e last message stored in the buffer is overwritten by the new incoming message. in this case, the latest message is always available to the software. ? if the buffer lock function is enabled (lincr1[rblm] set), the most recent message is discarded and the previous message is available in the buffer. 24.7.3 slave mode with identifier filtering in the lin protocol, the identifier of a message is not associated with the address of a node but related to the content of the message. consequently a transmit ter broadcasts its message to all receivers. when a slave node receives a header, it decides?depending on the identifier value?whether the software needs to receive or send a response. if the message does not ta rget the node, it must be discarded without software intervention. checksum error the computed checksum does not match the received checksum if encountered during reception: ? discards the received frame ? generates an interrupt if linier[ceie] is set ? returns to idle state header error an error occurred during header reception (break delimiter error, inconsistent sync field, header timeout) if encountered during header reception, a break field error, an inconsistent sync field, or a timeout: ? discards the header ? generates an interrupt if linier[heie] is set ? returns to idle state table 24-2. errors in slave mode (continued) error description linflexd response to error
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 479 to fulfill this requirement, the linflexd controller provides configurable filt ers in order to request software intervention only if neede d. this hardware filtering saves cp u resources, which would otherwise be needed by software for filtering. the filtering is accomplished through the use of ifcr registers. these registers have the names ifcr0 through ifcr. this section also uses the nomenclature ifcr 2n and ifcr 2n+1 ; in this nomenclature, n is an integer, and the corresponding ifcr register is calculated using the formula in the subscript. 24.7.3.1 filter submodes usually each of the 16 ifcrs is used to filter one dedicated identifier, but this means that the linflexd controller could filter a maximum of 16 id entifiers. in order to be able to handle more identifiers, the filters can be configured to operate as masks. table 24-3 describes the two avai lable filter submodes. the bit mapping and register organization in these two submodes is shown in figure 24-9 . figure 24-9. filter configuration?register organization table 24-3. filter submodes submode description identifier list both filter regi sters are used as identifier r egisters. all bits of the incoming identifier must match the bits specified in the filter register. this is the default submode fo r the linflexd controller. mask the identifier registers are associated with ma sk registers specifying whic h bits of the identifier are handled as ?must match? or as ?don?t care?. ifcr x identifier id bit mapping identifier filter register organization ccs dir identifier filter configuration ifcr 2n identifier identifier ifcr 2n+1 ifm = 0 identifier filter submode ifcr 2n identifier mask ifcr 2n+1 ifm = 1 identifier list submode mask submode dfl
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 480 freescale semiconductor 24.7.3.2 identifier filter submode configuration the identifier filters are configured in the ifcr register s. to configure an identifier filter the filter must first be activated by setting the corresponding bit in th e ifer[fact] field. the subm ode (identifier list or mask) for the corresponding ifcr regi ster is configured by the ifmr[ifm ] field. for each filter, the ifcr register is used to configure: ? the id or mask ? the direction (tx or rx) ? the data field length ? the checksum type if no filter is active, an rx interrupt is generated on any received identifier event. if at least one active filter is conf igured as tx, all received identifiers matching this filter generate a tx interrupt. if at least one active filter is conf igured as rx, all received identifiers matching this filter generate an rx interrupt. if no active filter is configured as rx, all received identi fiers not matching tx filter(s) generate an rx interrupt. further details are provided in table 24-4 and figure 24-10 . table 24-4. filter to interrupt vector correlation number of active filters number of active filters configured as tx number of active filters configured as rx interrupt vector 0 0 0 rx interrupt on all ids a (a > 0) a 0 ? tx interrupt on ids matching the filters ? rx interrupt on all other ids if bf bit is set, no rx interrupt if bf bit is reset n (n = a + b) a (a > 0) b (b > 0) ? tx interrupt on ids matching the tx filters ? rx interrupt on ids matching the rx filters ? all other ids discarded (no interrupt) b (b > 0) 0 b ? rx interrupt on ids matching the filters ? tx interrupt on all other ids if bf bit is set, no tx interrupt if bf bit is reset
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 481 figure 24-10. identifier match index 24.7.4 slave mode with automatic resynchronization automatic resynchronization must be enabled in slave mode if f ipg_clock_lin tolerance is greater than 1.5%. this feature compensates a deviation up to 14%, as specified in the lin standard. this mode is similar to sl ave mode as described in section 24.7.2, slave mode, with the addition of automatic resynchroni zation enabled by the lincr1[lase] bit. in this mode linflexd adjusts the fractional baud rate generator af ter each synch field reception. 24.7.4.1 automatic resynchronization method when automatic resynchronization is enabled, after each lin break, the time dura tion between five falling edges on rdi is sampled on as shown in figure 24-11 . then the lfdiv value (and its associated linibrr and linfbrr registers) is automatically updated at the end of the fifth falling edge. during lin sync field measur ement, the linflexd state m achine is stopped and no data is transferred to the data register. figure 24-11. lin sync field measurement lfdiv is an unsigned fixed point number. the mantissa is coded on 20 bi ts in the linibrr register and the fraction is coded on 4 bits in the linfbrr register. ifmi message0 message1 message2 data pointers table ram @ + lin break break bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 start bit stop bit next start bit lin sync field lfdiv(n) lfdiv(n+1) t br = baud rate period t br delim. t = clock period t br =16.lfdiv.t measurement = 8.t br lfdiv = tbr/(16.t)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 482 freescale semiconductor if lincr1[lase] is set, lfdiv is automatical ly updated at the end of each lin sync field. three registers are used internally to manage the auto-update of the linflexd divider (lfdiv): ? lfdiv_nom (nominal value written by soft ware at linibrr a nd linfbrr addresses) ? lfdiv_meas (results of the field synch measurement) ? lfdiv (used to genera te the local baud rate) on transition to idle, break or break delimiter state due to any error or on rece ption of a complete frame, hardware reloads lfdiv with lfdiv_nom. 24.7.4.2 deviation error on the sync field the deviation error is checke d by comparing the current baud rate (relative to the slave oscillator) with the received lin sync field (relative to the master os cillator). two checks are performed in parallel. the first check is based on a measurement between the fi rst falling edge and the last falling edge of the sync field: ? if d1 > 14.84%, lhe is set. ? if d1 < 14.06%, lhe is not set. ? if 14.06% < d1 < 14.84%, lhe can be either set or reset depending on th e dephasing between the signal on linflexd_rx pin the f ipg_clock_lin clock. the second check is based on a meas urement of time between each fa lling edge of the sync field: ? if d2 > 18.75%, lhe is set. ? if d2 < 15.62%, lhe is not set. ? if 15.62% < d2 < 18.75%, lhe can be either set or reset depending on th e dephasing between the signal on linflexd_rx pin the f ipg_clock_lin clock. note that the linflexd does not need to check if th e next edge occurs slower than expected. this is covered by the check for deviation error on the full synch byte. 24.8 test modes the linflexd controller includes two test modes, loop back mode and self test mode. they can be selected by the lbkm and sftm bits in the lincr1 register. these bits must be configured while linflexd is in initialization mode. after one of the two test modes has been se lected, linflexd must be started in normal mode. 24.8.1 loop back mode linflexd can be put in loop back mode by setting lincr1[lbkm]. in loop back mode, the linflexd treats its own transmitted messages as r eceived messages. this is illustrated in figure 24-12 .
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 483 figure 24-12. linflexd in loop back mode this mode is provided for self-test functions. to be independe nt of external events , the lin core ignores the linrx signal. in this mode, the linflexd performs an internal fee dback from its tx output to its rx input. the actual value of the linr x input pin is disregarded by the linflexd. the transmitted messages can be monitored on the lintx pin. 24.8.2 self test mode linflexd can be put in self te st mode by setting linc r1[lbkm] and lincr1[s ftm]. this mode can be used for a hot self test, meaning the linflexd can be tested as in loop back mode but without affecting a running lin syst em connected to the lintx and linrx pins. in this mode, the linrx pin is disconnected from the li nflexd and the lintx pin is held recessive. th is is illustrated in figure 24-13 . figure 24-13. linflexd in self test mode 24.9 uart mode the main features of uart mode are presented in section 24.2.2, uart mode features . 24.9.1 data frame structure 24.9.1.1 8-bit data frame the 8-bit uart data frame is shown in figure 24-14 . the 8th bit can be a data or a parity bit. parity (even, odd, 0, or 1) can be selected by the uartcr[pc] field. an even parity is set if the modulo-2 sum of the 7 data bits is 1. an odd parity is cleared in this case. lintx linrx linflexd tx rx linflexd lintx linrx tx rx =1
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 484 freescale semiconductor figure 24-14. uart mode 8-bit data frame 24.9.1.2 9-bit data frame the 9-bit uart data frame is shown in figure 24-15 . the 9th bit is a parity b it. parity (even, odd, 0, or 1) can be selected by the by the uartcr[ pc] field. an even parity is set if the modulo-2 su m of the 8 data bits is 1. an odd parity is cleared in this case. parity 0 forces a zero logical valu e. parity 1 forces a high logical value. figure 24-15. uart mode 9-bit data frame 24.9.1.3 16-bit data frame the 16-bit uart data frame is shown in figure 24-16 . the 16th bit can be a data or a parity bit. parity (even, odd, 0, or 1) can be selected by the uartcr[pc] field. pa rity 0 forces a zero logical value. parity 1 forces a high logical value. figure 24-16. uart mode 16-bit data frame 24.9.1.4 17-bit data frame the 17-bit uart data frame is shown in figure 24-17 . the 17th bit is the parity bit. parity (even, odd, 0, or 1) can be selected by the uartcr [pc] field. parity 0 forces a zero l ogical value. parity 1 forces a high logical value. start bit d0 d7 stop bit byte field ? data bit ? parity bit d1 d2 d3 d4 d5 d6 start bit d0 d7 stop bit byte field ? parity bit d1 d2 d3 d4 d5 d6 d8 start bit d0 d15 stop bit byte field ? data bit ? parity bit d1 d2 ... ... d13 d14
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 485 figure 24-17. uart mode 17-bit data frame 24.9.2 buffer the 8-byte buffer is divided into two parts?one fo r receiver and one for tr ansmitter?as shown in table 24-5 . for 16-bit frames, the lower 8 bits will be written in bdr0 and the upper 8 bits will be written in bdr1. 24.9.3 uart transmitter in order to start transmission in uart mode, th e uartcr[uart] and uartcr [txen] bits must be set. transmission starts when bdr0 (least significa nt data byte) is programmed. the number of bytes transmitted is equal to the value confi gured by the uartcr[tdfltfc] field (see table 24-16 ). the transmit buffer size is as follows: ? 4 bytes when uartcr[wl1] = 0 ? 2 half-words when uartcr[wl1] = 1 therefore, the maximum transmission that can be triggered is 4 bytes (2 half-words). after the programmed number of bytes has be en transmitted, the uartsr[dtftff] flag is set. if the uartcr[txen] field is cleared dur ing a transmission, the current tr ansmission is completed, but no further transmission can be invoked. the buffer can be configured in fifo mode (mandatory when dma tx is enabled) by setting uartcr[tfbm]. the access to the bdrl register is shown in table 24-6 . table 24-5. uart buffer structure bdr uart mode 0tx0 1tx1 2tx2 3tx3 4rx0 5rx1 6rx2 7rx3 start bit d0 d16 stop bit byte field ? parity bit d1 d2 ... d13 d14 d15
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 486 freescale semiconductor 24.9.4 uart receiver reception of a data byte is star ted as soon as the software comple tes the following tasks in order: 1. exits initialization mode 2. sets the uartcr[rxen] field 3. detects the start bit there is a dedicated data buffer for recei ved data bytes. its size is as follows: ? 4 bytes when uartcr[wl1] = 0 ? 2 half-words when uartcr[wl1] = 1 after the programmed number (rdfl bits) of bytes has been receive d, the uartsr[drfrfe] field is set. if the uartcr[rxen] field is cleared during a reception, the current recep tion is completed, but no further reception can be invoked unt il uartcr[rxen] is set again. the buffer can be configured in fifo mode (r equired when dma rx is enabled) by setting uartcr[rfbm]. table 24-6. bdrl access in uart mode access mode 1 1 as specified by uartcr[tfbm] word length 2 2 as specified by the wl1 and wl0 bi ts of the uartcr register. in uart fifo mode (uartcr[tfbm] = 1),any read operation causes an ips transfer error. ips operation result write byte0 fifo byte ok write byte1-2-3 fifo byte ips transfer error write half-word0-1 fifo byte ips transfer error write word fifo byte ips transfer error write byte0-1-2-3 fifo half-word ips transfer error write half-word0 fifo half-word ok write half-word1 fifo half-word ips transfer error write word fifo half-word ips transfer error read byte0-1-2-3 fifo byte/half-word ips transfer error read half-word0-1 fifo byte/half-word ips transfer error read word fifo byte/half-word ips transfer error write byte0-1-2-3 buffer byte/half-word ok write half-word0-1 buffer byte/half-word ok write word buffer byte/half-word ok read byte0-1-2-3 buffer byte/half-word ok read half-word0-1 buffer byte/half-word ok read word buffer byte/half-word ok
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 487 the access to the bdrm register is shown in table 24-7 . table 24-8 lists some common scenarios, controller re sponses, and suggestions when the linflexd controller is acting as a uart receiver. table 24-7. bdrm access in uart mode access mode 1 1 as specified by uartcr[rfbm] word length 2 2 as specified by the wl1 and w l0 bits of the uartcr register ips operation result read byte4 fifo byte ok read byte5-6-7 fifo byte ips transfer error read half-word2-3 fifo byte ips transfer error read word fifo byte ips transfer error read byte4-5-6-7 fifo half-word ips transfer error read half-word2 fifo half-word ok read half-word3 fifo half-word ips transfer error read word fifo half-word ips transfer error write byte4-5-6-7 fifo byte/half-word ips transfer error write half-word2-3 fifo byte/half-word ips transfer error write word fifo byte/half-word ips transfer error read byte4-5-6-7 buffer byte/half-word ok read half-word2-3 buffer byte/half-word ok read word buffer byte/half-word ok write byte4-5-6-7 buffer byte/half-word ips transfer error write half-word2-3 buffer byte/half-word ips transfer error write word buffer byte/half-word ips transfer error table 24-8. uart receiver scenarios scenario responses and suggestions the software does not know (in advance) how many bytes will be received. do not program uartcr[rdflrfc] in advance. when this field is zero (as it is after reset), reception occurs on a byte-by-byte basis. therefore, the state machine will move to idle state after each byte is received. uartcr[rdflrfc] is programmed for a certain number of bytes received, but the actual number of bytes received is smaller. the reception will hang. in this case, the software must monitor the uartsr[to] field, and move to idle state by setting lincr1[sleep].
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 488 freescale semiconductor 24.10 memory map and register description 24.10.1 lin control register 1 (lincr1) a stop request arrives before the reception is completed. the request is acknowledged only after the programmed number of data bytes are received. in other words, the stop request is not serviced immediately. in this case, the software must monitor the uartsr[to] field and move the state machine to idle state as appropriate. the stop request will be serviced only after this is complete. a parity error occurs during the reception of a byte. the corresponding uartsr[pe n ] field is set. no interrupt is generated. a framing error occurs during the reception of a byte. ? uartsr[fe] is set. ? if linier[feie] = 1, an interrupt is generated. this interrupt is helpful in identifying which byte has the framing error, since there is only one register bit for framing errors. a new byte has been received, but the last received frame has not been read from the buffer (uartsr[rmb] has not yet been cleared by the software) ? an overrun error will occur (uartsr[bof] will be set). ? one message will be lost (depending on the setting of lincr[rblm]). ? an interrupt is generated if linier[boie] is set. offset:0x00 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ccd 1 cfd 1 lase 1 awum 1 mbl 1 bf 1 sft m 1 lbkm 1 mme 1 sbdt 1 rblm 1 sleep init w reset000000001000/1 2 0010 1 these fields are writable only in initialization mode (lincr1[init] = 1). 2 resets to 0 in slave mode and to 1 in master mode figure 24-18. lin control register 1 (lincr1) table 24-8. uart receiver scenarios (continued) scenario responses and suggestions
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 489 table 24-9. lincr1 field descriptions field description ccd checksum calculation disable this bit is used to disable the checksum calculation (see table 24-10 ). 0: checksum calculation is done by hardware. when th is bit is reset the lincfr register is read-only. 1: checksum calculation is disabled. when this bit is set the lincfr register is read/write. user can program this register to send a software calculated crc (provided cfd is reset). note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. cfd checksum field disable this bit is used to disable the checksum field transmission (see table 24-10 ). 0: checksum field is sent after the r equired number of data bytes is sent. 1: no checksum field is sent. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. lase lin slave automatic resynchronization enable 0: automatic resynch ronization disable 1: automatic resynch ronization enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. awum automatic wake-up mode this bit controls the behavior of the linflexd hardware during sleep mode. 0: the sleep mode is exited on software request by clearing the sleep bit of the lincr register. 1: the sleep mode is exit ed automatically by ha rdware on rx dominant state detection. the sleep bit of the lincr register is cleared by hardware whenever wuf bit in linsr is set. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. mbl lin master break length these bits indicate the break length in master mode (see ta b l e 2 4 - 1 1 ). note: these bits can be written in initialization mode only. they are read-only in normal or sleep mode. bf bypass filter 0: no interrupt if id does not match any filter 1: an rx interrupt is generat ed on id not matching any filter notes: ? if no filter is activated, this bit is reserved. ? this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sftm self test mode this bit controls the self test mode. for more details please refer to section 24.8.2, self test mode . 0: self test mode disable 1: self test mode enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. lbkm loop back mode this bit controls the loop back mode. for more details please refer to section 24.8.1, loop back mode . 0: loop back mode disable 1: loop back mode enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode mme master mode enable 0: slave mode enable 1: master mode enable note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 490 freescale semiconductor sbdt slave mode break detection threshold 0: 11-bit break 1: 10-bit break note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. rblm receive buffer locked mode 0: receive buffer not locked on overrun. once the slave receive buffer is full the next incoming message overwrites the previous one. 1: receive buffer locked against overrun. once t he receive buffer is full the next incoming message is discarded. note: this bit can be written in initialization mode only. it is read-only in normal or sleep mode. sleep sleep mode request this bit is set by software to request linflexd to enter sleep mode. this bit is cleared by software to exit sleep mode or by hardware if the awum bit in lincr1 and the wuf bit in linsr are set (see table 24-12 ). init initialization request the software sets this bit to switch hardware in to initialization mode. if the sleep bit is reset, linflexd enters normal mode when clearing the init bit (see table 24-12 ). table 24-10. checksum bits configuration cfd ccd lincfr checksum sent 1 1 read/write none 1 0 read-only none 0 1 read/write programmed in lincfr by bits cf[0:7] 0 0 read-only hardware calculated table 24-11. lin master break length selection mbl length 0000 10-bit 0001 11-bit 0010 12-bit 0011 13-bit 0100 14-bit 0101 15-bit 0110 16-bit 0111 17-bit 1000 18-bit 1001 19-bit 1010 20-bit table 24-9. lincr1 field descriptions (continued) field description
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 491 24.10.2 lin interrupt en able register (linier) 1011 21-bit 1100 22-bit 1101 23-bit 1110 36-bit 1111 50-bit table 24-12. operating mode selection sleep init operating mode 1 0 sleep (reset value) x 1 initialization 00normal offset: 0x04 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szie ocie beie ceie heie 0 0 feie boie lsie wuie dbfie dbeietoie drie dtie hrie w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 24-19. lin interrupt enable register (linier) table 24-13. linier field descriptions field description szie stuck at zero interrupt enable 0: no interrupt when szf bit in linesr or uartsr is set 1: interrupt generated when szf bit in linesr or uartsr is set table 24-11. lin master break length selection (continued) mbl length
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 492 freescale semiconductor ocie output compare interrupt enable 0: no interrupt when ocf bit in linesr or uartsr is set 1: interrupt generated when ocf bit in linesr or uartsr is set beie bit error interrupt enable 0: no interrupt when bef bit in linesr is set 1: interrupt generated when bef bit in linesr is set ceie checksum error interrupt enable 0: no interrupt on checksum error 1: interrupt generated when checksum error flag (cef) is set in linesr heie header error interrupt enable 0: no interrupt on break delimiter error, synch field error, id field error 1: interrupt generated on break delimiter error, synch field error, id field error feie framing error interrupt enable 0: no interrupt on framing error 1: interrupt generated on framing error boie buffer overrun interrupt enable 0: no interrupt on buffer overrun 1: interrupt generated on buffer overrun lsie lin state interrupt enable 0: no interrupt on lin state change 1: interrupt generated on lin state change this interrupt can be used for debugging purposes. it has no status flag but is reset when writing 1111 into the lin state bits in the linsr register. wuie wake-up interrupt enable 0: no interrupt when wuf bit in linsr or uartsr is set 1: interrupt generated when wuf bit in linsr or uartsr is set dbfie data buffer full interrupt enable 0: no interrupt when buffer data register is full 1: interrupt generated when data buffer register is full dbeietoie data buffer empty interrupt enable / timeout interrupt enable 0: no interrupt when buffer data register is empty 1: interrupt generated when data buffer register is empty note: an interrupt is generated if this bit is set and one of the following is true: linflexd is in lin mode and linsr[dbef] is set linflexd is in uart mode and uartsr[to] is set drie data reception complete interrupt enable 0: no interrupt when data reception is completed 1: interrupt generated when data received flag (drf) in linsr or uartsr is set dtie data transmitted interrupt enable 0: no interrupt when data transmission is completed 1: interrupt generated when data transmitted flag (dtf) is set in linsr or uartsr register hrie header received interrupt enable 0: no interrupt when a valid lin header has been received 1: interrupt generated when a valid lin header has b een received, that is, hrf bit in linsr register is set table 24-13. linier field descriptions (continued) field description
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 493 24.10.3 lin status register (linsr) offset: 0x08 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r lins 00rmb0 rbsy rps wuf dbff dbef drf dtf hrf ww1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000001000000 figure 24-20. lin status register (linsr)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 494 freescale semiconductor table 24-14. linsr field descriptions field description lins lin state lin mode states description 0000: sleep mode linflexd is in sleep mode to save power consumption. 0001: initialization mode linflexd is in initialization mode. 0010: idle this state is entered on several events: ? sleep bit and init in lincr1 register have been cleared by software, ? a falling edge has been received on rx pin and awum bit is set, ? the previous frame reception or transmission has been completed or aborted. 0011: break in slave mode, a falling edge followed by a dom inant state has been detec ted. receiving break. note: in slave mode, in case of error new lin state can be either idle or break depending on last bit state. if last bit is dominant new lin state is break, otherwise idle. in master mode, break transmission ongoing. 0100: break delimiter in slave mode, a valid break has been detected. refer to lincr1 register for break length configuration (10-bit or 11-bit). waiting for a rising edge. in master mode, break transmission has been comp leted. break delimiter transmission is ongoing. 0101: synch field in slave mode, a valid break delimiter has been detec ted (recessive state for at least one bit time). receiving synch field. in master mode, synch field transmission is ongoing. 0110: identifier field in slave mode, a valid synch field has been received. receiving id field. in master mode, identifier transmission is ongoing. 0111: header reception/t ransmission completed in slave mode, a valid header has been received and id entifier field is available in the bidr register. in master mode, header transmission is completed. 1000: data reception/transmission response reception/transmission is ongoing. 1001: checksum data reception/transmission completed. checksum reception/transmission ongoing. in uart mode, only the following states are flagged by the lin state bits: ?init ?sleep ?idle ? data transmission/reception rmb release message buffer 0: buffer is free 1: buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. rbsy receiver busy flag 0: receiver is idle 1: reception ongoing note: in slave mode, after header reception, if dir bi t in bidr is reset and reception starts then this bit is set. in this case, user cannot set dtrq bit in lincr2. rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 495 wuf wake-up flag this bit is set by hardware and indicates to the software that linflexd has detected a falling edge on the linrx pin when ? slave is in sleep mode, ? master is in sleep mode or idle state. this bit must be cleared by software. it is reset by hardware in initializati on mode. an interrupt is generated if wuie bit in linier is set. dbff data buffer full flag this bit is set by hardware and indicates the buffer is full. it is set only when receiving extended frames (dfl > 7). this bit must be cleared by software. it is reset by hardware in initialization mode. dbef data buffer empty flag this bit is set by hardware and indicates the buffer is empty. it is set only when transmitting extended frames (dfl > 7). this bit must be cleared by software, once buffer has been filled again, in order to start transmission. this bit is reset by hardware in initialization mode. drf data reception completed flag this bit is set by hardware and indicates the data reception is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in ca se of bit error or framing error. dtf data transmission completed flag this bit is set by hardware and indicates the data transmission is completed. this bit must be cleared by software. it is reset by hardware in initialization mode. note: this flag is not set in case of bit error if iobe bit is reset. hrf header reception flag this bit is set by hardware and indicates a valid header reception is completed. this bit must be cleared by software. this bit is reset by hardware in initialization mode and at end of completed or aborted frame. note: if filters are enabled, this bit is set only when identifier software filtering is required, that is to say: ? all filters are inactive and bf bit in lincr1 is set ? no match in any filter and bf bit in lincr1 is set ? tx filter match table 24-14. linsr field descriptions (continued) field description
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 496 freescale semiconductor 24.10.4 lin error status register (linesr) offset: 0x0c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf bef cef sfef bdef idpef fef bof 0 0 0 000nf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 24-21. lin error status register (linesr) table 24-15. linesr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. it is cleared by software. ocf output compare flag 0: no output compare event occurred 1: the content of the count er has matched the content of oc1[0:7] or oc2[0:7] in linocr. if this bit is set and iot bit in lintcsr is se t, linflexd moves to idle state. if ltom bit in lintcsr register is set then ocf is reset by hardware in initialization mode. if ltom bit is reset, then ocf maintains its status whatever the mode is. bef bit error flag this bit is set by hardware and indicates to the soft ware that linflexd has detected a bit error. this error can occur during response field transmission (slave and master modes) or during header transmission (in master mode). this bit is cleared by software. cef checksum error flag this bit is set by hardware and indicates that the received checksum does not match the hardware calculated checksum. this bit is cleared by software. note: this bit is never set if ccd or cfd bit in lincr1 register is set. sfef synch field error flag this bit is set by hardware and indicates that a synch field error occurred (inconsistent synch field). bdef break delimiter error flag this bit is set by hardware and indicates that the received break delimiter is too short (less than one bit time).
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 497 24.10.5 uart mode cont rol register (uartcr) idpef identifier parity error flag this bit is set by hardware and indicates that a identifier parity error occurred. note: header interrupt is triggered when sfef or bdef or idpef bit is set and heie bit in linier is set. fef framing error flag this bit is set by hardware and indicates to the so ftware that linflexd has detected a framing error (invalid stop bit). this error can occur during reception of any data in the response field (master or slave mode) or during reception of synch field or identifier field in slave mode. bof buffer overrun flag this bit is set by hardware when a new data byte is received and the buffer full flag is not cleared. if rblm in lincr1 is set then the new byte received is discarded. if rblm is reset then the new byte overwrites the buffer. it can be cleared by software. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. offset: 0x10 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tdfltfc 1 rdflrfc 1 rfbm tfbm 2 wl[1] 2 pc1 2 rxen txen pc0 2 pce 2 wl[0] 2 uart 2 w reset0000000000000000 1 these fields are read/write in uart bu ffer mode and read-only in other modes. 2 these fields are writable only in initialization mode (l incr1[init] = 1). figure 24-22. uart mode control register (uartcr) table 24-15. linesr field descriptions (continued) field description
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 498 freescale semiconductor table 24-16. uartcr field descriptions field description tdfltfc transmitter data field length / tx fifo counter this field has one of two functions depending on the mode of operation as follows: ? when linflexd is in uart buffer mode (tfb m = 0), tdfltfc defines the number of bytes to be transmitted. the field is read/write in this c onfiguration. the first bit is reserved and not implemented. the permissible values are as follows (with x representing the unimplemented first bit): 0bx00: 1 byte 0bx01: 2 bytes 0bx10: 3 bytes 0bx11: 4 bytes when the uart data length is configured as half -word (wl = 0b10 or 0b11), the only valid values for tdfltfc are 0b001 and 0b011. ? when linflexd is in uart fifo mode (tfb m = 1), tdfltfc contains the number of entries (bytes) of the tx fifo. the field is read-only in this configuration. the permissible values are as follows: 0b000: empty 0b001: 1 byte 0b010: 2 bytes 0b011: 3 bytes 0b100: 4 bytes all other values are reserved. this field is meaningful and can be programmed only when the uart bit is set. rdflrfc receiver data field length / rx fifo counter this field has one of two functions depending on the mode of operation as follows: ? when linflexd is in uart buffer mode (rfb m = 0), rdflrfc defines the number of bytes to be received. the field is read/write in this configurat ion. the first bit is reserved and not implemented. the permissible values are as follows (with x representing the unimplemented first bit): 0bx00: 1 byte 0bx01: 2 bytes 0bx10: 3 bytes 0bx11: 4 bytes when the uart data length is configured as half -word (wl = 0b10 or 0b11), the only valid values for rdflrfc are 0b001 and 0b011. ? when linflexd is in uart fifo mode (rfb m = 1), rdflrfc contains the number of entries (bytes) of the rx fifo. the field is read-only in this configuration. the permissible values are as follows: 0b000: empty 0b001: 1 byte 0b010: 2 bytes 0b011: 3 bytes 0b100: 4 bytes all other values are reserved. this field is meaningful and can be programmed only when the uart bit is set. rfbm rx fifo/buffer mode 0 rx buffer mode enabled 1 rx fifo mode enabled (mandatory in dma rx mode) this field can be programmed in initialization mode only when the uart bit is set.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 499 tfbm tx fifo/buffer mode 0 tx buffer mode enabled 1 tx fifo mode enabled (mandatory in dma tx mode) this field can be programmed in initialization mode only when the uart bit is set. rxen receiver enable 0: receiver disabled 1: receiver enabled this field can be programmed only when the uart bit is set. txen transmitter enable 0: transmitter disabled 1: transmitter enabled this field can be programmed only when the uart bit is set. note: transmission starts when this bit is set and when writing data0 in the bdrl register. pc parity control 00 parity sent is even 01 parity sent is odd 10 a logical 0 is always transmitted/checked as parity bit 11 a logical 1 is always transmitted/checked as parity bit this field can be programmed in initialization mode only when the uart bit is set. pce parity control enable 0: parity transmit/check disabled 1: parity transmit/check enabled this field can be programmed in initialization mode only when the uart bit is set. wl word length in uart mode 00 7 bits data + parity 01 8 bits data when pce = 0 or 8 bits data + parity when pce = 1 10 15 bits data + parity 11 16 bits data when pce = 0 or 16 bits data + parity when pce = 1 this field can be programmed in initialization mode only when the uart bit is set. uart uart mode enable 0: lin mode 1: uart mode this field can be programmed in initialization mode only. table 24-16. uartcr field descriptions (continued) field description
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 500 freescale semiconductor 24.10.6 uart mode status register (uartsr) offset: 0x14 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r szf ocf pe3 pe2 pe1 pe0 rmb fef bof rps wuf 0 to drfrfe dtftff nf w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset0000000000000000 figure 24-23. uart mode status register (uartsr) table 24-17. uartsr field descriptions field description szf stuck at zero flag this bit is set by hardware when the bus is dominant for more than a 100-bit time. it is cleared by software. ocf ocf output compare flag 0: no output compare event occurred 1: the content of the counter has matched the content of oc1[0:7] or oc2[0:7] in linocr. an interrupt is generated if the ocie bit in linier register is set. pe3 parity error flag rx3 this bit indicates if there is a parity error in the corresponding received byte (rx3). no interrupt is generated if this error occurs. 0: no parity error 1: parity error pe2 parity error flag rx2 this bit indicates if there is a parity error in the corresponding received byte (rx2). no interrupt is generated if this error occurs. 0: no parity error 1: parity error pe1 parity error flag rx1 this bit indicates if there is a parity error in the corresponding received byte (rx1). no interrupt is generated if this error occurs. 0: no parity error 1: parity error pe0 parity error flag rx0 this bit indicates if there is a parity error in the corresponding received byte (rx0). no interrupt is generated if this error occurs. 0: no parity error 1: parity error
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 501 rmb release message buffer 0: buffer is free 1: buffer ready to be read by software. this bit must be cleared by software after reading data received in the buffer. this bit is cleared by hardware in initialization mode. fef framing error flag this bit is set by hardware and indicates to the so ftware that linflexd has detected a framing error (invalid stop bit). bof fifo/buffer overrun flag this bit is set by hardware when a new data byte is received and the rmb bit is not cleared in uart buffer mode. in uart fifo mode, this bit is set when there is a new byte and the rx fifo is full. in uart fifo mode, once rx fifo is full, the new received message is discarded regardless of the value of lincr1[rblm]. if lincr1[rblm] = 1, the new byte received is discarded. if lincr1[rblm] = 0, the new byte overwrites buffer. this field can be cleared by writing a 1 to it. an interrupt is generated if linier[boie] is set. rps lin receive pin state this bit reflects the current status of linrx pin for diagnostic purposes. wuf wake-up flag this bit is set by hardware and indicates to the software that linflexd has detected a falling edge on the linrx pin in sleep mode. this bit must be cleared by software. it is reset by hardware in initialization mode. an interrupt i generated if wuie bit in linier is set. to timeout the linflexd controller sets this field when a ua rt timeout occurs ? that is, when the value of uartcto becomes equal to the preset value of the timeout (uartpto register setting). this field should be cleared by software. the gcr[sr] field should be used to reset the receiver fsm to idle state in case of uart timeout for uart recept ion depending on the application both in buffer and fifo mode. an interrupt is generated when li nier[dbeietoie] is set on the error interrupt line in uart mode. drfrfe data reception complete d flag / rx fifo empty flag the linflexd controller sets this field as follows: ? in uart buffer mode (rfbm = 0), it indicates t hat the number of bytes programmed in rdfl has been received. this field should be cleared by soft ware. an interrupt is generated if linier[drie] is set. this field is set in case of framing error, pa rity error, or overrun. th is field reflects the same value as in linesr when in initialization mode and uart bit is set. ? in uart fifo mode (rfbm = 1), it indicates that the rx fifo is empty. this field is a read-only field used internally by the dma rx interface. dtftff data transmission completed flag / tx fifo full flag the linflexd controller sets this field as follows: ? in uart buffer mode (tfbm = 0), it indicates that the data transmission is completed. this field should be cleared by software. an interrupt is gener ated if linier[dtie] is set. this field reflects the same value as in linesr when in initialization mode and uart bit is set. ? in uart fifo mode (tfbm = 1), it indicates that th e tx fifo is full. this field is a read-only field used internally by the dma tx interface. nf noise flag this bit is set by hardware when noise is detected on a received character. this bit is cleared by software. table 24-17. uartsr field descriptions (continued) field description
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 502 freescale semiconductor 24.10.7 lin timeout control status register (lintcsr) offset: 0x18 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reset0000001000000000 1 these fields are writable only in initialization mode (l incr1[init] = 1). figure 24-24. lin timeout control status register (lintcsr) table 24-18. lintcsr field descriptions name description ltom lin timeout mode 0: lin timeout mode (header, re sponse and frame timeout detection) 1: output compare mode this bit can be set/cleared in initialization mode only. iot idle on timeout 0: lin state machine not reset to idle on timeout event 1: lin state machine reset to idle on timeout event this bit can be set/cleared in initialization mode only. toce timeout counter enable 0: timeout counter disable. ocf bit in linesr or uartsr is not set on an output compare event. 1: timeout counter enable. ocf bit is set if an output compare event occurs. toce bit is configurable by software in initialization mode. if lin state is not init and if timer is in lin timeout mode, then hardware takes control of toce bit. cnt counter value these bits indicate the lin timeout counter value.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 503 24.10.8 lin output comp are register (linocr) offset: 0x1c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 roc2 1 oc1 1 ww1c 1 w1c 1 reset1111111111111111 1 if lintcsr[ltom] = 0, these fields are read-only. figure 24-25. lin output compare register (linocr) table 24-19. linocr field descriptions field description oc2 output compare 2 value these bits contain the value to be co mpared to the val ue of lintcsr[cnt]. oc1 output compare 1 value these bits contain the value to be co mpared to the val ue of lintcsr[cnt].
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 504 freescale semiconductor 24.10.9 lin timeout cont rol register (lintocr) offset: 0x20 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 rto 0 hto 3 w reset00001110000/1 1 0/1 2 1100 1 resets to 1 in slave mode and to 0 in master mode 2 resets to 0 in slave mode and to 1 in master mode 3 hto field can only be written in slave mode, lincr1[mme] = 0. figure 24-26. lin timeout control register (lintocr) table 24-20. lintocr field descriptions field description rto response timeout value this register contains the response ti meout duration (in bit time) for 1 byte. the reset value is 0xe = 14, corresponding to t response_maximum =1.4xt response_nominal hto header timeout value this register contains the header timeout duration (i n bit time). this value does not include the first 11 dominant bits of the break. the reset val ue depends on which mode linflexd is in. hto can be written only for slave mode.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 505 24.10.10 lin fractional baud rate register (linfbrr) 24.10.11 lin integer baud rate register (linibrr) offset: 0x24 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 0000 div_f 1 w reset0000000000000000 1 this field is writable only in in itialization mode, lincr1[init] = 1. figure 24-27. lin timeout control register (lintocr) table 24-21. linfbrr field descriptions field description div_f fraction bits of lfdiv the 4 fraction bits define the value of the fraction of the linflexd divider (lfdiv). fraction (lfdiv) = decimal value of div_f / 16. this register can be written in in itialization mode only, lincr1[init] = 1. offset: 0x28 access: user read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 0000 div_m 1 w reset00000000000000000000000000000000 1 this field is writable only in initialization mode (lincr1[init] = 1). figure 24-28. lin integer ba ud rate register (linibrr)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 506 freescale semiconductor 24.10.12 lin checksum field register (lincfr) table 24-22. linibrr field descriptions field description div_m lfdiv mantissa these bits define the linflexd di vider (lfdiv) mantissa value (see table 24-23 ). this register can be written in initialization mode only. table 24-23. integer baud rate selection div_m mantissa 0x0 lin clock disabled 0x1 1 ... ... 0xffffe 1048574 0xfffff 1048575 offset: 0x2c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 cf w reset0000000000000000 figure 24-29. lin checksum field register (lincfr) table 24-24. lincfr field descriptions field description cf checksum bits when lincr1[ccd] is cleared, these bits are read-only. when lincr1 [ccd] is set, these bits are read/write. see table 24-10 .
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 507 24.10.13 lin control register 2 (lincr2) offset: 0x30 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 iobe 1 iope 1 wurq ddrq dtrq abrq htrq 0 0 0 0 0 0 0 0 w w1c w1c w1c w1c w1c reset 0 1 0/1 2 0000000000000 1 these fields are writable only in initialization mode (lincr1[init] = 1. 2 resets to 1 in slave mode and to 0 in master mode figure 24-30. lin control register 2 (lincr2) table 24-25. lincr2 field descriptions field description iobe idle on bit error 0: bit error does not reset lin state machine 1: bit error reset lin state machine this bit can be set/cleared in init ialization mode only (lincr1[init]) = 1. iope idle on identifier parity error 0: identifier parity error does not reset lin state machine. 1: identifier parity erro r reset lin state machine. this bit can be set/cleared in init ialization mode only (lincr1[init]) = 1. wurq wake-up generation request setting this bit generates a wake-up pulse. it is reset by hardware when the wake-up character has been transmitted. the character sent is copied from data0 in bdrl buffer. note that this bit cannot be set in sleep mode. software has to exit sleep mode before requesting a wake-up. bit error is not checked when transmitting the wake-up request. ddrq data discard request set by software to stop data reception if the fram e does not concern the node. this bit is reset by hardware once linflexd has moved to idle state. in slave mode, this bit can be set only when hrf bit in linsr is set and identi fier did not match any filter. dtrq data transmission request set by software in slave mode to request the transmission of the lin data field stored in the buffer data register. this bit can be set only when hrf bit in linsr is set. cleared by hardware when the request has been completed or aborted or on an error condition. in master mode, this bit is set by hardware when dir bit in bidr is set and header transmission is completed.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 508 freescale semiconductor 24.10.14 buffer identifier register (bidr) this register contains the fields that identify a transaction and provi de other information related to it. all the fields in this regi ster must be updated when an id filter (enabled) in sl ave mode (tx or rx) matches the id received. abrq abort request set by software to abort the current transmission. cleared by hardware when the transmission has been a borted. linflexd aborts the transmission at the end of the current bit. this bit can also abort a wake-up request. it can also be used in uart mode. htrq header transmission request set by software to request the transmission of the lin header. cleared by hardware when the request has been completed or aborted. this bit has no effect in uart mode. offset: 0x34 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reset0000000000000000 figure 24-31. buffer identifier register (bidr) table 24-26. bidr field descriptions field description dfl data field length these bits define the number of data byte s in the response part of the frame. dfl = number of data bytes ? 1. normally, lin uses only dfl[0:2] to manage frames wit h a maximum of 8 bytes of data. identifier filters are compatible with dfl[0:2] and dfl[0:5] . df l[3:5] are provided to manage extended frames. dir direction this bit controls the dire ction of the data field. 0: linflexd receives the data and copy them in the bdr registers. 1: linflexd transmits the data from the bdr registers. table 24-25. lincr2 field descriptions (continued) field description
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 509 24.10.15 buffer data regist er least significant (bdrl) ccs classic checksum this bit controls the type of checksum applied on the current message. 0: enhanced checksum covering identifier and data fiel ds. this is compatible with lin specification 2.0 and higher. 1: classic checksum covering data fields only. this is compatible with lin sp ecification 1.3 and below. id identifier identifier part of the identifier field without the identifier parity. offset: 0x38 access: user read/write 0123456789101112131415 r data3 data2 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data1 data0 w reset0000000000000000 figure 24-32. buffer data register least significant (bdrl) table 24-27. bdrl field descriptions field description data3 data byte 3 data byte 3 of the data field data2 data byte 2 data byte 2 of the data field data1 data byte 1 data byte 1 of the data field data0 data byte 0 data byte 0 of the data field table 24-26. bidr field descriptions (continued) field description
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 510 freescale semiconductor 24.10.16 buffer data regist er most significant (bdrm) offset: 0x3c access: user read/write 0123456789101112131415 r data7 data6 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r data5 data4 w reset0000000000000000 figure 24-33. buffer data regi ster most significant (bdrm) table 24-28. bdrm field descriptions field description data7 data byte 7 data byte 7 of the data field data6 data byte 6 data byte 6 of the data field data5 data byte 5 data byte 5 of the data field data4 data byte 4 data byte 4 of the data field
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 511 24.10.17 identifier filter enable register (ifer) offset: 0x40 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 0000 fact 1 w reset0000000000000000 1 this field is writable only in initialization mode (lincr1[init] = 1). figure 24-34. identifier filter enable register (ifer) table 24-29. ifer field descriptions field description fact filter activation (see ta b l e 2 4 - 3 0 ) the software sets the bit fact[x] to acti vate the filters x in identifier list mode. in identifier mask mode bits fact(2n + 1) have no ef fect on the corresponding filters as they act as masks for the identifiers 2n. 0 filters 2n and 2n + 1 are deactivated. 1 filters 2n and 2n + 1 are activated. table 24-30. ifer[fact] configuration bit value result fact[0] 0 filters 0 and 1 are deactivated. 1 filters 0 and 1 are activated. fact[1] 0 filters 2 and 3 are deactivated. 1 filters 2 and 3 are activated. fact[2] 0 filters 4 and 5 are deactivated. 1 filters 4 and 5 are activated. fact[3] 0 filters 6 and 7 are deactivated. 1 filters 6 and 7 are activated. fact[4] 0 filters 8 and 9 are deactivated. 1 filters 8 and 9 are activated.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 512 freescale semiconductor 24.10.18 identifier filter match index (ifmi) fact[5] 0 filters 10 and 11 are deactivated. 1 filters 10 and 11 are activated. fact[6] 0 filters 12 and 13 are deactivated. 1 filters 12 and 13 are activated. fact[7] 0 filters 14 and 15 are deactivated. 1 filters 14 and 15 are activated. offset: 0x44 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reset0000000000000000 figure 24-35. identifier filter match index (ifmi) table 24-31. ifmi field descriptions field description ifmi filter match index this register contains the index corresponding to the re ceived id. it can be used to directly write or read the data in ram (refer to section 24.7.2, slave mode, for more details). when no filter matches, ifmi = 0. when filter n is matching, ifmi = n + 1. table 24-30. ifer[fact] configuration (continued) bit value result
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 513 24.10.19 identifier filter mode register (ifmr) 24.10.20 identifier filter control registers (ifcr0?ifcr15) the function of these registers is different depending on which mode the linflexd controller is in, as described in table 24-33 . offset:0x48 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reset0000000000000000 figure 24-36. identifier filter mode register (ifmr) table 24-32. ifmr field descriptions field description ifm filter mode 0 filters 2 n and 2 n + 1 are in identifier list mode. 1 filters 2 n and 2 n + 1 are in mask mode (filter 2 n + 1 is the mask for the filter 2 n ). table 24-33. ifcr functionality based on mode mode ifcr functionality identifier list each ifcr regi ster acts as a filter. identifier mask if a = (number of f ilters) / 2, and n = 0 to (a ? 1), then ifcr[2n] acts as a filter and if cr[2n + 1] acts as the mask for ifcr[2n].
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 514 freescale semiconductor 24.10.21 global control register (gcr) this register can be programmed only in initialization mode. the configuration specified in this register applies in both lin and uart modes. offsets: 0x4c?0x88 (16 regist ers) access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dfl 1 dir 1 ccs 1 00 id 1 w reset0000000000000000 1 these fields are writable only in initialization mode (lincr1[init] = 1). figure 24-37. identifier filter control registers (ifcr0?ifcr15) table 24-34. ifcr field descriptions field description dfl data field length this field defines the number of data bytes in the response part of the frame. dir direction this bit controls the direction of the data field. 0: linflexd receives the data and copy them in the bdrl and bdrm registers. 1: linflexd transmits the data fr om the bdrl and bdrm registers. ccs classic checksum this bit controls the type of checksum applied on the current message. 0: enhanced checksum covering identifier and data fiel ds. this is compatible with lin specification 2.0 and higher. 1: classic checksum covering data fields only. this is compatible with lin sp ecification 1.3 and below. id identifier identifier part of the identifier field without the identifier parity.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 515 offset: 0x8c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0000 000 tdfbm 1 rdfbm 1 tdlis 1 rdlis 1 stop 1 0 w sr 1 reset0000000000000000 1 this field is writable only in initialization mode (lincr1[init] = 1). figure 24-38. global control register (gcr) table 24-35. gcr field descriptions field description tdfbm transmit data first bit msb this field controls the first bit of transmitted da ta (payload only) as msb/lsb in both uart and lin modes. 0 the first bit of transmitted data is lsb ? that is , the first bit transmitted is mapped on the lsb bit (bdr(0), bdr(8), bdr(16), bdr(24)). 1 the first bit of transmitted data is msb ? that is, the first bit transmitted is mapped on the msb bit (bdr(7), bdr(15), bdr(23), bdr(31)). rdfbm received data first bit msb this field controls the first bit of received data (payload only) as msb/lsb in both uart and lin modes. 0 the first bit of received data is lsb ? that is, t he first bit received is mapped on the lsb bit (bdr(0), bdr(8), bdr(16), bdr(24)). 1 the first bit of received data is msb ? that is, the first bit received is mapped on the msb bit (bdr(7), bdr(15), bdr(23), bdr(31)). tdlis transmit data level inversion selection this field controls the data inversion of transmitt ed data (payload only) in both uart and lin modes. 0 transmitted data is not inverted. 1 transmitted data is inverted. rdlis received data level inversion selection this field controls the data inversion of receiv ed data (payload only) in both uart and lin modes. 0 received data is not inverted. 1 received data is inverted. stop stop bit configuration this field controls the number of stop bits in tr ansmitted data in both uart and lin modes. the stop bit is configured for all the fields (delimiter, sync, id, checksum, and payload). 0 one stop bit 1 two stop bits
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 516 freescale semiconductor 24.10.22 uart preset timeout register (uartpto) this register contains the preset timeout value in uart mode, and is used to monitor the idle state of the reception line. the timeout detection uses this register and the uartcto register described in section 24.10.23, uart current timeout register (uartcto) . 24.10.23 uart current timeout register (uartcto) this register contains the current timeout value in uart mode, and is used in conjunction with the uartpto register (see section 24.10.22, uart preset t imeout register (uartpto) ) to monitor the idle state of the reception line. uart ti meout works in both cpu and dma modes. the timeout counter: ? starts at 0 and counts upward ? is clocked with the baud rate clock presca led by a hard-wired sc aling factor of 16 ? is automatically enabled when uartcr[rxen] = 1 sr soft reset if the software writes a 1 to this field, the linflexd controller executes a soft reset in which the fsms, fifo pointers, counters, timers, status registers, and error registers are reset but the configuration registers are unaffected. this field always reads 0. offset: 0x90 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0 pto w reset0000111111111111 figure 24-39. uart preset timeout register (uartpto) table 24-36. uartpto field descriptions field description pto preset value of the timeout counter do not set pto = 0 (otherwise, uartsr[to] would immediately be set). table 24-35. gcr field descriptions (continued) field description
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 517 24.10.24 dma tx enable register (dmatxe) this register enables the dma tx interface. offset: 0x94 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000 0cto w reset0000000000000000 figure 24-40. uart current timeout register (uartcto) table 24-37. uartcto field descriptions field description cto current value of the timeout counter this field is reset whenever one of the following occurs: ? a new value is written to the uartpto register ? the value of this field matches the value of uartpto[pto] ? a hard or soft reset occurs ? new incoming data is received when cto matches the value of uartpto[pto], uartsr[to] is set. offset: 0x98 access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reset0000000000000000 figure 24-41. dma tx enable register (dmatxe)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 518 freescale semiconductor 24.10.25 dma rx enable register (dmarxe) this register enables the dma rx interface. 24.11 dma interface the linflexd dma interface offers a parametric and programmable solu tion with the following features: ? lin master node, tx mode: single dma channel ? lin master node, rx mode: single dma channel ? lin slave node, tx mode: 1 to n dma cha nnels where n = max num ber of id filters ? lin slave node, rx mode: 1 to n dma cha nnels where n = max number of id filters ? uart node, tx mode: single dma channel ? uart node, rx mode: single dma channel + timeout the linflexd controller interacts with an enhanced direct memory access (e dma) controller; see the description of that controller fo r details on its operati on and the transfer cont rol descriptors (tcds) referenced in this section. table 24-38. dmatxe field descriptions field description dte n dma tx channel n enable 0 dma tx channel n disabled 1 dma tx channel n enabled note: when dmatxe = 0x0, the dma tx interface fsm is forced (soft reset) into the idle state. offset: 0x9c access: user read/write 0123456789101112131415 r 0000 0000 0000 0000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reset0000000000000000 figure 24-42. dma rx enable register (dmarxe) table 24-39. dmarxe field descriptions field description dre n dma rx channel n enable 0 dma rx channel n disabled 1 dma rx channel n enabled note: when dmarxe = 0x0, the dma rx interface fsm is forced (soft reset) into the idle state.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 519 24.11.1 master node, tx mode on a master node in tx mode, the dma interface re quires a single tx channel. each tcd controls a single frame, except for the extended frames (multiple tcds). the memory map associated with the tcd chain (ram area and linflexd registers) is shown in figure 24-43 . figure 24-43. tcd chain memory map (master node, tx mode) the tcd chain of the dma tx channel on a master node supports: ? master to slave: transmission of the entire frame (header + data) ? slave to master: transmission of the header. the data reception is controlled by the rx channel on the master node. ? slave to slave: tran smission of the header. the register settings for the lincr2 and bidr re gisters for each class of lin frame are shown in table 24-40 . table 24-40. register settings (master node, tx mode) lin frame lincr2 bidr master to slave ddrq=1 dtrq=0 htrq=0 dfl = payload size id = address ccs = checksum dir = 1 (tx) lincr2 (4 bytes) bidr (4 bytes) bdrl + bdrm dma transfer (4/8 bytes) lincr2 (4 bytes) bidr (4 bytes) lincr2 (4 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) ram area tcd (n+2) tcd (n+3) linked chain lincr2 (4 bytes) bidr (4 bytes) bdrl + bdrm (4/8 bytes) lincr2 (4 bytes) bidr (4 bytes) lincr2 (4 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) linflex2 registers frame (n+1) slave ? master or slave ? slave extended frame (n+2) master ? slave extended frame (n+3) master ? slave frame (n) master ? slave 1 dma tx channel (tcd si ngle and/or linked chain) tcd (n+1) tcd (n)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 520 freescale semiconductor the concept fsm to control the dma tx interface is shown in figure 24-44 . the dma tx fsm will move to idle state immediately at next clock edge if dmatxe[0] = 0. slave to master ddrq=0 dtrq=0 htrq=0 dfl = payload size id = address ccs = checksum dir = 0 (rx) slave to slave ddrq=1 dtrq=0 htrq=0 dfl = payload size id = address ccs = checksum dir = 0 (rx) table 24-40. register settings (master node, tx mode) (continued) lin frame lincr2 bidr
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 521 figure 24-44. fsm to control the dma tx interface (master node) the tcd settings (word transfer) are shown in table 24-41 . all other tcd fields are equal to 0. tcd settings based on half-word or byte transfers are allowed. enables dma tx channel request (dmaerqh, dmaerql) !dtf & !drf & (lin idle | dbef) & dma_ten & !token_dma_rx ? true dma tx transfer (req/ack minor/major loop) from ram area to linflex registers dma tx transfer is completed ? true dbef ? false set htrq to transmit the lin frame (header + [data]) !dir & !ddrq ? false (tx mode) true (rx mode) clear dbef to transmit the lin frame (data for extended frame) true false false false false dtf ? dbef ? set token_dma_rx to enable the dma rx interface clear dtf true (end of frame) true (extended frame, size > 8 bytes)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 522 freescale semiconductor 24.11.2 master node, rx mode on a master node in rx mode, the dma interface re quires a single rx channel. each tcd controls a single frame, except for the extended frames (multipl e tcds). the memory map associated to the tcd chain (ram area and linflexd registers) is shown in figure 24-45 . figure 24-45. tcd chain memory map (master node, rx mode) the tcd chain of the dma rx cha nnel on a master node supports slave- to-master reception of the data field. table 24-41. tcd settings (master node, tx mode) tcd field value description citer[14:0] 1 single iteration for the major loop biter[14:0] 1 single iteration for the major loop nbytes[31:0] [4 + 4] + 0/4/8 = n data buffer is stuffed with dummy bytes if the length is not word aligned. lincr2 + bidr + bdrl + bdrm saddr[31:0] ram address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] lincr2 address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request bidr (4 bytes) bdrl + bdrm (4/8 bytes) dma transfer ram area tcd (n+2) linked chain bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) linflex2 registers extended frame (n+1) frame (n) slave ? master 1 dma rx channel (tcd single and/or linked chain) tcd (n+1) tcd (n) extended frame (n+2) bidr (4 bytes) bdrl + bdrm (4/8 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 523 the bidr register is optionally copi ed into the ram area. this bidr fi eld (part of fifo data) contains the id of each message to allow the cpu to figure out which id was received by the linflexd dma if only the ?one dma channel? setup is used. the concept fsm to control the dma rx interface is shown in figure 24-46 . the dma rx fsm will move to idle state immediately at next clock edge if dmarxe[0]=0. figure 24-46. fsm to control the dma rx interface (master node) the tcd settings (word transfer) are shown in table 24-42 . all other tcd fields are equal to 0. tcd settings based on half-word or byte transfer are allowed. enables dma rx channel request (dmaerqh, dmaerql) (drf | (dbff & rmb)) & token_dma_rx & dma_ren ? true dma rx transfer (req/ack minor/major loop) from linflex registers to ram area dma rx transfer done ? true false false false false drf ? dbff & rmb ? clear token_dma_rx true true (extended frame, clear drf clear dbff, rmb (for extended frame) size > 8 bytes)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 524 freescale semiconductor 24.11.3 slave node, tx mode on a slave node in tx mode, the dma interface requires a dma tx channel for each id filter programmed in tx mode. in case a si ngle dma tx channel is available, a single id field filter must be programmed in tx mode. each tcd controls a single frame, except for the extended frames (multiple tcds). the memory map associated to the tcd chai n (ram area and linflexd registers) is shown in figure 24-47 . figure 24-47. tcd chain memory map (slave node, tx mode) table 24-42. tcd settings (master node, rx mode) tcd field value description citer[14:0] 1 single iteration for the major loop biter[14:0] 1 single iteration for the major loop nbytes[31:0] [4] + 4/8 = n data buffer is stuff ed with dummy bytes if the length is not word aligned. bidr + bdrl + bdrm saddr[31:0] bidr address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] ram address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request dma transfer ram area tcd (n+2) linked chain linflex2 registers extended frame (n+1) frame (n) slave ? master 1 dma tx channel/filter (tcd single and/or linked chain) tcd (n+1) tcd (n) extended frame (n+2) bdrl + bdrm (4/8 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) slave ? slave bdrl + bdrm (4/8 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 525 the tcd chain of the dma tx channel on a slave node supports: ? slave to master: transmission of the data field ? slave to slave: transm ission of the data field the register settings of the lincr2, ifer , ifmr, and ifcr registers are shown in table 24-43 . the concept fsm to control the dma tx interface is shown in figure 24-48 . dma tx fsm will move to idle state if dmatxe[ x ] = 0, where x =ifmi?1. table 24-43. register settings (slave node, tx mode) lin frame lincr2 ifer ifmr ifcr slave to master or slave to slave ddrq = 0 dtrq = 0 htrq = 0 to enable an id filter (tx mode) for each dma tx channel identifier list mode identifier mask mode dfl = payload size id = address ccs = checksum dir = 1(tx)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 526 freescale semiconductor figure 24-48. fsm to control the dma tx interface (slave node) the tcd settings (word transfer) are shown in table 24-44 . all other tcd fields are equal to 0. tcd settings based on half-word or byte transfer are allowed. enables dma tx channel/filter request (dmaerqh, dmaerql) !dtf & !drf & (dbef | hrf) & (ifmi != 0) & dma_ten ? true dma tx transfer (req/ack) from ram area to linflex registers (channel/filter mapping) dma tx transfer done ? true dbef ? false set dtrq to transmit the lin frame (data) clear dbef to transmit the lin frame (data for extended frame) true false false false false dtf ? dbef ? clear dtf true true (extended frame, size > 8 bytes)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 527 24.11.4 slave node, rx mode on a slave node in rx mode, th e dma interface requires a dma rx channel for each id filter programmed in rx mode. in case a single dma rx channe l is available, a single id field filter must be programmed in rx mode. each tcd controls a single frame, except for the extended frames (multiple tcds). the memory map associated to the tcd chai n (ram area and linflexd registers) is shown in figure 24-49 . figure 24-49. tcd chain memory map (slave node, rx mode) table 24-44. tcd settings (slave node, tx mode) tcd field value description citer[14:0] 1 single iteration for the major loop biter[14:0] 1 single iteration for the major loop nbytes[31:0] 4/8 = n data buffer is stuffed with dummy bytes if the length is not word aligned. bdrl + bdrm saddr[31:0] ram address soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] bdrl address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no sca tter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request bidr (4 bytes) bdrl + bdrm (4/8 bytes) dma transfer ram area tcd (n+2) linked chain bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) linflex2 registers extended frame (n+1) frame (n) master ? slave 1 dma rx channel/filter (tcd single and/or linked chain) tcd (n+1) tcd (n) extended frame (n+2) bidr (4 bytes) bdrl + bdrm (4/8 bytes) bidr (4 bytes) bdrl + bdrm (8 bytes) bdrl + bdrm (4/8 bytes) slave ? slave
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 528 freescale semiconductor the tcd chain of the dma rx channel on a slave node supports: ? master to slave: recep tion of the data field. ? slave to slave: recep tion of the data field. the register setting of the lincr2, ifer , ifmr, and ifcr registers are given in table 24-45 . the concept fsm to control the dma rx interface is shown in figure 24-50 . dma rx fsm will move to idle state if dmarxe[ x ]=0 where x =ifmi?1. table 24-45. register settings (slave node, rx mode) lin frame lincr2 ifer ifmr ifcr master to slave or slave to slave ddrq = 0 dtrq = 0 htrq = 0 to enable an id filter (rx mode) for each dma rx channel identifier list mode identifier mask mode dfl = payload size id = address ccs = checksum dir = 0 (rx)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 529 figure 24-50. fsm to control the dma rx interface (slave node) the tcd settings (word transfer) are shown in table 24-46 . all other tcd fields = 0. tcd settings based on half-word or byte transfer are allowed. table 24-46. tcd settings (slave node, rx mode) tcd field value description citer[14:0] 1 single iterat ion for the major loop biter[14:0] 1 single iteration for the major loop nbytes[31:0] [4] + 4/8 = n data buffer is stuffed with dummy bytes if the length is not word aligned. bidr + bdrl + bdrm saddr[31:0] bdrl address enables dma rx channel/filter request (dmaerqh, dmaerql) !dtf & (drf | (dbff & rmb)) & (ifmi != 0) & dma_ren ? true dma rx transfer (req/ack) from linflex registers to ram area (channel/filter mapping) dma rx transfer done ? true false false false false drf ? dbff & rmb ? true true (extended frame, clear drf clear dbff, rmb (for extended frame) size > 8 bytes)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 530 freescale semiconductor 24.11.5 uart node, tx mode in uart tx mode, the dma inte rface requires a dma tx channel. a single tcd can control the transmission of an entire tx buffer. the memory map associated with the tcd chain (ram area and linflexd registers) is shown in figure 24-51 . figure 24-51. tcd chain memory map (uart node, tx mode) the uart tx buffer must be configur ed in fifo mode in order to: ? allow the transfer of large data buffer by a single tcd ? adsorb the latency, following a dma request (due to the dma arbitration), to move data from the ram to the fifo ? use low priority dma channels ? support the uart baud rate (2 mb/s) without underrun events the tx fifo size is: soff[15:0] 4 word increment ssize[2:0] 2 word transfer slast[31:0] ?n daddr[31:0] ram address doff[15:0] 4 word increment dsize[2:0] 2 word transfer dlast_sga[31:0] ?n no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request table 24-46. tcd settings (slave node, rx mode) (continued) tcd field value description bdrl (m half-words) bdrl (2 half-words fifo mode) bdrl (m half-words) bdrl (2 half-words fifo mode) bdrl (m bytes) bdrl (m bytes) dma transfer (8/16-bit data format) ram area linflex2 registers 1 dma tx channel (tcd single and/or linked chain) tcd (n+1) tcd (n) buffer (n+1) bdrl (4 bytes fifo mode) bdrl (4 bytes fifo mode) buffer (n)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 531 ? 4 bytes in 8-bit data format ? 2 half-words in 16-bit data format a dma request is triggered by fifo not full (tx) status signals. the concept fsm to control the dma tx interface is shown in figure 24-52 . dma tx fsm will move to idle state if dmatxe[0] = 0. figure 24-52. fsm to control the dma tx interface (uart node) the tcd settings (typica l case) are shown in table 24-47 . all other tcd fields = 0. the minor loop transfers a single byte/half-word as soon a free entry is available in the tx fifo. !tff & dma_ten ? true false false !tff ? uart tx buffer (fifo mode) set txen enables dma tx channel request (dmaerqh, dmaerql) dma tx transfer (req/ack) from ram area to uart tx fifo dma tx (major loop) done ? true false dma tx (minor loop) done ? true false true
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 532 freescale semiconductor 24.11.6 uart node, rx mode in uart rx mode, the dma inte rface requires a dma rx channel. a single tcd can control the reception of an entire rx buffer. the memory map associated with the tcd chain (ram area and linflexd registers) is shown in figure 24-53 . figure 24-53. tcd chain memory map (uart node, rx mode) table 24-47. tcd settings (uart node, tx mode) tcd field value description 8-bit data 16-bit data citer[14:0] m multiple iterations for the major loop biter[14:0] m multiple iterations for the major loop nbytes[31:0] 1 2 minor loop transfer = 1 or 2 bytes saddr[31:0] ram address soff[15:0] 1 2 byte/hal f-word increment ssize[2:0] 0 1 byte/half-word transfer slast[31:0] ?m ?m 2 daddr[31:0] bdrl address daddr = bdrl + 0x3 for byte transfer daddr = bdrl + 0x2 for half-word transfer doff[15:0] 0 no increment (fifo) dsize[2:0] 0 1 byte/half-word transfer dlast_sga[31:0] 0 no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request buffer (n+1) buffer (n) dma transfer (8/16-bit data format) ram area linflex2 registers 1 dma rx channel (tcd single and/or linked chain) bdrm (4 bytes fifo mode) bdrm (2 half-words fifo mode) bdrm (4 bytes fifo mode) bdrm (2 half-words fifo mode) tcd (n+1) tcd (n) bdrm (m bytes) bdrm (m half-words) bdrm (m bytes) bdrm (m half-words)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 533 the uart rx buffer must be configur ed in fifo mode in order to: ? allow the transfer of large data buffer by a single tcd ? adsorb the latency, following a dma request (due to the dma arbitration), to move data from the fifo to the ram ? use low priority dma channels ? support high uart baud rate (at l east 2 mb/s) without overrun events the rx fifo size is: ? 4 bytes in 8-bit data format ? 2 half-words in 16-bit data format this is sufficient because just one byte allows a reaction time of about 3.8 ? s (at 2 mbit/s), corresponding to about 450 clock cycles at 120 mhz, before the tran smission is affected. a dm a request is triggered by fifo not empty (rx) status signals. the concept fsm to control the dma rx interface is shown in figure 24-54 . dma rx fsm will move to idle state if dmarxe[0] = 0.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 534 freescale semiconductor figure 24-54. fsm to control the dma rx interface (uart node) the tcd settings (typica l case) are shown in table 24-48 . all other tcd fields = 0. the minor loop transfers a single byte/half-w ord as soon an entry is av ailable in the rx fifo. a new software reset bit is !rfe & dma_ren ? true false !rfe ? uart rx buffer (fifo mode) timeout config enables dma rx channel request (dmaerqh, dmaerql) dma rx transfer (req/ack) from uart rx fifo to ram area dma rx (major loop) done ? true false dma rx (minor loop) done ? true false true set rxen timeout restart false false timeout ? true set timeout flag
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 535 required that allows the linflexd fsms to be reset in case this timeout state is reached or in any other case. timeout counter can be rewritten by so ftware at any time to extend timeout period. 24.11.7 use cases and limitations ? in lin slave mode, the dma capability can be used only if the id filtering mode is activated. the number of id filters enabled must be equal to the number of dma channels enabled. the correspondence between channel # an d id filter is based on ifmi (i dentifier filter match index). ? in lin master mode, both the dma channels (t x and rx) must be enabled in case the dma capability is required. ? in uart mode, the dma capability can be used only if the uart tx/rx buffers are configured as fifos. ? dma and cpu operating modes are mutually exclusive for the data/frame transfer on a uart or lin node. once a dma transfer is finishe d, the cpu can handle subsequent accesses. ? error management must be alwa ys executed via cpu enabling the related error interrupt sources. the dma capability does not provi de support for the error manage ment. error management means checking status bits, handling irqs, a nd potentially canceling dma transfers. ? the dma programming model must be coherent wi th the tcd setting defined in this document. table 24-48. tcd settings (uart node, rx mode) tcd field value description 8 bits data 16 bits data citer[14:0] m multiple iterations for the major loop biter[14:0] m multiple iterations for the major loop nbytes[31:0] 1 2 minor loop transfer = 1 or 2 bytes saddr[31:0] bdrm address saddr = bdrm + 0x3 for byte transfer saddr = bdrm + 0x2 for half-word transfer soff[15:0] 0 no in crement (fifo) ssize[2:0] 0 1 byte/half-word transfer slast[31:0] 0 daddr[31:0] ram address doff[15:0] 1 2 byte/half-word increment dsize[2:0] 0 1 byte/half-word transfer dlast_sga[31:0] ?m ?m 2 no scatter/gather processing int_maj 0/1 interrupt disabled/enabled d_req 1 only on the last tcd of the chain. start 0 no software request
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 536 freescale semiconductor 24.12 functional description 24.12.1 8-bit timeout counter 24.12.1.1 lin timeout mode clearing the ltom bit (setting its value to 0) in the lintcsr enables the lin timeout mode. the linocr becomes read-only, and oc 1 and oc2 output compare values in the linocr are automatically updated by hardware. this configuration detects header time out, response timeout, and frame timeout. depending on the lin mode (selected by the mme bit in lincr1), the 8-bit time out counter will behave differently. lin timeout mode must not be enab led during lin extended fr ames transmission or reception (that is, if the data field length in the bidr is configur ed with a value higher than 8 data bytes). 24.12.1.1.1 lin master mode field rto in the lintocr can be used to tune response timeout and frame timeout values. header timeout value is fixed to hto = 28-bit time. field oc1 checks theader and tresponse and field oc2 checks tframe (refer to figure 24-55 (header and response timeout) ). when linflexd moves from break delimiter st ate to synch field state (refer to section 24.10.3, lin status register (linsr) ): ? oc1 is updated with the value of ocheader (ocheader = cnt + 28), ? oc2 is updated with the value of ocframe (o cframe = cnt + 28 + rto 9 (frame timeout value for an 8-byte frame) ? the toce bit is set. on the start bit of the fi rst response data byte (and if no error occurred during th e header reception), oc1 is updated with the valu e of ocresponse (ocresponse = cnt + rto 9 (respons e timeout value for an 8-byte frame)). on the first response byte is received, oc1 and oc 2 are automatically updated to check tresponse and tframe according to rt o (tolerance) and dfl. on the checksum reception or in case of error in the header or response, the toce bit is reset. if there is no response, frame timeout value does not take into account the dfl value, and an 8-byte response (dfl = 7) is always assumed. 24.12.1.1.2 lin slave mode field rto in the lintocr can be used to tune response timeout and frame timeout values. header timeout value is fixed to hto.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 537 oc1 checks theader and tresponse a nd oc2 checks tframe (refer to figure 24-55 (header and response timeout) ). when linflexd moves from break stat e to break delimiter state (refer to section 24.10.3, lin status register (linsr) ): ? oc1 is updated with the value of ocheader (ocheader = cnt + hto), ? oc2 is updated with the value of ocframe (ocframe = cnt + hto + rto 9 (frame timeout value for an 8-byte frame)), ? the toce bit is set. on the start bit of the fi rst response data byte (and if no error occurred during th e header reception), oc1 is updated with the valu e of ocresponse (ocresponse = cnt + rto 9 (respons e timeout value for an 8-byte frame)). once the first response byte is received, oc1 and oc 2 are automatically update d to check tresponse and tframe according to rt o (tolerance) and dfl. on the checksum reception or in case of error in the header or data field, the toce bit is reset. figure 24-55. header and response timeout 24.12.1.2 output compare mode setting lintcsr[ltom] = 1 enables the output compar e mode. this mode allows the user to fully customize the use of the counter. oc1 and oc2 output compare values can be updated in the lintocr by software. 24.12.2 interrupts table 24-49. linflexd interrupt control interrupt event event flag bit enable control bit interrupt vector header received interrupt hrf hrie rxi 1 data transmitted interrupt dtf dtie txi oc frame oc header oc response header response break frame oc1 oc2 response space
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 538 freescale semiconductor data received interrupt drf drie rxi data buffer empty interrupt dbef dbeie txi data buffer full interrupt dbff dbfie rxi wake-up interrupt wupf wupie rxi lin state interrupt 2 lsf lsie rxi buffer overrun interrupt bof boie err framing error interrupt fef feie err header error interrupt hef heie err checksum error interrupt cef ceie err bit error interrupt bef beie err output compare interrupt ocf ocie err stuck at zero interrupt szf szie err 1 in slave mode, if at least one filter is configured as tx and enabled, header received interrupt vector is rxi or txi depending on the value of identifier received. 2 for debug and validation purposes. table 24-49. linflexd interrupt control (continued) interrupt event event flag bit enable control bit interrupt vector
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 539 figure 24-56. interrupt diagram 24.12.3 fractional baud rate generation the baud rates for the receiver and transmitter are both set to the sa me value as programmed in the mantissa (linibrr) and fr action (linfbrr) registers . lfdiv is an unsigned fixed point number. the 20-bit ma ntissa is coded in the linibrr register and the fraction is coded in the linfbrr register. the following examples show how to derive lf div from linibrr and li nfbrr register values: lsie states wuie wuf dbff drf hrie tx dtie dtf hrie hrf rx dbfie drie boie bof feie fef cef beie bef ceie hrf heie sfef,sdef,idpef ocie ocf szie szf error dbeie dbef toie to tx/rx baud = f ipg_clock_lin (16 lfdiv)
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 540 freescale semiconductor example 24-1. if linibrr = 27d and linfbrr = 12d, then mantissa (lfdiv) = 27d fraction (lfdiv) = 12/16 = 0.75d therefore lfdiv = 27.75d example 24-2. to program lfdiv = 25.62d, linfbrr = 16 0.62 = 9.92, nearest real number 10d = ah linibrr = mantissa(25.620d) = 25d = 19h note the baud counters are updated with the new value of the baud registers after a write to linibrr. hence the baud register value must not be changed during a transact ion. the linfbrr (contai ning the fraction bits) must be programmed before linibrr. note lfdiv must be greater than or equal to 1.5d, for example, linibrr = 1 and linfbrr = 8. therefore, the maximum possible baud rate is fperiph_set_1_clk / 24. 24.13 programming considerations this section describes the various configurat ions in which the linflexd can be used. 24.13.1 master node figure 24-57. programming consideration: master node, transmitter header data tx checksum tx configure id dfl, data buffer set htrq txi interrupt dtf set dir = 1
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 541 figure 24-58. programming consideration: master node, receiver figure 24-59. programming consideration: master node, transmitter, bit error figure 24-60. programming consideration: master node, receiver, checksum error 24.13.2 slave node figure 24-61. programming consideration: slave node, transmitter, no filters header data rx checksum rx configure id, dfl set htrq rxi interrupt drf set dir = 0 and ddrq = 0 header data tx configure id dfl, data buffer set htrq dir = 1 bef set erri interrupt iobe = 1 header data tx checksum tx configure id dfl, data buffer set htrq tx interrupt dtf set dir = 1 bef set err interrupt iobe = 0 header data rx checksum rx configure id, dfl set htrq err interrupt cef set dir = 0 and ddrq = 0 header data tx checksum tx tx interrupt dtf set hrf set rx interrupt set dtrq configure ccs, dir, dfl, data buffers
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 542 freescale semiconductor figure 24-62. programming consideration: slave node, receiver, no filters figure 24-63. programming consideration: slave node, transmitter, no filters, bit error figure 24-64. programming consideration: slave node, receiver, no filters, checksum error figure 24-65. programming consideration: slave node, at le ast one tx filter, bf is reset, id matches filter header data rx checksum rx rx interrupt drf set configure ccs, dir, dfl hrf set rx interrupt ddrq = 0 header ddrq = 1 hrf set rx interrupt header data tx err interrupt bef set hrf set rx interrupt set dtrq configure dir, dfl, data buffers iobe = 1 header data rx checksum rx err interrupt cef set ddrq = 0 configure dir, dfl hrf set rx interrupt header data tx checksum tx tx interrupt dtf set set dtrq write data buffers hrf set tx interrupt (id matched) note: this configuration can be used in case the slave never receives data (for example, as with a sensor).
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 543 figure 24-66. programming consideration: slave node, at least one rx filter, bf is reset, id matches filter figure 24-67. programming consideration: slave node, rx only, tx only, rx and tx filters, id not matching filter, bf is reset figure 24-68. programming consideration: slave node, tx filter, bf is set header data rx checksum rx rxi interrupt drf set ifmi = id matched+1 header id not matching any filter header data tx checksum tx tx interrupt dtf set set dtrq write data buffers hrf set tx interrupt (id has matched) header data rx checksum rx rx interrupt drf set ddrq = 0 configure ccs, dir, dfl hrf set rx interrupt (id not matched) note: this configuration is used when: a) all tx ids are managed by filters b) the number of other filters is not enough to manage all reception ids
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 544 freescale semiconductor figure 24-69. programming consideration: slave node, rx filter, bf is set figure 24-70. programming consideration: slave node, tx filter, rx filter, bf is set header data receive checksum receive receive interrupt drf set ifmi = id matched header data receive checksum receive receive interrupt drf set hrf set receive interrupt (id not matched) configure ccs, dir, dfl (id is receive) ddrq = 0 header data transmit checksum transmit transmit interrupt dtf set hrf set receive interrupt set dtrq configure ccs, dir, dfl, data buffers (id is transmit) header data transmit checksum transmit transmit interrupt dtf set set dtrq write data buffers hrf set transmit interrupt (ifmi = id matched+1) header data receive checksum receive rxi interrupt drf set ifmi = id matched+1 header data receive/transmit checksum receive/transmit receive/transmit interrupt drf/dtf set ddrq = 0 configure ccs, dir, dfl hrf set receive interrupt (id not matched) note: this configuration is used when: a) the number of filters is not enough b) filters are used for most frequently used ids to reduce cpu usage
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 545 24.13.3 extended frames figure 24-71. programming consideration: extended frames 24.13.4 timeout figure 24-72. programming consideration: response timeout figure 24-73. programming consideration: frame timeout figure 24-74. programming consideration: header timeout header 8 bytes transmit 8 bytes transmit checksum transmit transmit interrupt dtf set configure dir, dfl, hrf set receive interrupt (id not matched) dbef set refill buffer reset dbef ccs dtrq =1 header 8 bytes receive 8 bytes receive checksum receive receive interrupt drf set configure dir, dfl, hrf set receive interrupt (id not matched) rmb, dbff read buffer reset rmb set ddrq = 0 ccs header receive/transmit data receive oc1 t response_max ocf is set err interrupt header transmit/receive data receive/transmit oc2 t frame_max ocf is set err interrupt header receive oc1 t header_max ocf is set err interrupt break
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 546 freescale semiconductor 24.13.5 uart mode figure 24-75. programming consideration: uart mode data receive/transmit dtf/drf is set transmit/receive interrupt set txen/rxen write buffer for transmit
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 547 this page is intent ionally left blank.
chapter 24 lin controller (linflexd) MPC5606BK microcontroller reference manual, rev. 2 548 freescale semiconductor
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 547 chapter 25 flexcan 25.1 information specific to this device this section presents device-speci fic parameterization and customizat ion information not specifically referenced in the remainder of this chapter. 25.1.1 device-specific features the device has six controller area network (flexcan) blocks. ? each block supports 64 message buffers (mb). ? dma support is not provided. ? it is possible to operate the fl excan bit timing logic with either system clock or 4?40 mhz fast external crystal osci llator clock (fxosc). ? in the case of safe mode entry, the pad asso ciated with cantx can opt ionally be put into a high-impedance state (not recessive state) ? modes of operation: ? four functional modes: normal (user and supe rvisor), freeze, list en-only, and loop-back ? one low-power mode (disable mode) ? 1056 bytes (64 mbs) of ram used for mb storage ? 256 bytes (64 mbs) of ram used for individual rx mask registers ? hardware cancellation on tx message buffers ? module configuration register (mcr) : bits 5, 9, 12, and 13 are reserved ? error and status register (esr): bit 31 is reserved 25.2 introduction the flexcan module is a communication controller implementing the can protocol according to the can 2.0b protocol specification. a ge neral block diagram is shown in figure 25-1 , which describes the main sub-blocks implemented in the flexcan module, including two embedded memories, one for storing message buffers (mb) and another one for st oring rx individual mask registers. support for as many as 64 message buffers is provi ded. the functions of the sub-modul es are described in subsequent sections.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 548 freescale semiconductor figure 25-1. flexcan block diagram 25.2.1 overview the can protocol was primarily, but not only, designed to be used as a vehicle serial data bus, meeting the specific requirements of this fi eld: real-time processing, reliable operation in the emi environment of a vehicle, cost-effectiveness, a nd required bandwidth. the flexcan m odule is a full implementation of the can protocol specification, version 2.0 b, wh ich supports both standard and extended message frames. a flexible number of messa ge buffers (16, 32 or 64) is also supported. the message buffers are stored in an embedded ram dedi cated to the flexcan module. the can protocol interface (cpi) submodule ma nages the serial communication on the can bus, requesting ram access for receiving a nd transmitting message frames, va lidating received messages, and performing error handling. the message buffer management (mbm ) submodule handles message buffer selection for reception and trans mission, taking care of arbitration a nd id matching algorithms. the bus interface unit (biu) subm odule controls the access to and from the internal interface bus in order to 288/544/1056- bus interface unit max mb # (0?31) ip bus interface can message can tx can rx mb1 mb0 mb30 mb31 clocks, address & data buses, interrupt and test signals buffer management protocol interface byte ram message buffer storage 64/128/256- rximr1 rximr0 rximr62 rximr63 byte ram id mask storage
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 549 establish connection to the cpu and to other blocks. cl ocks, address and data bus es, interrupt outputs, and test signals are accessed through the bus interface unit. 25.2.2 flexcan module features the flexcan module includes these distinctive features: ? full implementation of the can pr otocol specification, version 2.0b ? standard data and remote frames ? extended data and remote frames ? 0 to 8 bytes data length ? programmable bit rate as fast as 1 mbit/s ? content-related addressing ? flexible message buffers (as many as 64) of 0 to 8 bytes data length ? each mb configurable as rx or tx, al l supporting standard and extended messages ? individual rx mask register s per message buffer (mb) ? includes either 1056 bytes (64 mbs), 544 bytes (32 mbs), or 288 bytes (16 mbs) of ram used for mb storage ? includes either 256 bytes (64 mb s), 128 bytes (32 mbs), or 64 byt es (16 mbs) of ram used for individual rx mask registers ? full featured rx fifo with storage capacity for 6 frames and internal pointer handling ? powerful rx fifo id filtering, capable of ma tching incoming ids against either 8 extended, 16 standard, or 32 partial (8 bits) id s, with individual masking capability ? selectable backwards compatibilit y with previous flexcan version ? programmable clock source to th e can protocol interface, either bus clock or crystal oscillator ? unused mb and rx mask register space can be used as general purpose ram space ? listen only mode capability ? programmable loopback mode supporting self-test operation ? programmable transmission priority scheme: lowest id, lowest buffer number or highest priority ? time stamp based on 16-bit free-running timer ? global network time, synchr onized by a specific message ? maskable interrupts ? independent of the transm ission medium (an external transceiver is assumed) ? short latency time due to an arbitration scheme for high-priority messages ? low power modes, with progra mmable wake up on bus activity 25.2.3 modes of operation the flexcan module has four functi onal modes: normal mode (user and supervisor), freeze mode, listen-only mode, and loop-back mode. there is also a low-power mode (disable mode).
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 550 freescale semiconductor ? normal mode (user or supervisor): in normal mode, the module operates receiving a nd/or transmitting message frames, errors are handled normally and all the can protocol functions are enable d. user and supervisor modes differ in the access to some restricted control registers. ? freeze mode: it is enabled when the frz bit in mcr is assert ed. if enabled, freeze mode is entered when the halt bit in mcr is set or when debug mode is requested at mcu level. in this mode, no transmission or reception of fr ames is done and synchronicity to the can bus is lost. see section 25.5.10.1, freeze mode , for more information. ? listen-only mode: the module enters this mode when the lom bit in ctrl is asserted. in th is mode, transmission is disabled, all error counters are frozen and the m odule operates in a can error passive mode. only messages acknowledged by another c an station will be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (without changing the rec), as if it was trying to acknowledge the message. ? loop-back mode: the module enters this mode when the lpb bit in ctrl is asserted. in this mode, flexcan performs an internal loop back th at can be used for self test ope ration. the bit stream output of the transmitter is internally fed back to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic 1). flexcan behaves as it normally does when transmitting and treats its own tran smitted message as a message rece ived from a remote node. in this mode, flexcan ignores the bi t sent during the ack slot in the can frame acknowledge field to ensure proper reception of its own message. bo th transmit and receive interrupts are generated. ? module disable mode: this low power mode is entered when the mcr[md is] bit is asserted by th e cpu. when disabled, the module requests to disable the clocks to the can protocol interface and message buffer management submodules. exit from this mode is done by negating the mdis bit in mcr. see section 25.5.10.2, module disable mode , for more information. 25.3 external signal description 25.3.1 overview the flexcan module has two i/o si gnals connected to the external mcu pins. these signals are summarized in table 25-1 and described in more detail in the next subsections. table 25-1. flexcan signals signal name 1 1 the actual mcu pins may have different names. direction description can rx input can receive pin can tx output can transmit pin
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 551 25.3.2 signal descriptions 25.3.2.1 can rx this pin is the receive pin from th e can bus transceiver. dominant st ate is represented by logic level 0. recessive state is represented by logic level 1. 25.3.2.2 can tx this pin is the transmit pin to th e can bus transceiver. dominant st ate is represented by logic level 0. recessive state is represented by logic level 1. 25.4 memory map/register definition this section describes the registers and data structures in the flexca n module. the base address of the module depends on the particul ar memory map of the mcu. the addres ses presented here are relative to the base address. the address space occupied by flexcan has 96 bytes fo r registers starting at the module base address, followed by mb storage space in embedded ram st arting at address 0x0060, and an extra id mask storage space in a separate em bedded ram starting at address 0x0880. 25.4.1 flexcan memory mapping the complete memory map for a flexcan mo dule with 64 mbs capability is shown in table 25-2 . all registers except for the mcr can be configured to have either s upervisor or unrestricted access by programming the mcr[supv] bit. the iflag2 and imask2 registers ar e considered reserved space when flexcan is configured with 16 or 32 mbs. the rx globa l mask (rxgmask), rx buffer 14 mask (rx14mask), and the rx buffer 15 mask (rx15mask) registers are provided for backwa rds compatibility and are not used when the bcc bit in mcr is asserted. the address ranges 0x0060?0x047f a nd 0x0880?0x097f are occupied by two separate embedded memories. these two ranges are completely occ upied by ram (1056 and 256 bytes, respectively) only when flexcan is configured with 64 mbs. when it is c onfigured with 16 mbs, the memory sizes are 288 and 64 bytes, so the address ranges 0x0180?0x047f and 0x08c0?0x097f are c onsidered reserved space. when it is configured with 32 mbs, the memory sizes are 544 a nd 128 bytes, so the address ranges 0x0280?0x047f and 0x0900?0x097f are considered reserved sp ace. furthermore, if the bcc bit in mcr is negated, then the whole rx individual mask registers address range (0x0880?0x097f) is considered reserved space.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 552 freescale semiconductor the flexcan module stores can messages for tran smission and reception us ing a message buffer structure. each individual mb is formed by 16 bytes mapped on memory as described in table 25-3 . table 25-3 shows a standard/extended message buffer (mb0) memory map, using 16 bytes total (0x80 ? 0x8f space). table 25-2. flexcan memory map base addresses: 0xfffc_0000 (flexcan_0) 0xfffc_4000 (flexcan_1) 0xfffc_8000 (flexcan_2) 0xfffc_c000 (flexcan_3) 0xfffd_0000 (flexcan_4) 0xfffd_4000 (flexcan_5) address offset register location 0x0000 module configuration (mcr) on page 557 0x0004 control register (ctrl) on page 561 0x0008 free running timer (timer) on page 564 0x000c reserved 0x0010 rx global mask (rxgmask) on page 565 0x0014 rx buffer 14 mask (rx14mask) on page 567 0x0018 rx buffer 15 mask (rx15mask) on page 567 0x001c error counter register (ecr) on page 567 0x0020 error and status register (esr) on page 569 0x0024 interrupt masks 2 (imask2) on page 572 0x0028 interrupt masks 1 (imask1) on page 573 0x002c interrupt flags 2 (iflag2) on page 573 0x0030 interrupt flags 1 (iflag1) on page 574 0x0034?0x007f reserved 0x0080?0x017f message buffers mb0?mb15 ? 0x0180?0x027f message buffers mb16?mb31 ? 0x0280?0x047f message buffers mb32?mb63 ? 0x0480?087f reserved 0x0880?0x08bc rx individual mask registers rximr0?rximr15 on page 575 0x08c0?0x08fc rx individual mask registers rximr16?rximr31 on page 575 0x0900?0x097c rx individual mask registers rximr32?rximr63 on page 575 table 25-3. message buffer mb0 memory mapping address offset mb field 0x80 control and status (c/s)
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 553 25.4.2 message buffer structure the message buffer structure used by the flexcan module is represented in figure 25-2 . both extended and standard frames (29-bit identifier and 11-bit identifier, re spectively) used in the can specification (version 2.0 part b) are represented. 0x84 identifier field 0x88?0x8f data field 0 ? data field 7 (1 byte each) 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 0x0 code srr ide rtr length time stamp 0x4 prio id (standard/extended) id (extended) 0x8 data byte 0 data byte 1 data byte 2 data byte 3 0xc data byte 4 data byte 5 data byte 6 data byte 7 = unimplemented or reserved figure 25-2. message buffer structure table 25-4. message buffer structure field description field description code message buffer code this 4-bit field can be accessed (read or write) by the cpu and by the flexcan module itself, as part of the message buffer matching and arbitrat ion process. the encoding is shown in table 25-5 and table 25-6 . see section 25.5, functional description , for additional information. srr substitute re mote request fixed recessive bit, used only in extended format. it must be set to 1 by the user for transmission (tx buffers) and will be stored with the value received on the can bus for rx receiving buffers. it can be received as either recessive or dominant. if flexcan receives this bit as dominant, then it is interpreted as arbitration loss. 0 dominant is not a valid value for transmission in extended format frames. 1 recessive value is compulsory for transmission in extended format frames. ide id extended bit this bit identifies whether the fram e format is standard or extended. 0 frame format is standard. 1 frame format is extended. rtr remote transmission request this bit is used for requesting transmissions of a data frame. if flexcan transmits this bit as 1 (recessive) and receives it as 0 (dominant), it is inte rpreted as arbitration loss. if this bit is transmitted as 0 (dominant), then if it is received as 1 (recessive ), the flexcan module treats it as bit error. if the value received matches the value transmitted, it is considered as a successful bit transmission. 0 indicates the current mb has a data frame to be transmitted. 1 indicates the current mb has a remote frame to be transmitted. note: do not configure the last message buffer to be the rtr frame. table 25-3. message buffer mb0 memory mapping
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 554 freescale semiconductor length length of data in bytes this 4-bit field is the length (in bytes) of the rx or tx data, which is located in offset 0x8 through 0xf of the mb space (see figure 25-2 ). in reception, this field is written by the flexcan module, copied from the dlc (data length code) field of the receiv ed frame. in transmission, this field is written by the cpu and corresponds to the dlc field value of the frame to be transmitted. when rtr=1, the frame to be transmitted is a remote frame and does not include the data field, regardless of the length field. time stamp free-running counter time stamp this 16-bit field is a copy of the free-running timer, captured for tx and rx frames at the time when the beginning of the identifier field appears on the can bus. prio local priority this 3-bit field is only used when lprio_en bit is set in mcr and it only makes sense for tx buffers. these bits are not transmitted. they are appended to the regular id to define the transmission priority. see section 25.5.4, arbitration process. id frame identifier in standard frame format, only the 11 most significant bits (3 to 13) are used for frame identification in both receive and transmit cases. the 18 least significant bits are ignored. in extended frame format, all bits are used for frame identification in both receive and transmit cases. data data field as many as 8 bytes can be used for a data frame. for rx frames, the data is stored as it is received from the can bus. for tx frames, the cpu prepares the data field to be transmitted within the frame. table 25-5. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment 0000 inactive: mb is not active. ? mb does not participate in the matching process. 0100 empty: mb is active and empty. 0010 mb participates in the matching process. when a frame is received successfully, the code is automatically updated to full. 0010 full: mb is full. 0010 the act of reading the c/s word followed by unlocking the mb does not make the code return to empty. it remains full. if a new frame is written to the mb after the c/s word was read and the mb was unlocked, the code still remains full. 0110 if the mb is full and a new frame is overwritten to this mb before the cpu had time to read it, the code is automatically updated to overrun. see section 25.5.6, matching process, for details about overrun behavior. table 25-4. message buffer structure field description (continued) field description
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 555 0110 overrun: a frame was overwritten into a full buffer. 0010 if the code indicates overrun but the cpu reads the c/s word and then unlocks the mb, when a new frame is written to the mb the code returns to full. 0110 if the code already indicates overrun, and yet another new frame must be written, the mb will be overwritten again, and the code will remain overrun. see section 25.5.6, matching process , for details about overrun behavior. 0xy1 1 busy: flexcan is updating the contents of the mb. the cpu must not access the mb. 0010 an empty buffer was written with a new frame (xy was 01). 0110 a full/overrun buffer was overwritten (xy was 11). 1 note that for tx mbs (see ta b l e 2 5 - 6 ), the busy bit should be ignored up on read, except when aen bit is set in the mcr register. table 25-6. message buffer code for tx buffers rtr initial tx code code after successful transmission description x 1000 ? inactive: mb does not partic ipate in the arbitration process. x 1001 ? abort: mb was configured as tx and cpu aborted the transmission. this code is only valid when aen bit in mcr is asserted. mb does not participate in the arbitration process. 0 1100 1000 transmit data frame unconditionally once. after transmission, the mb automatically returns to the inactive state. 1 1100 0100 transmit remote frame unconditionally once. after transmission, the mb automatically becomes an rx mb with the same id. 0 1010 1010 transmit a data frame whenever a remote request frame with the same id is received. this mb participates simultaneously in both the matching and arbitration processes. the matching process compares the id of the incoming remote request frame with the id of the mb. if a match occurs this mb is allowed to participate in the current arbitration process and the code field is automatically updated to 1110 to allow the mb to participate in future arbitration runs. when the frame is eventually transmitted successfully, the code automatically returns to 1010 to restart the process again. 0 1110 1010 this is an intermediate code t hat is automatically written to the mb by the mbm as a result of match to a remote request frame. the data frame will be transmitted unconditionally once and then the code will automatically return to 1010. the cpu can also write this code with the same effect. table 25-5. message buffer code for rx buffers rx code before rx new frame description rx code after rx new frame comment
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 556 freescale semiconductor 25.4.3 rx fifo structure when the fen bit is set in the mcr, the memory ar ea from 0x80 to 0xfc (which is normally occupied by mbs 0 to 7) is used by the reception fifo engine. figure 25-3 shows the rx fifo data structure. the region 0x80?0x8c contains an mb stru cture, which is the port through wh ich the cpu reads data from the fifo (the oldest frame r eceived and not read yet). the region 0x90?0x dc is reserved fo r internal use of the fifo engine. the region 0xe0?0xfc contains an 8-entry id table that specifies filtering criteria for accepting frames into the fifo. figure 25-4 shows the three different format s that the elements of the id table can assume, depending on the idam field of the mcr. note that all elements of the table must have the same format. see section 25.5.8, rx fifo , for more information. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0x80 srr ide rtr length time stamp 0x84 id (standard/extended) id (extended) 0x88 data byte 0 data byte 1 data byte 2 data byte 3 0x8c data byte 4 data byte 5 data byte 6 data byte 7 0x90 reserved to 0xdc 0xe0 id table 0 0xe4 id table 1 0xe8 id table 2 0xec id table 3 0xf0 id table 4 0xf4 id table 5 0xf8 id table 6 0xfc id table 7 = unimplemented or reserved figure 25-3. rx fifo structure
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 557 25.4.4 register descriptions the flexcan registers are described in this section in as cending address order. 25.4.4.1 module configur ation register (mcr) this register defines global system configurations, such as the m odule operation mode (e.g., low power) and maximum message buffer configur ation. this register can be acce ssed at any time, however some fields must be changed only during freeze mode. find more information in the fields de scriptions ahead. 012345678910111213141516171819202122232425262728293031 a rem ext rxida (standard = 2?12, extended = 2?30) b rem ext rxidb_0 (standard = 2?12, extended = 2?15) rem ext rxidb_1 (standard = 18?28, extended = 18?31) c rxidc_0 (std/ext = 0?7) rxidc_1 (std/ext = 8?15) rxidc_2 (std/ext = 16?23) rxidc_3 (std/ext = 24?31) = unimplemented or reserved figure 25-4. id table 0?7 table 25-7. rx fifo structure field description field description rem remote frame this bit specifies if remote frames are accepted into the fifo if they match the target id. 0 remote frames are rejected and data frames can be accepted 1 remote frames can be accepted and data frames are rejected ext extended frame specifies whether extended or standar d frames are accepted into the fifo if they match the target id. 0 extended frames are rejected and standard frames can be accepted 1 extended frames can be accepted and standard frames are rejected rxida rx frame identifier (format a) specifies an id to be used as acceptance criteria for the fifo. in the stand ard frame format, only the 11 most significant bits (3 to 13) are used for frame identification. in the extended frame format, all bits are used. rxidb_0, rxidb_1 rx frame identifier (format b) specifies an id to be used as acceptance criteria for the fifo. in the stand ard frame format, the 11 most significant bits (a full standard id) (3 to 13) are used for frame identificat ion. in the extended frame format, all 14 bits of the field are compared to the 14 most significant bits of the received id. rxidc_0, rxidc_1, rxidc_2, rxidc_3 rx frame identifier (format c) specifies an id to be used as acceptance criteria for the fifo. in both standard and extended frame formats, all 8 bits of the field are compared to the 8 most significant bits of the received id.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 558 freescale semiconductor offset: 0x0000 access: supervisor read/write 0123456789101112131415 r mdis frz fen halt not_rdy 0 soft_rst frz_ack supv 0 wrn_en lpm_ack 00 srx_dis bcc w reset: 1101100 note 1 1 different on various platforms, but it is always the opposite of the mdis reset value. 100 note 2 2 different on various platforms, but it is always the same as the mdis reset value. 0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 lprio_en aen 00 idam 00 maxmb w reset: 0 000000000001111 figure 25-5. module configuration register (mcr) table 25-8. mcr field descriptions field description mdis module disable this bit controls whether flexcan is enabled or not. when disabled, flexcan shuts down the clocks to the can protocol interface and message bu ffer management submodules. this is the only bit in mcr not affected by soft reset. see section 25.5.10.2, module disable mode , for more information. 0 enable the flexcan module 1 disable the flexcan module frz freeze enable the frz bit specifies the flexcan behavior when the halt bit in mcr is set or when debug mode is requested at mcu level. when frz is assert ed, flexcan is enabled to enter freeze mode. negation of this bit field causes flexcan to exit from freeze mode. 0 not enabled to enter freeze mode 1 enabled to enter freeze mode fen fifo enable this bit controls whether the fifo feature is enabled or not. when fen is set, mbs 0 to 7 cannot be used for normal reception and transmi ssion because the corresponding memory region (0x80?0xff) is used by the fifo engine. see section 25.4.3, rx fifo structure , and section 25.5.8, rx fifo , for more information. this bit must be written in freeze mode only. 0 fifo not enabled 1 fifo enabled
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 559 halt halt flexcan assertion of this bit puts the flexcan module in to freeze mode. the cpu should clear it after initializing the message buffers and ctrl. no rece ption or transmission is performed by flexcan before this bit is cleared. while in freeze mode, the cpu has write access to ecr, which is otherwise read-only. freeze mode cannot be entere d while flexcan is in any of the low power modes. see section 25.5.10.1, freeze mode , for more information. 0 no freeze mode request. 1 enters freeze mode if the frz bit is asserted. not_rdy flexcan not ready this read-only bit indicates that flexcan is in disable mode or freeze mode. it is negated once flexcan has exited these modes. 0 flexcan module is in normal mode, listen-only mode or loop-back mode 1 flexcan module is in disable mode or freeze mode soft_rst soft reset when this bit is asserted, flexcan resets its internal state machines and some of the memory mapped registers. the following registers are reset: mcr (except the mdis bit), timer, ecr, esr, imask1, imask2, iflag1, iflag2. conf iguration registers that cont rol the interface to the can bus are not affected by soft reset. the following registers are unaffected: ctrl rximr0?rximr63 rxgmask, rx14mask, rx15mask all message buffers the soft_rst bit can be asserted directly by the cpu when it writes to mcr, but it is also asserted when global soft reset is requested at mcu level. since soft reset is synchronous and has to follow a request/acknowledge procedure across clock domains, it may take some time to fully propagate its effect. the soft _rst bit remains asserted while reset is pending, and is automatically negated when reset completes. therefor e, software can poll this bit to know when the soft reset has completed. soft reset cannot be applied while clocks are shut down in any of the low power modes. the module should be first removed from low power mode, and then soft reset can be applied. 0 no reset request 1 resets the registers marked as affected by soft reset in ta b l e 2 5 - 2 frz_ack freeze mode acknowledge this read-only bit indicates that flexcan is in freeze mode and its prescaler is stopped. the freeze mode request cannot be granted until current transmi ssion or reception processes have finished. therefore the software can poll the frz_ack bit to know when flexcan has actually entered freeze mode. if freeze mode request is negate d, then this bit is negated once the flexcan prescaler is running again. if freeze mode is requested while flexcan is in any of the low power modes, then the frz_ack bit will only be set when the low power mode is exited. see section 25.5.10.1, freeze mode , for more information. 0 flexcan not in freeze mode, prescaler running 1 flexcan in freeze mode, prescaler stopped supv supervisor mode this bit configures some of the flexcan registers to be either in supervisor or unrestricted memory space. the registers affected by this bit ar e marked as s/u in the access type column of ta b l e 2 5 - 2 . reset value of this bit is 1, so the affected registers start with su pervisor access restrictions. this bit should be written in freeze mode only. 0 affected registers are in unrestricted memory space 1 affected registers are in supervisor memory space. any access without supervisor permission behaves as though the access was done to an unimplemented register location table 25-8. mcr field descriptions (continued) field description
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 560 freescale semiconductor wrn_en warning interrupt enable when asserted, this bit enables the generation of the twrn_int and rwrn_int flags in the error and status register (esr). if wrn_en is negated, the twrn_int and rwrn_int flags will always be zero, independent of the values of the error counters, and no warning interrupt will ever be generated. this bit must be written in freeze mode only. 0 twrn_int and rwrn_int bits are zero, independent of the values in the error counters. 1 twrn_int and rwrn_int bits are set when the respective error counter transition from < 96 to ? 96. lpm_ack low power mode acknowledge this read-only bit indicates that flexcan is in di sable mode. this mode cannot be entered until all current transmission or reception processes have finished, so the cpu can poll the lpm_ack bit to know when flexcan has actually entered low power mode. see section 25.5.10.2, module disable mode , for more information. 0 flexcan not in any low-power mode 1 flexcan is in disable mode srx_dis self reception disable this bit defines whether flexcan is allowed to rece ive frames transmitted by itself. if this bit is asserted, frames transmitted by the module will not be stored in any mb, regardless if the mb is programmed with an id that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due to the frame reception. this bit must be written in freeze mode only. 0 self reception enabled 1 self reception disabled bcc backwards compatibility configuration this bit is provided to support backwards compatibility with previous flexcan versions. on this device, flexcan supports individual rx id masking using rximr0?63. setting this bit enables individual rx id masking. when this bit is cleared. flexcan uses a backw ards compatible masking scheme with rxgmask, rx14mask, and rx15mask; and t he reception queue feature is disabled. upon receiving a message, if the first mb with a matching id that is found is still occupied by a previous unread message, flexcan will not look for another matchi ng mb. it will override this mb with the new message and set the code field to ?0110? (overrun). this bit is cleared on reset, allowing legacy software to work without modification. this bit must be written in freeze mode only. 0 individual rx masking and queue feature are disabled. 1 individual rx masking and queue feature are enabled. lprio_en local priority enable this bit is provided for backwards compatibility reasons. it controls whether the local priority feature is enabled or not. it is used to extend the id us ed during the arbitration process. with this extended id concept, the arbitration process is done based on the full 32-bit word, but the actual transmitted id still has 11-bit for standard frames and 29-bit for extended frames. this bit must be written in freeze mode only. 0 local priority disabled 1 local priority enabled aen abort enable this bit is supplied for backwards compatibility reasons. when asserted, it enables the tx abort feature. this feature guarantees a safe proced ure for aborting a pending transmission, so that no frame is sent in the can bus wit hout notification. this bit must be written in freeze mode only. 0 abort disabled 1 abort enabled table 25-8. mcr field descriptions (continued) field description
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 561 25.4.4.2 control (ctrl) register this register is defined for specifi c flexcan control features related to the can bus, such as bit rate, programmable sampling point within an rx bit, loop back mode, listen only mode, bus off recovery behavior, and interrupt enabling (bus-off, error, warni ng). it also determines th e division factor for the clock prescaler. most of the fields in this register shoul d only be changed while the module is in disable mode or in freeze m ode. exceptions are the boff_msk, e rr_msk, twrn_msk, rwrn_msk, and boff_rec bits, which can be accessed at any time. idam id acceptance mode this 2-bit field identifies the form at of the elements of the rx fi fo filter table, as shown in table 25-9 . note that all elements of the table are config ured at the same time by this field (they are all the same format). see section 25.4.3, rx fifo structure . this bit must be written in freeze mode only. maxmb maximum number of message buffers this 6-bit field defines the maximum number of me ssage buffers that will take part in the matching and arbitration processes. the reset value (0x0f) is equivalent to 16 mb configuration. this field must be changed only while the module is in freeze mode. maximum mbs in use = maxmb + 1. note: maxmb must be programmed with a value smal ler or equal to the number of available message buffers, otherwise flexcan can transmit and receive wrong messages. table 25-9. idam coding idam format explanation 0b00 a one full id (standard or extended) per filter element. 0b01 b two full standard ids or two partial 14-bit extended ids per filter element. 0b10 c four partial 8-bit ids (standard or extended) per filter element. 0b11 d all frames rejected. table 25-8. mcr field descriptions (continued) field description
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 562 freescale semiconductor offset: 0x0004 access: read/write 0123456789101112131415 r presdiv rjw pseg1 pseg2 w reset: 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r boff_msk err_ msk clk_src lpb twrn_msk rwrn_msk 00 smp boff_rec tsyn lbuf lom propseg w reset: 0000000000000000 figure 25-6. control (ctrl) register table 25-10. ctrl field descriptions field description presdiv prescaler division factor this 8-bit field defines the ratio between the cp i clock frequency and the serial clock (sclock) frequency. the sclock period defines the time quant um of the can protocol. for the reset value, the sclock frequency is equal to the cpi clock frequency. the maximum value of this register is 0xff, that gives a minimum sclock frequency equal to the cpi clock frequency divided by 256. for more information refer to section 25.5.9.4, protocol timing. this bit must be written in freeze mode only. sclock frequency = cpi clock frequency / (presdiv + 1) rjw resync jump width this 2-bit field defines the maximum number of time quanta 1 that a bit time can be changed by one resynchronization. the valid programmable values are 0?3. this bit must be written in freeze mode only. resync jump width = rjw + 1. pseg1 phase segment 1 this 3-bit field defines the length of phase buffer segment 1 in the bit time. the valid programmable values are 0?7. this bit must be written in freeze mode only. phase buffer segment 1 = (pseg1 + 1) time quanta. pseg2 phase segment 2 this 3-bit field defines the length of phase buffer segment 2 in the bit time. the valid programmable values are 1?7. this bit must be written in freeze mode only. phase buffer segment 2 = (pseg2 + 1) time quanta. boff_msk bus off mask this bit provides a mask for the bus off interrupt. 0 bus off interrupt disabled 1 bus off interrupt enabled err_msk error mask this bit provides a mask for the error interrupt. 0 error interrupt disabled 1 error interrupt enabled
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 563 clk_src can engine clock source this bit selects the clock source to the can protocol interface (cpi) to be either the peripheral clock (driven by the pll) or the crystal oscillator clock. the selected clock is the one fed to the prescaler to generate the serial clock (sclock). in order to g uarantee reliable operation, this bit must only be changed while the module is in disable mode. see section 25.5.9.4, protocol timing , for more information. 0 the can engine clock source is the oscillator clock 1 the can engine clock source is the bus clock twrn_msk tx warning interrupt mask this bit provides a mask for the tx warning interrupt associated with the twrn_int flag in esr. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated. 0 tx warning interrupt disabled 1 tx warning interrupt enabled rwrn_msk rx warning interrupt mask this bit provides a mask for the rx warning in terrupt associated with the rwrn_int flag in esr. this bit has no effect if the wrn_en bit in mcr is negated and it is read as zero when wrn_en is negated. 0 rx warning interrupt disabled 1 rx warning interrupt enabled lpb loop back this bit configures flexcan to operate in loop-back mode. in this mode, flexcan performs an internal loop back that can be used for self test oper ation. the bit stream output of the transmitter is fed back internally to the receiver input. the rx can input pin is ignored and the tx can output goes to the recessive state (logic 1). flexcan behaves as it normally does when transmitting, and treats its own transmitted message as a message received from a remote node. in this mode, flexcan ignores the bit sent during the ack slot in the can frame acknowledge field, generating an internal acknowledge bit to ensure proper reception of its own message. both transmit and receive interrupts are generated. this bit must be written in freeze mode only. 0 loop back disabled 1 loop back enabled smp sampling mode this bit defines the sampling mode of can bits at th e rx input. this bit must be written in freeze mode only. 0 just one sample is used to determine the bit value 1 three samples are used to determine the value of the received bit: the regular one (sample point) and two preceding samples, a majority rule is used boff_rec bus off recovery mode this bit defines how flexcan recovers from bus off state. if this bit is negated, automatic recovering from bus off state occurs according to the can specification 2.0b. if the bit is asserted, automatic recovering from bus off is disabled and the module remains in bus off state until the bit is negated by the user. if the negation occurs before 128 sequenc es of 11 recessive bits are detected on the can bus, then bus off recovery happens as if the boff_rec bit had never been asserted. if the negation occurs after 128 sequences of 11 recessive bits o ccurred, then flexcan will resynchronize to the bus by waiting for 11 recessive bits before joining the bus. after negation, the boff_rec bit can be reasserted again during bus off, but it will only be ef fective the next time the module enters bus off. if boff_rec was negated when the module entered bus off, asserting it during bus off will not be effective for the current bus off recovery. 0 automatic recovering from bus off state ena bled, according to can spec 2.0 part b 1 automatic recovering from bus off state disabled table 25-10. ctrl field descriptions (continued) field description
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 564 freescale semiconductor 25.4.4.3 free running timer (timer) register this register represents a 16-bit free running count er that can be read and written by the cpu. the timer is clocked by the flexcan bit clock (whi ch defines the baud rate on the can bus). during a message transmission/recepti on, it increments by one for each bit that is received or transmitted. when there is no message on the bus, it counts using the previously program med baud rate. du ring freeze mode, the timer is not incremented. the timer value is captured at the beginning of the identifier field of any frame on the can bus. this captured value is written into the time stamp entry in a message buffer after a successful reception or transmission of a message. writing to the timer is an indirect operation. the data is first written to an auxili ary register and then an internal request/acknowledge procedur e across clock domains is executed. all this is transparent to the user, except for the fact that the da ta will take some time to be actuall y written to the register. if desired, software can poll the register to discove r when the data was actually written. tsyn timer sync mode this bit enables a mechanism that resets the free-running timer each time a message is received in message buffer 0. this feature provides means to synchronize multiple flexcan stations with a special sync message (i.e., global network time). if the fen bit in mcr is set (fifo enabled), mb8 is used for timer synchronization instead of mb0. this bit must be written in freeze mode only. 0 timer sync feature disabled 1 timer sync feature enabled lbuf lowest buffer transmitted first this bit defines the ordering mechanism for message buffer transmission. when asserted, the lprio_en bit does not affect the priority arbitratio n. this bit must be written in freeze mode only. 0 buffer with highest priority is transmitted first 1 lowest number buffer is transmitted first lom listen-only mode this bit configures flexcan to operate in listen on ly mode. in this mode, transmission is disabled, all error counters are frozen and the module oper ates in a can error passive mode [ref. 1]. only messages acknowledged by another can station will be received. if flexcan detects a message that has not been acknowledged, it will flag a bit0 error (wit hout changing the rec), as if it was trying to acknowledge the message. this bit must be written in freeze mode only. 0 listen only mode is deactivated 1 flexcan module operates in listen only mode propseg propagation segment this 3-bit field defines the length of the propagation segment in the bit time. the valid programmable values are 0?7. this bit must be written in freeze mode only. propagation segment time = (propseg + 1) time quanta. time quantum = one sclock period. 1 one time quantum is equal to the sclock period. table 25-10. ctrl field descriptions (continued) field description
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 565 25.4.4.4 rx global mask (rxgmask) register this register is provided for legacy support and fo r mcus that do not have the individual masking per message buffer feature. setting the bcc bit in mcr causes the rxgmask regist er to have no effect on the module operation. rxgmask is used as acceptance mask for all rx mbs, excluding mbs 14?15, which have individual mask registers. when the fen bit in mcr is set (fifo enabled), the rxgmask also applies to all elements of the id filter table, except elements 6?7, which have individual masks. see section 25.5.8, rx fifo , for important details on usage of rxgmask on filtering process for rx fifo. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. during can messages reception by fl excan, the rxgmask (rx global ma sk) is used as acceptance mask for most of the rx message buffers (mb). when the fifo enable bit in the flexcan module configuration register (c anx_mcr[fen], bit 2) is set, the rxgmask also applies to most of the elements of the id f ilter table. however, there is a misalignment between the position of the id field in the rx mb and in rxida, rxidb, and rx idc fields of the id tables. in fact, the rxida filter in the id tables is shifted one bit to the left from rx mbs id position as shown below: ? rx mb id = bits 3?31 of id word corresponding to mess age id bits 0?28 ? rxida = bits 2?30 of id table co rresponding to message id bits 0?28 the mask bits one-to-one correspondence occurs with the filters bits, not with the incoming message id bits. this leads the rxgmask to affect rx mb and rx fifo filtering in different ways. offset: 0x0008 access: read/write 0123456789101112131415 r0000000000000000 w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r timer w reset: 0 0 00000000000000 figure 25-7. free running timer (timer) register table 25-11. timer field descriptions field description timer free-running timer counter. the timer starts from 0x0000 after reset, counts linearly to 0xffff, and wraps around.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 566 freescale semiconductor for example, if the user intends to mask out the bi t 24 of the id filter of message buffers then the rxgmask will be configured as 0xffff_ffef. as result, bit 24 of the id field of the incoming message will be ignored during fi ltering process for message buffers. this very same configuration of rxgmask would lead bit 24 of rxida to be ?don?t care? and thus bit 25 of th e id field of the incoming message would be ignored during filt ering process for rx fifo. similarly, both rxidb and rx idc filters have multiple misalignments with regards to pos ition of id field in rx mbs, which can lead to erroneous masking during filtering process for either rx fifo or mbs. rx14mask (rx 14 mask) and rx15mask (rx 15 mask) have the same struct ure as the rxgmask. this includes the misalignment problem between the pos ition of the id field in the rx mbs, and in rxida, rxidb, and rxidc fields of the id tables. therefore it is recommended that one of the following actions be ta ken to avoid problems: ? do not enable the rxfifo. if canx_mcr[fen]=0 then the rx fifo is disabled and thus the masks rxgmask, rx14mask, a nd rx15mask do not affect it. ? enable rx individual mask registers. if the ba ckwards compatibility c onfiguration bit in the flexcan module configuration register (canx_mcr[bcc], bit 15) is set then the rx individual mask registers (r ximr0?63) are enabled, and thus the masks rxgmask, rx14mask, and rx15mask are not used. ? do not use masks rxgmask, rx14mask, and rx 15mask (that is, leave them at their reset value, which is 0xffff_ffff) when canx_m cr[fen]=1 and canx_mcr[bcc]=0. in this case, filtering processes for both rx mbs a nd rx fifo are not affected by those masks. ? do not configure any mb as rx (i.e., let all mbs as either tx or inactive) when canx_mcr[fen]=1 and canx_mcr[bcc]=0. in this case, the masks rxgmask, rx14mask, and rx15mask can be us ed to affect id tables wit hout affecting filtering process for rx mbs. offset: 0x0010 access: read/write 0123456789101112131415 r mi31 mi30 mi29 mi28 mi27 mi26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w reset: 1 1 11111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 mi8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w reset: 1 1 11111111111111 figure 25-8. rx global mask (rxgmask) register
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 567 25.4.4.5 rx 14 mask (r x14mask) register this register is provided for legacy support and fo r mcus that do not have the individual masking per message buffer feature. setting the bcc bit in mcr causes the rx14mas k register to ha ve no effect on the module operation. rx14mask is used as acceptance mask for the identi fier in message buffer 14. when the fen bit in mcr is set (fifo enabled), the rxg14mask also applies to element 6 of the id filt er table. this register has the same structure as th e rx global mask register. see section 25.5.8, rx fifo , for important details on usage of rx14mask on filtering process for rx fifo. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. ? address offset: 0x14 ? reset value: 0xffff_ffff 25.4.4.6 rx 15 mask (r x15mask) register this register is provided for legacy support and fo r mcus that do not have the individual masking per message buffer feature. setting the bcc bit in mcr causes the rx15mas k register to ha ve no effect on the module operation. when the bcc bit is negated, rx15mask is used as ac ceptance mask for the identifier in message buffer 15. when the fen bit in mcr is set (fifo enabled), the rxg15mask also applies to element 7 of the id filter table. this register has the same structure as the rx global mask register. refer to section 25.5.8, rx fifo , for important details on usage of rx15mask on filtering process for rx fifo. the contents of this register must be programmed while the module is in freeze mode, and must not be modified when the module is tr ansmitting or r eceiving frames. ? address offset: 0x18 ? reset value: 0xffff_ffff 25.4.4.7 error counte r register (ecr) this register has two 8-bit fields reflecting the value of two flex can error counters: transmit error counter (tx_err_counter fiel d) and receive error count er (rx_err_counter field) . the rules table 25-12. rxgmask field descriptions field description mi n mask bits for normal rx mbs, the mask bits affect the id filter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 0 the corresponding bit in the filter is ?don?t care? 1 the corresponding bit in the filter is checked against the one received
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 568 freescale semiconductor for increasing and decreasing these counters are de scribed in the can protocol and are completely implemented in the flexcan module. both counters are read only except in freeze mode, where they can be written by the cpu. writing to the error counter register while in free ze mode is an indirect ope ration. the data is first written to an auxiliary register an d then an internal request/acknowle dge procedure acro ss clock domains is executed. all this is transparent to the user, except for the fact that the data wi ll take some time to be actually written to the register. if desired, software can poll the regist er to discover when the data was actually written. flexcan responds to any bus state as described in the protocol, e.g., transmit error active or error passive flag, delay its transmission start time (error passive) and avoid any influence on the bus when in bus off state. the following are the basic rule s for flexcan bus state transitions. ? if the value of tx_err_counter or rx_err_c ounter increases to be greater than or equal to 128, the flt_conf field in the error and status register is updated to reflect error passive state. ? if the flexcan state is error passive, and either tx_err_counter or rx_err_counter decrements to a value less than or equal to 127 wh ile the other already sati sfies this condition, the flt_conf field in the error and status regist er is updated to reflect error active state. ? if the value of tx_err_counter increases to be greater than 255, the flt_conf field in the error and status register is updated to reflect bu s off state, and an interrupt may be issued. the value of tx_err_counter is then reset to zero. ? if the flexcan is in bus off stat e, then tx_err_counter is cascaded together wi th another internal counter to count the 128th occurrences of 11 consecutive recessive bits on the bus. hence, tx_err_counter is reset to 0 and counts in a manner where the internal counter counts 11 such bits and then wraps around while incrementing the tx_err_counter. when tx_err_counter reaches the value of 128, the flt_conf field in the error and status register is updated to be error active and both error counters are reset to 0. at any instance of dominant bit following a stream of less than 11 consecutive recessive bits, the internal counter resets itself to 0 without af fecting the tx_err_counter value. ? if during system start-up, only one node is opera ting, then its tx_err_counter increases in each message it is trying to tr ansmit, as a result of acknowledge errors (indi cated by the ack_err bit in the error and status register). afte r the transition to error passive state, the tx_err_counter does not increment anymore by acknowledge errors. therefore the device never goes to the bus off state. ? if the rx_err_counter increases to a value gr eater than 127, it is not incremented further, even if more errors are detect ed while being a receiver. at th e next successful message reception, the counter is set to a value between 119 and 127 to resume to error active state.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 569 25.4.4.8 error and status register (esr) this register reflects various error conditions, some genera l status of the de vice and it is th e source of four interrupts to the cpu. the reported error conditions (bits 16?21) are those that occurr ed since the last time the cpu read this register. the cpu read ac tion clears bits 16?23. bits 22?28 are status bits. most bits in this register are read-only, ex cept twrn_int, rwrn_int, boff_int, and err_int, which are interrupt flags that can be cleared by writing 1 to them (writing 0 has no effect). see section 25.5.11, interrupts , for more details. offset: 0x001c access: read/write 0123456789101112131415 r0000000000000000 w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rx_err_counter tx_err_counter w reset: 0 0 00000000000000 figure 25-9. error counter register (ecr) table 25-13. ecr field descriptions field description rx_error_ counter receive error counter. see the text of this sect ion for a detailed description of this field and how it interacts with tx_error_counter. tx_error_ counter transmit error counter. see the text of this se ction for a detailed description of this field and how it interacts with rx_error_counter.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 570 freescale semiconductor offset: 0x0020 access: read/write 0123456789101112131415 r00000000000000 twrn_int rwrn_int w reset: 00000000000000 0 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bit1_ err bit0_ err ack_ err crc_err frm_err stf_err tx_wrn rx_wrn idle txrx flt_conf 0 boff_int err_ int 0 w reset: 00000000000000 0 0 figure 25-10. error and status register (esr) table 25-14. esr field descriptions field description twrn_int twrn_int ? tx warning interrupt flag if the wrn_en bit in mcr is asserted, the twrn_int bit is set when the tx_wrn flag transition from 0 to 1, meaning that the tx error counter re ached 96. if the corresponding mask bit in the control register (twrn_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to 1. writing 0 has no effect. 0 no such occurrence 1 the tx error counter transition from < 96 to ? 96 rwrn_int rwrn_int ? rx warning interrupt flag if the wrn_en bit in mcr is asserted, the rwrn _int bit is set when the rx_wrn flag transition from 0 to 1, meaning that the rx error counters reached 96. if the corresponding mask bit in the control register (rwrn_msk) is set, an interrupt is generated to the cpu. this bit is cleared by writing it to 1. writing 0 has no effect. 0 no such occurrence 1 the rx error counter transition from < 96 to ? 96 bit1_err bit1_err ? bit1 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 0 no such occurrence 1 at least one bit sent as recessive is received as dominant note: this bit is not set by a transmitter in case of arbitration field or ack slot, or in case of a node sending a passive error flag that detects dominant bits. bit0_err bit0_err ? bit0 error this bit indicates when an inconsistency occurs between the transmitted and the received bit in a message. 0 no such occurrence 1 at least one bit sent as dominant is received as recessive
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 571 ack_err ack_err ? acknowledge error this bit indicates that an acknowledge error has been detected by the transmitter node, i.e., a dominant bit has not been det ected during the ack slot. 0 no such occurrence 1 an ack error occurred since last read of this register crc_err crc_err ? cyclic redundancy check error this bit indicates that a crc error has been detected by the receiver node, i.e., the calculated crc is different from the received. 0 no such occurrence 1 a crc error occurred since last read of this register. frm_err frm_err ? form error this bit indicates that a form error has been detected by the receiver node, i.e., a fixed-form bit field contains at least one illegal bit. 0 no such occurrence 1 a form error occurred since last read of this register stf_err stf_err ? stuffing error this bit indicates that a stuffing error has been detected. 0 no such occurrence. 1 a stuffing error occurred sinc e last read of this register. tx_wrn tx error warning this bit indicates when repetitive errors are occurring during message transmission. 0 no such occurrence 1 tx_err_counter ? 96 rx_wrn rx error counter this bit indicates when repetitive errors are occurring during message reception. 0 no such occurrence 1 rx_err_counter ?? 96 idle can bus idle state this bit indicates when can bus is in idle state. 0 no such occurrence 1 can bus is now idle txrx current flexcan status (transmitting/receiving) this bit indicates if flexcan is transmitting or receiving a message when the can bus is not in idle state. this bit has no meaning when idle is asserted. 0 flexcan is receiving a message (idle=0) 1 flexcan is transmitting a message (idle=0) flt_conf fault confinement state this 2-bit field indicates the confinement state of the flexcan module, as shown in table 25-15 . if the lom bit in the control register is asserted, the flt_conf field will indicate ?error passive?. since the control register is not affected by soft reset, the flt_conf field will not be affected by soft reset if the lom bit is asserted. boff_int bus of f interrupt this bit is set when flexcan enters bus off state. if the corresponding mask bit in the control register (boff_msk) is set, an in terrupt is generated to the cpu. this bit is cleared by writing it to 1. writing 0 has no effect. 0 no such occurrence 1 flexcan module entered bus off state table 25-14. esr field descriptions (continued) field description
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 572 freescale semiconductor 25.4.4.9 interrupt mas ks 2 (imask2) register this register allows any num ber of a range of 32 message buffer in terrupts to be enabled or disabled. it contains one interrupt mask bit per buffer, enabling the cpu to de termine which buffer generates an interrupt after a successful transmission or recepti on (i.e., when the corresponding iflag2 bit is set). err_int error interrupt this bit indicates that at least one of the error bi ts (bits 16-21) is set. if the corresponding mask bit in the control register (err_msk) is set, an inte rrupt is generated to the cpu. this bit is cleared by writing it to 1.writing 0 has no effect. 0 no such occurrence 1 indicates setting of any error bit in the error and status register table 25-15. fault confinement state value meaning 00 error active 01 error passive 1x bus off offset: 0x0024 access: read/write 0123456789101112131415 r buf 63m buf 62m buf 61m buf 60m buf 59m buf 58m buf 57m buf 56m buf 55m buf 54m buf 53m buf 52m buf 51m buf 50m buf 49m buf 48m w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47m buf 46m buf 45m buf 44m buf 43m buf 42m buf 41m buf 40m buf 39m buf 38m buf 37m buf 36m buf 35m buf 34m buf 33m buf 32m w reset: 0 0 00000000000000 figure 25-11. interrupt masks 2 (imask2) register table 25-16. mask2 field descriptions field description buf n m buffer mb n mask each bit enables or disables the respective flexcan message buffer (mb32 to mb63) interrupt. 0 the corresponding buffer interrupt is disabled 1 the corresponding buffer interrupt is enabled note: setting or clearing a bit in the imask2 register can a ssert or negat e an interrupt request, if the corresponding iflag2 bit is set. table 25-14. esr field descriptions (continued) field description
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 573 25.4.4.10 interrupt mas ks 1 (imask1) register this register allows to enable or disable any number of a ra nge of 32 message buffer interrupts. it contains one interrupt mask bit per buffer, en abling the cpu to determine which bu ffer generates an interrupt after a successful transmission or re ception (i.e., when the corresponding iflag1 bit is set). 25.4.4.11 interrupt flags 2 (iflag2) register this register defines the flags for 32 message buffer interrupts. it contains one interrupt flag bit per buffer. each successful transmission or reception sets the corresponding ifla g2 bit. if the corresponding imask2 bit is set, an interrupt will be generated. the interrupt flag must be clea red by writing it to 1. writing 0 has no effect. when the aen bit in the mcr is set (abort enabled), while the iflag2 bit is se t for a mb configured as tx, the writing access done by cpu into the corresponding mb will be blocked. offset: 0x0028 access: read/write 0123456789101112131415 r buf 31m buf 30m buf 29m buf 28m buf 27m buf 26m buf 25m buf 24m buf 23m buf 22m buf 21m buf 20m buf 19m buf 18m buf 17m buf 16m w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15m buf 14m buf 13m buf 12m buf 11m buf 10m buf 9m buf 8m buf 7m buf 6m buf 5m buf 4m buf 3m buf 2m buf 1m buf 0m w reset: 0 0 00000000000000 figure 25-12. interrupt masks 1 (imask1) register table 25-17. imask1 field descriptions field description buf n m buffer mb n mask each bit enables or disables the respective flexcan message buffer (mb0 to mb31) interrupt. 0 the corresponding buffer interrupt is disabled 1 the corresponding buffer interrupt is enabled note: setting or clearing a bit in imask1 can assert or negate an interrupt request, if the corresponding iflag1 bit is set.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 574 freescale semiconductor 25.4.4.12 interrupt flags 1 (iflag1) register this register defines the flags fo r 32 message buffer interrupts and fi fo interrupts. it contains one interrupt flag bit per buffer. each successful transm ission or reception sets the corresponding iflag1 bit. if the corresponding imask1 bit is set, an interrupt will be generated. th e interrupt flag must be cleared by writing it to 1. writing 0 has no effect. when the mcr[aen] bit is set (abort enabled), while the iflag1 bit is set for a mb configured as tx, the writing access done by cpu into th e corresponding mb will be blocked. when the mcr[fen] bit is set (fifo enabled), the function of the 8 least significant interrupt flags (buf7i?buf0i) is changed to support the fifo opera tion. buf7i, buf6i, and buf5i indicate operating conditions of the fifo, while buf4i to buf0i are not used. offset: 0x002c access: read/write 0123456789101112131415 r buf 63i buf 62i buf 61i buf 60i buf 59i buf 58i buf 57i buf 56i buf 55i buf 54i buf 53i buf 52i buf 51i buf 50i buf 49i buf 48i w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 47i buf 46i buf 45i buf 44i buf 43i buf 42i buf 41i buf 40i buf 39i buf 38i buf 37i buf 36i buf 35i buf 34i buf 33i buf 32i w reset: 0 0 00000000000000 figure 25-13. interrupt flags 2 (iflag2) register table 25-18. iflag2 field descriptions field description buf n i buffer mb n interrupt each bit flags the respective flexcan me ssage buffer (mb32 to mb63) interrupt. 0 no such occurrence 1 the corresponding buffer has successfully completed transmission or reception
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 575 25.4.4.13 rx individual mask registers (rximr0 ? rximr63) these registers are used as acceptan ce masks for id filtering in rx mbs and the fifo. if the fifo is not enabled, one mask register is provi ded for each available message buff er, providing id masking capability on a per message buffer basis. when the fifo is en abled (fen bit in mcr is set), the first 8 mask offset: 0x002c access: read/write 0123456789101112131415 r buf 31i buf 30i buf 29i buf 28i buf 27i buf 26i buf 25i buf 24i buf 23i buf 22i buf 21i buf 20i buf 19i buf 18i buf 17i buf 16i w reset: 0 0 00000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r buf 15i buf 14i buf 13i buf 12i buf 11i buf 10i buf 9i buf 8i buf 7i buf 6i buf 5i buf 4i buf 3i buf 2i buf 1i buf 0i w reset: 0 0 00000000000000 figure 25-14. interrupt flags 1 (iflag1) register table 25-19. iflag1 field descriptions field description buf31i?buf8i buffer mb n interrupt each bit flags the respective flexcan message buffer (mb8 to mb31) interrupt. 0 no such occurrence 1 the corresponding mb has successfully completed transmission or reception buf7i buffer mb7 interrupt or fifo overflow if the fifo is not enabled, th is bit flags the interrupt for mb 7. if the fifo is enabled, this flag indicates an overflow condition in the fifo (frame lost because fifo is full). 0 no such occurrence 1 mb7 completed transmission/reception or fifo overflow buf6i buffer mb6 interrupt or fifo warning if the fifo is not enabled, th is bit flags the interrupt for mb 6. if the fifo is enabled, this flag indicates that 5 out of 6 buffers of the fifo are already occupied (fifo almost full). 0 no such occurrence 1 mb6 completed transmission/reception or fifo almost full buf5i buffer mb5 interrupt or frames available in fifo if the fifo is not enabled, th is bit flags the interrupt for mb 5. if the fifo is enabled, this flag indicates that at least one frame is available to be read from the fifo. 0 no such occurrence 1 mb5 completed transmission/reception or frames available in the fifo buf4i?buf0i buffer mb i interrupt or reserved if the fifo is not enabled, these bits flag the interrupts for mb0 to mb4. if the fifo is enabled, these flags are not used and mu st be considered as reserved locations. 0 no such occurrence 1 corresponding mb completed transmission/reception
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 576 freescale semiconductor registers apply to the 8 elements of the fifo filter table (on a one-t o-one correspondence), while the rest of the registers apply to the regular mbs, starting from mb8. the individual rx mask regi sters are implemented in ram, so they are not affected by reset and must be explicitly initialized prior to any reception. furtherm ore, they can only be accessed by the cpu while the module is in freeze mode. out of freeze mode, write accesse s are blocked and read accesses will return all zeros. furthermore, if the bcc bit in mcr is ne gated, any read or write operation to these registers results in access error. 25.5 functional description 25.5.1 overview the flexcan module is a can protocol engine with a very flexible mailbox system for transmitting and receiving can frames. the mailbox system is composed by a set of as many as 64 message buffers (mb) that store configuration and control data , time stamp, message id, and data (see section 25.4.2, message buffer structure ). the memory corresponding to the first 8 mbs can be configured to support a fifo reception scheme with a powerful id filtering mechan ism, capable of checking incoming frames against a table of ids (as many as 8 extende d ids or 16 standard ids or 32 8-bit id slices), each one with its own individual mask register. simultaneous recepti on through fifo and mailbox is supported. for mailbox reception, a matching algorithm makes it possible to st ore received frames only into mbs that have the same id programmed on its id field. a masking scheme makes it possible to match the id programmed on the mb with a range of ids on re ceived can frames. for transmission, an arbitrat ion algorithm decides the prioritization of mbs to be transmitted based on the message id (optionally augmented by 3 local priority bits) or the mb ordering. offsets: 0x0880?0x097f (64 re gisters0 access: read/write 0123456789101112131415 r mi31 mi30 mi29 mi28 mi27 mi 26 mi25 mi24 mi23 mi22 mi21 mi20 mi19 mi18 mi17 mi16 w 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mi15 mi14 mi13 mi12 mi11 mi10 mi9 m i8 mi7 mi6 mi5 mi4 mi3 mi2 mi1 mi0 w figure 25-15. rx individual mask registers (rximr0?rximr63) table 25-20. rximr0?rximr63 field descriptions field description mi n mask bits for normal rx mbs, the mask bits affect the id filter programmed on the mb. for the rx fifo, the mask bits affect all bits programmed in the filter table (id, ide, rtr). 0 the corresponding bit in the filter is ?don?t care? 1 the corresponding bit in the filter is checked against the one received
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 577 before proceeding with the functional description, an important concept must be explained. a message buffer is said to be active at a given time if it ca n participate in the matching and arbitration algorithms that are happening at that ti me. an rx mb with a 0000 c ode is inactive (refer to table 25-5 ). similarly, a tx mb with a 1000 or 1001 code is also inactive (refer to table 25-6 ). an mb programmed with 0000, 1000, (inactive), or 1001 (abort) will be temporarily deactivated (will not participate in the current arbitration or matching run) when the cpu writes to the c/s field of that mb (see section 25.5.7.2, message buffer deactivation ). 25.5.2 local priority transmission the term local priority refers to the priority of transmit messages of the hos t node. this allows increased control over the priority mechanism for transmitting messages. figure 25-2 shows the placement of prio in the id part of the message buffer. an additional 3-bit field (p rio) in the long-word id part of the message buffer structure has been added for local priority determina tion. they are prefixed to the regular id to define the transmission priority. these bits are not transmitted a nd are intended only for tx buffers. perform the following to use the local priority feature: 1. set the lprio_en bit in the canx_mcr. 2. write the additional prio bits in the id long-word of tx messa ge buffers when configuring the tx buffers. with this extended id concept, the arbitration proces s is based on the full 32-bit word. however, the actual transmitted id continues to have 11 bits for standard frames and 29 bits for extended frames. 25.5.3 transmit process in order to transmit a can frame, the cpu must prepare a message buffer for transmission by executing the following procedure: 1. if the mb is active (transmissi on pending), write an abort code ( 1001) to the code field of the control and status word to request an abortion of the transmission, then r ead back the code field and the iflag register to check if the transmission was aborted (see section 25.5.7.1, transmission abort mechanism ). if backwards compatibility is desired (aen in mcr negated), write 1000 to the code field to inactivate the mb but then the pending frame may be transmitted without notification (see section 25.5.7.2, message buffer deactivation ). 2. write the id word. 3. write the data bytes. 4. write the length, control, and c ode fields of the control and status word to activate the mb. once the mb is activated in the fourth step, it will participate into the arbitrat ion process and eventually be transmitted according to its priority. at the end of the successful transmission, the value of the free running timer is written into the time stamp field, the code field in the control and status word is updated, a status flag is set in the interrupt flag regi ster and an interrupt is generated if allowed by the corresponding interrupt mask register bit. the new code field after tr ansmission depends on the code that was used to activate the mb in step four (see table 25-5 and table 25-6 in section 25.4.2, message buffer
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 578 freescale semiconductor structure ). when the abort feature is enable d (aen in mcr is asserted), afte r the interrupt flag is asserted for a mb configured as tran smit buffer, the mb is blocked, therefore the cpu is not able to update it until the interrupt flag be negated by cp u. it means that the cpu must clear the corresponding iflag before starting to prepare this mb for a new transmission or reception. 25.5.4 arbitration process the arbitration process is an algorithm executed by the mbm that scans th e whole mb memory looking for the highest priority message to be transmitted. all mbs program med as transmit buffers will be scanned to find the lowest id 1 or the lowest mb number or the hi ghest priority, depending on the lbuf and lprio_en bits on the control register. the arbitr ation process is triggered in the following events: ? during the crc field of the can frame ? during the error delimiter field of the can frame ? during intermission, if the winner mb defined in a previous arbitration was deactivated, or if there was no mb to transmit, but the cpu wrote to the c/s word of a ny mb after the previous arbitration finished ? when mbm is in idle or bus off state and the cpu writes to the c/s word of any mb ? upon leaving freeze mode when lbuf is asserted, the lprio_en bit has no effect and the lowest number buffer is transmitted first. when lbuf and lprio_en ar e both negated, the mb with the lowest id is transmitted fi rst but. if lbuf is negated and lprio_en is asserte d, the prio bits augment the id us ed during the arb itration process. with this extended id concept, arbi tration is done based on the full 32- bit id and the prio bits define which mb should be transmitted first, therefore mbs wi th prio = 000 have higher pr iority. if two or more mbs have the same priority, the regul ar id will determine th e priority of transmission. if two or more mbs have the same priority (3 extra bits) and the same regular id, the lowest mb will be transmitted first. once the highest priority mb is sel ected, it is transferred to a tem porary storage space called serial message buffer (smb), which has the same structure as a normal mb but is not user accessible. this operation is called move-out and af ter it is done, write access to the corresponding mb is blocked (if the aen bit in mcr is asserted). the write access is released in the following events: ? after the mb is transmitted ? flexcan enters in halt or bus off ? flexcan loses the bus arbitration or th ere is an error during the transmission at the first opportunity window on the can bus, the me ssage on the smb is tran smitted according to the can protocol rules. flexcan tran smits as many as 8 data bytes, ev en if the dlc (data length code) value is bigger. 1. actually, if lbuf is negated, the arbitration considers not only the id, but also the rtr and ide bits placed inside the id a t the same positions they are tr ansmitted in the can frame.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 579 25.5.5 receive process to be able to receive can frames into the mail box mbs, the cpu must prep are one or more message buffers for reception by executing the following steps: 1. if the mb has a pending transmission, write an abort code (1001) to the code field of the control and status word to request an abortion of the transmission, then r ead back the code field and the iflag register to check if the transmission was aborted (see section 25.5.7.1, transmission abort mechanism ). if backwards compatibility is desired (aen in mcr negated), just write 1000 to the code field to inactivat e the mb, but then the pending frame may be transmitted without notification (see section 25.5.7.2, message buffer deactivation ). if the mb already programmed as a receiver, just write 0000 to the code field of the control and status word to keep the mb inactive. 2. write the id word. 3. write 0100 to the code field of the cont rol and status word to activate the mb. once the mb is activated in the third step, it will be able to receive frames that match the programmed id. at the end of a successful reception, the mb is updated by the mbm as follows: 1. the value of the free running timer is written into the time stamp field. 2. the received id, data (8 bytes at most), and length fields are stored. 3. the code field in the control and status word is updated (see table 25-5 and table 25-6 in section 25.4.2, message buffer structure ). 4. a status flag is set in the interrupt flag regist er and an interrupt is ge nerated if allowed by the corresponding interrupt mask register bit. upon receiving the mb interrupt, the cpu should se rvice the received frame using the following procedure: 1. read the control and status word (mandatory ? activates an internal lock for this buffer). 2. read the id field (optional ? ne eded only if a mask was used). 3. read the data field. 4. read the free running timer (optional ? releases the internal lock). upon reading the control and status word, if the busy bit is set in the code field, then the cpu should defer the access to the mb until th is bit is negated. reading the free running timer is not mandatory. if not executed the mb remains locke d, unless the cpu reads th e c/s word of another mb. note that only a single mb is locked at a time. th e only mandatory cpu read operation is the one on the control and status word to assure data coherency (see section 25.5.7, data coherence ). the cpu should synchronize to frame reception by the status flag bit for the specific mb in one of the iflag registers and not by the code field of that mb . polling the code field does not work because once a frame was received and the cpu services the mb (by reading the c/s word followed by unlocking the mb), the code field will not return to empt y. it will remain full, as explained in table 25-5 . if the cpu tries to workaround this behavior by writing to the c/s word to force an empty code after reading the mb, the mb is actually deactivated from any curre ntly ongoing matching process. as a result, a newly received frame matching the id of th at mb may be lost. in summary: never do polling by reading directly the c/s word of the mbs. instead, read the iflag registers.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 580 freescale semiconductor note that the received id field is al ways stored in the matching mb, thus the contents of the id field in an mb may change if the match was due to masking. note also that flexcan does r eceive frames transmitted by itself if there exists an rx matching mb, provi ded the srx_dis bit in the mcr is not asserted. if srx_dis is asserted, flexcan will not store frames transmitted by itself in any mb, even if it contains a matching mb, and no interrupt flag or interrupt si gnal will be generated due to the frame reception. to be able to receive can frames through the fifo, the cpu must enab le and configure the fifo during freeze mode (see section 25.5.8, rx fifo ). upon receiving the frames avai lable interrupt from fifo, the cpu should service the received fram e using the following procedure: 1. read the control and status word (optional ? needed only if a mask wa s used for ide and rtr bits). 2. read the id field (optional ? ne eded only if a mask was used). 3. read the data field. 4. clear the frames available interr upt (mandatory ? release the buffe r and allow the cpu to read the next fifo entry). 25.5.6 matching process the matching process is an algorithm executed by th e mbm that scans the mb memory looking for rx mbs programmed with the same id as the one receiv ed from the can bus. if the fifo is enabled, the 8-entry id table from fifo is sca nned first. if a match is not found wi thin the fifo table, the other mbs are scanned. in the event that the fifo is full, the matching algorithm will alwa ys look for a matching mb outside the fifo region. when the frame is received, it is te mporarily stored in a hi dden auxiliary mb called serial message buffer (smb). the matching process takes pl ace during the crc field of the receiv ed frame. if a matching id is found in the fifo table or in one of the regular mbs, the contents of the smb will be transferred to the fifo or to the matched mb during the 6th bit of the end-of-frame field of the can protocol. this operation is called move-in. if any protocol error (crc, ack, etc.) is detected, than the move-in operation does not happen. for the regular mailbox mbs, an mb is said to be fr ee to receive a new frame if the following conditions are satisfied: ? the mb is not locked (see section 25.5.7.3, message buffer lock mechanism ) ? the code field is either empty or else it is full or overrun but the cpu has already serviced the mb (read the c/s word and then unlocked the mb) if the first mb with a matching id is not free to receive the new fram e, then the matching algorithm keeps looking for another free mb until it finds one. if it cannot find one that is free, then it will overwrite the last matching mb (unless it is locked) a nd set the code field to overrun (refer to table 25-5 and table 25-6 ). if the last matching mb is locked, then th e new message remains in the smb, waiting for the mb to be unlocked (see section 25.5.7.3, message buffer lock mechanism ). suppose, for example, that the fifo is disabled a nd there are two mbs with the same id, and flexcan starts receiving messages with that id. let us say that these mbs are the second and the fifth in the array. when the first message arrives, the matching algorithm will find the first match in mb number 2. the code
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 581 of this mb is empty, so the message is stored there. when the second message arrives, the matching algorithm will find mb number 2 agai n, but it is not free to receive, so it will keep looking and find mb number 5 and store the message there. if yet anothe r message with the same id arrives, the matching algorithm finds out that there are no matching mbs that are free to receive, so it decides to overwrite the last matched mb, which is number 5. in doing so, it se ts the code field of th e mb to indicate overrun. the ability to match the same id in more than one mb can be exploited to implement a reception queue (in addition to the full featured fi fo) to allow more time for the cpu to service the mbs. by programming more than one mb with the same id, received me ssages will be queued into the mbs. the cpu can examine the time stamp field of the mbs to dete rmine the order in which the messages arrived. the matching algorithm described above can be changed to be the same one used in previous versions of the flexcan module. when the bcc bit in mcr is negated, the matchi ng algorithm stops at the first mb with a matching id that it founds, whether this mb is free or not. as a result, the message queueing feature does not work if the bcc bit is negated. matching to a range of ids is possible by using id acceptance masks. flexcan supports individual masking per mb. please refer to section 25.4.4.13, rx individual mask registers (rximr0?rximr63). during the matching algorithm, if a ma sk bit is asserted, th en the corresponding id bi t is compared. if the mask bit is negated, the corresponding id bit is ?don?t care?. please note that the indi vidual mask registers are implemented in ram, so they are not initialized out of reset. also, they can only be programmed if the bcc bit is asserted and while the module is in freeze mode. flexcan also supports an alternate masking sche me with only three mask registers (rgxmask, rx14mask and rx15mask) for backwards compatibilit y. this alternate masking scheme is enabled when the bcc bit in the mcr register is negated. 25.5.7 data coherence in order to maintain data cohere ncy and proper flexcan operation, the cpu must obey the rules described in section 25.5.3, transmit process and section 25.5.5, receive process . any form of cpu accessing an mb structure within flexcan ot her than those specified may cause flexcan to behave in an unpredictable way. 25.5.7.1 transmission abort mechanism the abort mechanism provides a safe way to request the abortion of a pending transmission. a feedback mechanism is provided to inform th e cpu if the transmission was aborte d or if the frame could not be aborted and was transmitted instead. in order to maintain backwards compatibility, the abort mechanism must be explicitly enabled by as serting the aen bit in the mcr. in order to abort a transmission, the cpu must write a specific abort code (1001) to the code field of the control and status word. when the abort mechanism is enabled, the active mbs configured as transmission must be aborte d first and then they may be updated. if th e abort code is written to an mb that is currently being transmitted, or to an mb that was already loaded into th e smb for transmission, the write operation is blocked and the mb is not deactivated, but the abort request is ca ptured and kept pending until one of the followi ng conditions is satisfied: ? the module loses the bus arbitration
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 582 freescale semiconductor ? there is an error during the transmission ? the module is put into freeze mode if none of these conditions is reached, the mb is transm itted correctly, the interrupt flag is set in the iflag register, and an interrupt to the cp u is generated (if enabled). the abor t request is automatically cleared when the interrupt flag is set. on the other hand, if one of the above c onditions is reached, the frame is not transmitted, therefore the abor t code is written into the code field, th e interrupt flag is set in the iflag, and an interrupt is (optiona lly) generated to the cpu. if the cpu writes the abort code before the transmissi on begins internally, then the write operation is not blocked, therefore the mb is updated and no interrupt flag is set. in th is way the cpu just needs to read the abort code to make sure the active mb was deactivated. although th e aen bit is asserted and the cpu wrote the abort code, in this case the mb is deactiv ated and not aborted, because the transmission did not start yet. one mb is only aborted when the abort request is captured and kept pending until one of the previous conditions are satisfied. the abort procedure can be summarized as follows: 1. cpu writes 1001 into the code field of the c/s word. 2. cpu reads the code field and compares it to the value that was written. 3. if the code field that was read is different from the value that was written, the cpu must read the corresponding iflag to check if th e frame was transmitte d or it is being cu rrently transmitted. if the corresponding iflag is set, the frame was tr ansmitted. if the corresponding iflag is reset, the cpu must wait for it to be se t, and then the cpu must read th e code field to check if the mb was aborted (code=1001) or it was transmitted (code=1000). 25.5.7.2 message buffer deactivation deactivation is mechanism pr ovided to maintain data coherence when the cpu writes to the control and status word of active mbs out of freeze mode. any cpu write access to the control and status word of an mb causes that mb to be excluded from the tran smit or receive processes during the current matching or arbitration round. the de activation is temporary, affecting only for the current match/arbitration round. the purpose of deactivation is data coherency. the match/arbitration process scans the mbs to decide which mb to transmit or receive. if the cpu updates the mb in the middle of a match or arbitration process, the data of that mb ma y no longer be coherent, therefore de activation of that mb is done. even with the coherence mechanism described above, writing to the control and status word of active mbs when not in freeze mode may produ ce undesirable results. examples are: ? matching and arbitration are one-p ass processes. if mbs are deactivated after they are scanned, no reevaluation is done to determine a new match/wi nner. if an rx mb with a matching id is deactivated during the matching proce ss after it was scanned, then this mb is marked as invalid to receive the frame, and flexcan wi ll keep looking for another matc hing mb within the ones it has not scanned yet. if it cannot find one, then the message will be lost . suppose, for example, that two mbs have a matching id to a recei ved frame, and the user deactivat ed the first matching mb after flexcan has scanned the second. the received frame will be lost ev en if the second matching mb was free to receive.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 583 ? if a tx mb containing th e lowest id is deactivated after fl excan has scanned it, then flexcan will look for another winner within the mbs that it has not scanned yet. ther efore, it may transmit an mb with id that may not be the lowest at the time because a lo wer id might be present in one of the mbs that it had already scanned before the deactivation. ? there is a point in time until which the deactivati on of a tx mb causes it not to be transmitted (end of move-out). after this point, it is transmitted but no interrupt is issued and the code field is not updated. in order to avoid this situati on, the abort procedures described in section 25.5.7.1, transmission abort mechanism , should be used. 25.5.7.3 message buffer lock mechanism besides mb deactivation, flexcan ha s another data coherence mechanis m for the receive process. when the cpu reads the control and status word of an ?active not empty? rx mb, flexcan assumes that the cpu wants to read the whole mb in an atomic operation, and thus it sets an internal lock flag for that mb. the lock is released when the cpu reads the free running timer (global unlock operation), or when it reads the control and status word of another mb. th e mb locking is done to prevent a new frame to be written into the mb while the cpu is reading it. note the locking mechanism only applies to rx mbs that have a code different than inactive (0000) or empty 1 (0100). also, tx mbs cannot be locked. suppose, for example, that the fifo is disabled and the second and the fifth mbs of the array are programmed with the same id, and flexcan has already received and stored messages into these two mbs. suppose now that the cpu decide s to read mb number 5 and at th e same time another message with the same id is arriving. when the cpu reads the cont rol and status word of mb number 5, this mb is locked. the new message a rrives and the matching algor ithm finds out that ther e are no free to receive mbs, so it decides to override mb number 5. however, this mb is locked, so the new message cannot be written there. it will remain in the smb waiting fo r the mb to be unlocked, a nd only then will be written to the mb. if the mb is not unlocke d in time and yet anothe r new message with the same id arrives, then the new message overwrites th e one on the smb and there wi ll be no indication of lo st messages either in the code field of the mb or in the error and status register. while the message is being moved in from the smb to the mb, the busy bit on the code field is asserted. if the cpu reads the control and status word and finds out that the busy bit is set, it should defer accessing the mb until the busy bit is negated. note if the busy bit is asserted or if the mb is empty, then reading the control and status word does not lock the mb. deactivation takes precedence over lock ing. if the cpu deactivates a locked rx mb, then its lock status is negated and the mb is marked as invalid fo r the current matching round. any pending message on the smb will not be transferred anymore to the mb. 1. in previous flexcan versions, reading the c/s word locked th e mb even if it was empty. this behavior will be honored when the bcc bit is negated.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 584 freescale semiconductor 25.5.8 rx fifo the receive-only fifo is enabled by a sserting the fen bit in the mcr. the reset value of this bit is zero to maintain software backwards comp atibility with previous versions of the module that did not have the fifo feature. when the fifo is enabled, the me mory region normally occ upied by the first 8 mbs (0x80?0xff) is now reserved for use of the fifo engine (see section 25.4.3, rx fifo structure ). management of read and write pointers is done inte rnally by the fifo engine. the cpu can read the received frames sequentially, in the order they we re received, by repeatedly accessing a message buffer structure at the beginning of the memory. the fifo can store as many as 6 fr ames pending service by the cpu. an interrupt is sent to the cpu when new frames are available in the fifo. upon receiv ing the interrupt, the cpu must read the frame (accessing an mb in the 0x80 address) a nd then clear the interrupt. the act of clearing the interrupt triggers the fifo engine to replace the mb in 0x80 with the next frame in the queue, and then issue another interrupt to the cpu. if the fifo is full and more frames continue to be received, an overflow interrupt is issued to the cpu and subsequent frames are not accepted until the cpu creates space in the fifo by reading one or more fram es. a warning interrupt is also generated when five frames are accumulated in the fifo. a powerful filtering scheme is provided to accept onl y frames intended for the target application, thus reducing the interrupt servicing work load. the filter ing criteria is specifie d by programming a table of eight 32-bit registers that can be configured to one of th e following formats (see also section 25.4.3, rx fifo structure ): ? format a: 8 extended or standard ids (including ide and rtr) ? format b: 16 standard ids or 16 extended 14-bit id slices (i ncluding ide and rtr) ? format c: 32 standard or extended 8-bit id slices note a chosen format is applied to all eight re gisters of the filter table. it is not possible to mix formats within the table. the eight elements of the filter ta ble are individually affect ed by the first eight i ndividual mask registers (rximr0?rximr7), allowing ve ry powerful filtering criteria to be defined. the rest of the rximr, starting from rxim8, continue to affe ct the regular mbs, starting from mb8. if the bcc bit is negated (or if the rximr are not available for the particular mcu), then the fifo filt er table is affected by the legacy mask registers as follows: elem ent 6 is affected by rx14mask, el ement 7 is affected by rx15mask and the other elements (0 to 5) are affected by rxgmask. 25.5.9 can protocol related features 25.5.9.1 remote frames remote frame is a special kind of frame. the user can program a mb to be a request remote frame by writing the mb as transmit with the rtr bit set to 1. after the remo te request frame is transmitted successfully, the mb becomes a receive message buffer, with the same id as before.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 585 when a remote request frame is received by flexcan, its id is compared to the ids of the transmit message buffers with the code fi eld 1010. if there is a matching id, then this mb frame will be transmitted. note that if the matching mb has the rt r bit set, then flexcan will transmit a remote frame as a response. a received remote request frame is no t stored in a receive buffer. it is only used to trigger a transmission of a frame in response. the mask re gisters are not used in remote fram e matching, and all id bits (except rtr) of the incoming received frame should match. in the case that a remote request frame was r eceived and matched an mb, this message buffer immediately enters the internal arbi tration process, but is considered as normal tx mb, with no higher priority. the data length of this fr ame is independent of the dlc field in the remote frame that initiated its transmission. if the rx fifo is enabled (bit fen set in mcr), flexcan will not generate an automatic response for remote request frames that match the fifo filteri ng criteria. if the remote frame matches one of the target ids, it will be stor ed in the fifo and presented to the cpu. note that for filtering formats a and b, it is possible to select wh ether remote frames are ac cepted or not. for format c, remote frames are always accepted (if they match the id). 25.5.9.2 overload frames flexcan does transmit overload frames due to detection of following conditions on can bus: ? detection of a dominant bit in th e first/second bit of intermission ? detection of a dominant bit at the 7th bit (last) of end of frame field (rx frames) ? detection of a dominant bit at th e 8th bit (last) of error fram e delimiter or overload frame delimiter 25.5.9.3 time stamp the value of the free running timer is sampled at the beginning of th e identifier field on the can bus, and is stored at the end of move-in in the time st amp field, providing network be havior with respect to time. note that the free running timer can be reset upon a specific frame recepti on, enabling network time synchronization. refer to tsyn description in section 25.4.4.2, control (ctrl) register. 25.5.9.4 protocol timing figure 25-16 shows the structure of the clock generation ci rcuitry that feeds the can protocol interface (cpi) submodule. the clock source bit (clk_src) in the ctrl register define s whether the internal clock is connected to the output of a crystal oscill ator (oscillator clock) or to the peripheral clock (generally from a pll). in order to guarantee reliable opera tion, the clock source s hould be selected while the module is in disable mode (bit mdis set in mcr).
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 586 freescale semiconductor figure 25-16. can engine clocking scheme the crystal oscillator cloc k should be selected whenever a tight to lerance (up to 0.1%) is required in the can bus timing. the crystal oscillator clock has better jitter pe rformance than pll generated clocks. the flexcan module supports a variety of means to set up bit timing para meters that are required by the can protocol. the control register has various fields used to control bit timing parameters: presdiv, propseg, pseg1, pseg2, and rjw. see section 25.4.4.2, control (ctrl) register. the presdiv field controls a prescal er that generates the serial cloc k (sclock), whose period defines the time quantum used to compose the can waveform. a time qua ntum is the atomic uni t of time handled by the can engine. eqn. 25-1 a bit time is subdivided into three segments 1 (reference figure 25-17 and table 25-21 ): ? sync_seg: this segment has a fixed length of one time quantum. signal e dges are expected to happen within this section. ? time segment 1: this segment includes the propa gation segment and the phase segment 1 of the can standard. it can be program med by setting the propseg and the pseg1 fields of ctrl so that their sum (plus 2) is in th e range of 4 to 16 time quanta. ? time segment 2: this segment represents the ph ase segment 2 of the can standard. it can be programmed by setting the pseg2 field of ctrl (plus 1) to be 2 to 8 time quanta long. eqn. 25-2 1. for further explanation of the underlying concepts please refer to iso/dis 11519 ? 1, section 10.3. reference also the bosch can 2.0a/b protocol specificatio n dated september 1991 for bit timing. peripheral clock (pll) oscillator clock (xtal) clk_src prescaler (1 .. 256) sclock cpi clock f tq f canclk prescaler v alue t ?? ---------------------- ----------------- ---------------- - = bit rate f tq number of time quanta tt t ?? ------------------- ----------------- ------------------ ------------------ ---------------- - = t
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 587 figure 25-17. segments within the bit time table 25-22 gives an overview of the can compliant segmen t settings and the related parameter values. note other combinations of time segment 1 and time segment 2 can be valid. it is the user?s responsibility to ensure the bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the value implemented in the flexcan module. table 25-21. time segment syntax syntax description sync_seg system expects transitions to occur on the bus during this period. transmit point a node in transmit mode transfers a new value to the can bus at this point. sample point a node samples the bus at this point. if the three samples per bit option is selected, then this point marks the position of the third sample. table 25-22. bosch can 2.0b standard compliant bit time segment settings time segment 1 time segment 2 resynchronization jump width 5?10 2 1?2 4?11 3 1?3 5?12 4 1?4 6?13 5 1?4 7?14 6 1?4 8?15 7 1?4 9?16 8 1?4 sync_seg time segment 1 time segment 2 1 4 ... 16 2 ... 8 8 ... 25 time quanta = 1 bit time nrz signal sample point (single or triple sampling) (prop_seg + pseg1 + 2) (pseg2 + 1) transmit point
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 588 freescale semiconductor 25.5.9.5 arbitration and matching timing during normal transmission or rece ption of frames, the arbitrati on, matching, move-in, and move-out processes are executed during certain time windows inside the can frame, as shown in figure 25-18 . figure 25-18. arbitration, match, and move time windows when doing matching and arbitration, flexcan needs to scan the whole message bu ffer memory during the available time slot. in order to have sufficient time to do that, the following requirements must be observed: ? a valid can bit timing must be programmed, as indicated in table 25-22 ? the peripheral clock frequency cannot be smaller than the oscillator clock frequency, i.e., the pll cannot be programmed to divi de down the oscillator clock ? there must be a minimum ratio between the peri pheral clock frequency and the can bit rate, as specified in table 25-23 a direct consequence of the first re quirement is that the minimum numbe r of time quanta per can bit must be 8, so the oscillator cl ock frequency should be at least 8 times the can bit ra te. the minimum frequency ratio specified in table 25-23 can be achieved by choosing a high e nough peripheral clock frequency when compared to the oscillator clock frequency, or by adjusting one or more of the bit timing parameters (presdiv, propseg, pseg1, pseg2). as an example, taking the case of 64 mbs, if the oscillator and peripheral clock frequencies are e qual and the can bit timing is progr ammed to have 8 time quanta per bit, then the prescaler factor (pre sdiv + 1) should be at least 2. for prescaler factor equal to one and can bit timing with 8 time quanta per bit, the ratio between peripheral and os cillator clock frequencies should be at least 2. 25.5.10 modes of operation details 25.5.10.1 freeze mode this mode is entered by asserting the halt bit in mcr or when the mc u is put into debug mode. in both cases it is also necessary that th e frz bit is asserted in mcr and th e module is not in a low-power mode table 25-23. minimum ratio between peripheral clock frequency and can bit rate number of message buffers minimum ratio 16 8 32 8 64 16 crc (15) eof (7) interm start move matching/arbitration window (24 bits) move (bit 6) window
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 589 (disable mode). when freeze mode is requested during transmission or rece ption, flexcan does the following: ? waits to be in either intermission, passive error, bus off, or idle state ? waits for all internal activi ties like arbitration, matching, move-in, and move-out to finish ? ignores the rx input pin and dr ives the tx pin as recessive ? stops the prescaler, thus halt ing all can prot ocol activities ? grants write access to the erro r counters register, which is read-only in other modes ? sets the not_rdy and frz_ack bits in mcr after requesting freeze mode, the us er must wait for the frz_ack bit to be asserted in mcr before executing any other action, otherwise flexcan may operate in an unpredic table way. in freeze mode, all memory mapped registers are accessible. exiting freeze mode is done in one of the following ways: ? cpu negates the frz bit in mcr ? the mcu is removed from debug mode and/or the halt bit is negated once out of freeze mode, fl excan tries to resynchronize to the can bus by waiting fo r 11 consecutive recessive bits. 25.5.10.2 module disable mode this low power mode is entered when the mcr[mdis] bit is asserted. if the module is disabled during freeze mode, it requests to disable the clocks to th e can protocol interface (cpi) and message buffer management (mbm) submodules, sets the lpm_ack bi t and negates the frz_ack bit. if the module is disabled during transmission or re ception, flexcan does the following: ? waits to be in either idle or bus off state, or else waits for th e third bit of intermission and then checks it to be recessive ? waits for all internal activi ties like arbitration, matching, move-in, and move-out to finish ? ignores its rx input pin and dr ives its tx pin as recessive ? shuts down the clocks to the cpi and mbm submodules ? sets the not_rdy and lpm_ack bits in mcr the bus interface unit continues to operate, enabling the cpu to access memory mapped registers, except the free running timer, the error counter register, and the message buffers, which cannot be accessed when the module is in disable mode . exiting from this mode is done by negating the mdis bit, which will resume the clocks and negate the lpm_ack bit. 25.5.11 interrupts the module can generate as many as 70 interrupt s ources (64 interrupts due to message buffers and 6 interrupts due to ored interrupts from mbs, bus off, error, tx warning, rx warning, and wake up). the number of actual sources depends on the configured number of message buffers.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 590 freescale semiconductor each one of the message buffers can be an interrupt source, if its co rresponding imask bi t is set. there is no distinction between tx and rx interrupts for a particular buffer, under the assumption that the buffer is initialized for eith er transmission or reception. each of the buffers has assi gned a flag bit in the iflag registers. the bit is set when the corresponding buf fer completes a successful transmission/reception and is cleared when the cpu writes it to 1 (unless another interrupt is gene rated at the same time). note it must be guaranteed that the cpu only clears the bit causing the current interrupt. for this reason, bit manipulati on instructions (bset) must not be used to clear interrupt flags. thes e instructions may cause accidental clearing of interrupt flags that are se t after entering the current interrupt service routine. if the rx fifo is enabled (bit fen on mcr set) , the interrupts corresponding to mbs 0 to 7 have a different behavior. bit 7 of the if lag1 becomes the fifo overflow fl ag; bit 6 becomes the fifo warning flag, bit 5 becomes the frames available in fifo flag, and bits 4?0 are unused. see section 25.4.4.12, interrupt flags 1 (iflag1) register for more information. a combined interrupt for all mbs is also generated by an or of all the interrupt sources from mbs. this interrupt gets generated when any of the mbs generate s an interrupt. in this case the cpu must read the iflag registers to determine wh ich mb caused the interrupt. the other 5 interrupt sources (bus off, error, tx wa rning, rx warning, and wake up) generate interrupts like the mb ones, and can be read from the error and status register. the bus of f, error, tx warning, and rx warning interrupt mask bits are located in ctrl , and the wake-up interrupt mask bit is located in mcr. 25.5.12 bus interface the cpu access to flexcan registers ar e subject to the following rules: ? read and write access to supe rvisor registers in user mo de results in access error. ? read and write access to unimplement ed or reserved address space al so results in access error. any access to unimplemented mb or rx individual mask regist er locations results in access error. any access to the rx individual mask register space when the bcc bit in mcr is negated results in access error. ? if maxmb is programmed with a value smaller than the available number of mbs, then the unused memory space can be used as general pu rpose ram space. note that the rx individual mask registers can only be accessed in freeze mode , and this is still true for unused space within this memory. note also that re served words within ram cannot be used. as an example, suppose flexcan is configured with 64 mbs and maxmb is program med with zero. the maximum number of mbs in this case b ecomes one. the mb memory star ts at 0x0060, but the space from 0x0060 to 0x007f is reserved (for smb usage), and the space fr om 0x0080 to 0x008f is used by the one mb. this leaves us wi th the available space from 0x0090 to 0x047f. the available memory in the mask registers space would be from 0x0884 to 0x097f.
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 591 note unused mb space must not be us ed as general purpose ram while flexcan is transmitting an d receiving can frames. 25.6 initialization/application information this section provide instructions for initializing the flexcan module. 25.6.1 flexcan initialization sequence the flexcan module may be reset in three ways: ? mcu level hard reset, which resets all memory mapped re gisters asynchronously ? mcu level soft reset, which rese ts some of the memory mapped re gisters synchronous ly (refer to table 25-2 to see what registers are affected by soft reset) ? soft_rst bit in mcr, which has the same effect as the mcu level soft reset soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock domains. therefore, it may take some time to full y propagate its effects. the soft_rst bit remains asserted while soft reset is pending, so software can poll this bit to know when the reset has completed. also, soft reset cannot be applied while clocks are shut down in any of the low power modes. the low power mode should be exited and the cloc ks resumed before applying soft reset. the clock source (clk_src bit) should be selected while the module is in disa ble mode. after the clock source is selected and the module is enabled (mdis bit negated), fl excan automatically goes to freeze mode. in freeze mode, flexcan is unsynchronized from the can bus, the halt and frz bits in mcr are set, the internal state machin es are disabled, and the frz_ack an d not_rdy bits in mcr are set. the tx pin is in recessive state and flexcan does not initiate any transmission or reception of can frames. note that the message buffer s and the rx individual mask registers are not affected by reset, so they are not automatically initialized. for any configuration change/initialization it is re quired that flexcan is put into freeze mode (see section 25.5.10.1, freeze mode ). the following is a generic initial ization sequence applicable to the flexcan module: ? initialize mcr ? enable the individual filtering per mb and r eception queue features by setting the bcc bit ? enable the warning interrupts by setting the wrn_en bit ? if required, disable frame self re ception by setting the srx_dis bit ? enable the fifo by setting the fen bit ? enable the abort mechanism by setting the aen bit ? enable the local priority feature by setting the lprio_en bit ?initialize ctrl ? determine the bit timing parame ters: propseg, pseg1, pseg2, rjw ? determine the bit rate by programming the presdiv field
chapter 25 flexcan MPC5606BK microcontroller reference manual, rev. 2 592 freescale semiconductor ? determine the internal ar bitration mode (lbuf bit) ? initialize the message buffers ? the control and status word of all message buffers must be initialized ? if fifo was enabled, the 8-entr y id table must be initialized ? other entries in each message buffer should be initialized as required ? initialize the rx individual mask registers ? set required interrupt mask bits in the imask registers (for all mb interrupts), in ctrl (for bus off and error interrupts), and in mcr for wake-up interrupt ? negate the halt bit in mcr starting with the last event, flexcan attempts to synchronize to the can bus. 25.6.2 flexcan addressing and ram size configurations there are three ram confi gurations that can be implemented wi thin the flexcan module. the possible configurations are: ? for 16 mbs: 288 bytes for mb memory an d 64 bytes for individual mask registers ? for 32 mbs: 544 bytes for mb memory an d 128 bytes for individual mask registers ? for 64 mbs: 1056 bytes for mb memory a nd 256 bytes for individual mask registers in each configuration the user ca n program the maximum number of mbs that will take part in the matching and arbitration processe s using the maxmb field in mcr. for 16 mb conf iguration, maxmb can be any number between 0?15. fo r 32 mb configuration, maxmb ca n be any number between 0?31. for 64 mb configuration, maxmb can be any number between 0?63.
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 593 chapter 26 deserial serial peripheral interface (dspi) 26.1 introduction this chapter describes the deseri al serial peripheral interface (dspi ), which provides a synchronous serial bus for communication between the mcu and an external peripheral device. the MPC5606BK has six iden tical dspi modules (dspi _0 ? dspi_5). the ?x? a ppended to signal names signifies the module to which the si gnal applies. thus cs0_x specifies that the cs0 signal applies to dspi module 0, 1, etc. a block diagram of the dspi is shown in figure 26-1 . figure 26-1. dspi block diagram the register content is trans mitted using an spi protocol. for queued operations the spi queues resi de in internal sram that is exte rnal to the dspi. data transfers between the queues and the dspi fifos are accomplished through the use of the edma controller or through host software. cmd dma and interrupt control tx fifo rx fifo tx data rx data 16 16 shift register sout _x spi spi baud rate, delay and transfer control sin _x sck _x cs0_ x cs1:4 _x cs5 _x intc edma 4
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 594 freescale semiconductor figure 26-2 shows a dspi with external queues in internal sram. figure 26-2. dspi with queues and edma 26.2 features the dspi supports these spi features: ? full-duplex, three-wire synchronous transfers ? master and slave mode ? buffered transmit and r eceive operation using the tx and rx fi fos, with depths of four entries ? visibility into tx and rx fifos for ease of debugging ? fifo bypass mode for low-latency updates to spi queues ? programmable transfer attributes on a per-frame basis ? six clock and transfer attribute registers ? serial clock with programmable polarity and phase ? programmable delays ? cs to sck delay ? sck to cs delay ? delay between frames ? programmable serial frame size of 4 to 16 bits, expanda ble with software control ? continuously held chip select capability ? as many as six peripheral chip selects, e xpandable to 64 with external demultiplexer ? deglitching support for as many as 32 periphera l chip selects with ex ternal demultiplexer ? two dma conditions for spi que ues residing in ram or flash ? tx fifo is not full (tfff) ? rx fifo is not empty (rfdf) ? six interrupt conditions: internal sram tx queue rx queue address/control tx fifo dspi rx fifo rx data tx data tx data rx data shift register edma controller address/control or host cpu
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 595 ? end of queue reached (eoqf) ? tx fifo is not full (tfff) ? transfer of current frame complete (tcf) ? rx fifo is not empty (rfdf) ? fifo overrun (attempt to transmit with an empt y tx fifo or serial frame received while rx fifo is full) (rfof) or (tfuf) ? modified spi transfer formats for comm unication with slower peripheral devices ? supports all functional modes from q spi subblock of qsmcm (mpc500 family) ? continuous serial comm unications clock (sck) 26.3 modes of operation the dspi has five modes of operation. these modes can be divided into two categories: ? module-specific: ma ster, slave, and module disable modes ? mcu-specific: external stop and debug modes the module-specific modes are ente red by host software writing to a register. the mcu-specific modes are controlled by signals external to the dspi. an mc u-specific mode is a mode that the entire device may enter, in parallel to the dspi be ing in one of its module-specific modes. 26.3.1 master mode master mode allows the dspi to initiate and control serial communi cation. in this mode, the sck, cs n , and sout signals are controlled by th e dspi and configured as outputs. for more information, see section 26.6.1.1, master mode . 26.3.2 slave mode slave mode allows the dspi to communicate with spi bus masters. in this mode the dspi responds to externally controlled serial transfers. the dspi cannot initiate serial transfers in slave mode. in slave mode, the sck signal and the cs0_ x signal are configured as input s and provided by a bus master. cs0_ x must be configured as input and pul led high. if the internal pullup is be ing used then the appropriate bits in the relevant siu_pcr must be set (siu_pcr [wpe = 1], [wps = 1]). for more information, see section 26.6.1.2, slave mode . 26.3.3 module disable mode the module disable mode is used for mcu power management. the clock to the non-memory mapped logic in the dspi is stopped while in module disabl e mode. the dspi enters the module disable mode when the mdis bit in dspi x _mcr is set. for more information, see section 26.6.1.3, module disable mode .
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 596 freescale semiconductor 26.3.4 debug mode debug mode is used for system development and de bugging. if the device enters debug mode while the frz bit in the dspi x _mcr is set, the dspi halts operation on th e next frame boundary. if the device enters debug mode while the frz bit is cleared, the dspi be havior is unaffected and remains dictated by the module-specific mode and c onfiguration of the dspi. for more information, see section 26.6.1.4, debug mode . 26.4 external signal description 26.4.1 signal overview table 26-1 lists off-chip dspi signals. 26.4.2 signal names and descriptions 26.4.2.1 peripheral chip sele ct / slave select (cs0_x ) in master mode, the cs0_x signal is a peripheral chip select output that selects the slave device to which the current transmission is intended. in slave mode, the cs0_x signal is a slave select input si gnal that allows an spi master to select the dspi as the target for transmission. cs0_x must be configured as input and pulled high. if the internal pullup is being used then the appropriate bits in the re levant siu_pcr must be set (siu_pcr [wpe = 1], [wps = 1]). set the ibe and obe bits in the siu_ pcr for all cs0_x pins when the d spi chip select or slave select primary function is selected for that pin. when the pin is used for dspi master mode as a chip select output, set the obe bit. when the pin is used in dspi sl ave mode as a slave select input, set the ibe bit. table 26-1. signal properties name i/o type function master mode slave mode cs0_ x output / input peripheral chip select 0 slave select cs1:3_x output peripheral chip select 1?3 unused 1 1 the siul allows you to select alternate pin functions for the device. cs4_x output peripheral chip select 4 master trigger cs5_x output peripheral chip select 5 / peripheral chip select strobe unused 1 sin_x input serial data in serial data in sout_x output serial data out serial data out sck_x output / input serial clock (output) serial clock (input)
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 597 26.4.2.2 peripheral chip selects 1?3 (cs1:3_x) cs1:3_x are peripheral chip select output signals in master mode. in slav e mode these signals are not used. 26.4.2.3 peripheral chip select 4 (cs4_x) cs4_x is a peripheral chip select output signal in master mode. 26.4.2.4 peripheral chip select 5 / peripheral chip select strobe (cs5_x) cs5_x is a peripheral chip select out put signal. when the dspi is in master mode and pcsse bit in the dspi x _mcr is cleared, the cs5_x signal is used to select the slave device that receives the current transfer. cs5_x is a strobe signal used by exte rnal logic for deglitching of the cs signals. when the dspi is in master mode and the pcsse bit in the dspi x _mcr is set, the cs5_x signal in dicates the timing to decode cs0:4_x signals, which preven ts glitches from occurring. cs5_x is not used in slave mode. 26.4.2.5 serial input (sin_ x ) sin_ x is a serial data input signal. 26.4.2.6 serial output (sout_ x ) sout_ x is a serial data output signal. 26.4.2.7 serial clock (sck_ x ) sck_ x is a serial communication clock signal. in mast er mode, the dspi generates the sck. in slave mode, sck_ x is an input from an external bus master. 26.5 memory map and register description 26.5.1 memory map table 26-2 shows the dspi memory map.
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 598 freescale semiconductor 26.5.2 dspi module config uration register (dspi x _mcr) the dspi x _mcr contains bits that config ure attributes of the dspi op eration. the values of the halt and mdis bits can be cha nged at any time, but their effect begi ns on the next frame boundary. the halt and mdis bits in the dspi x _mcr are the only bit valu es software can change while the dspi is running. table 26-2. dspi memory map base addresses: 0xfff9_0000 (dspi_0) 0xfff9_4000 (dspi_1) 0xfff9_8000 (dspi_2) 0xfff9_c000 (dspi_3) 0xfffa_0000 (dspi_4) 0xfffa_4000 (dspi_5) address offset register location 0x00 dspi module configuration register (dspi x _mcr) on page 598 0x04 reserved 0x08 dspi transfer count register (dspi x _tcr) on page 601 0x0c dspi clock and transfer attributes register 0 (dspi x _ctar0) on page 602 0x10 dspi clock and transfer attributes register 1 (dspi x _ctar1) on page 602 0x14 dspi clock and transfer attributes register 2 (dspi x _ctar2) on page 602 0x18 dspi clock and transfer attributes register 3 (dspi x _ctar3) on page 602 0x1c dspi clock and transfer attributes register 4 (dspi x _ctar4) on page 602 0x20 dspi clock and transfer attributes register 5 (dspi x _ctar5) on page 602 0x24?0x28 reserved 0x2c dspi status register (dspi x _sr) on page 610 0x30 dspi dma / interrupt request select and enable register (dspix_rser) on page 612 0x34 dspi push tx fifo register (dspi x _pushr) on page 614 0x38 dspi pop rx fifo register (dspi x _popr) on page 616 0x3c dspi transmit fifo register 0 (dspi x _txfr0) on page 617 0x40 dspi transmit fifo register 1 (dspi x _txfr1) on page 617 0x44 dspi transmit fifo register 2 (dspi x _txfr2) on page 617 0x48 dspi transmit fifo register 3 (dspi x _txfr3) on page 617 0x4c?0x78 reserved 0x7c dspi receive fifo register 0 (dspi x _rxfr0) on page 617 0x80 dspi receive fifo register 1 (dspi x _rxfr1) on page 617 0x84 dspi receive fifo register 2 (dspi x _rxfr2) on page 617 0x88 dspi receive fifo register 3 (dspi x _rxfr3) on page 617
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 599 offset: 0x00 access: read/write 0123456789101112131415 r mstr cont_scke dconf frz mtfe pcsse rooe 00 pcsis5 pcsis4 pcsis3 pcsis2 pcsis1 pcsis0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 mdis dis_txf dis_rxf 00 smpl_pt 0000000 halt w clr_txf clr_rxf reset0100000000000001 figure 26-3. dspi module c onfiguration register (dspi x _mcr) table 26-3. dspi x _mcr field descriptions field description mstr master/slave mode select configures the dspi for master mode or slave mode. 0 dspi is in slave mode 1 dspi is in master mode cont_sck e continuous sck enable enables the serial communication clock (sck) to run continuously. see section 26.6.6, continuous serial communications clock , for details. 0 continuous sck disabled note: 1continuous sck enabled dconf dspi configuration the following table lists the dconf val ues for the various configurations. dconf configuration 00 spi 01 invalid value 10 invalid value 11 invalid value
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 600 freescale semiconductor frz freeze enables the dspi transfers to be stopped on the next frame boundary when the device enters debug mode. 0 do not halt serial transfers 1 halt serial transfers mtfe modified timing format enable enables a modified transfer format to be used. see section 26.6.5.4, modified spi transfer format (mtfe = 1, cpha = 1) , for more information. 0 modified spi transfer format disabled 1 modified spi transfer format enabled pcsse peripheral chip select strobe enable enables the cs5_ x to operate as a cs strobe output signal. see section 26.6.4.5, peripheral chip select strobe enable (cs5_x) , for more information. 0cs5_ x is used as the peripheral chip select 5 signal 1cs5_ x as an active-low cs strobe signal rooe receive fifo overflow overwrite enable enables an rx fifo overflow condition to ignore the incoming serial data or to overwrite existing data. if the rx fifo is full and new data is receiv ed, the data from the transfer that generated the overflow is ignored or put in the shift register. if the rooe bit is set, the incoming data is put in the shift register. if the rooe bit is cleared, the incoming data is ignored. see section 26.6.7.6, receive fifo ov erflow interrupt request (rfof) , for more information. 0 incoming data is ignored 1 incoming data is put in the shift register pcsis n peripheral chip select inactive state determines the inactive state of the cs0_ x signal. cs0_ x must be configured as inactive high for slave mode operation. 0 the inactive state of cs0_ x is low 1 the inactive state of cs0_ x is high mdis module disable allows the clock to stop to the non-memory mapped logic in the dspi, effectively putting the dspi in a software controlled power-saving state. see section 26.6.8, power saving features for more information. 0 enable dspi clocks 1 allow external logic to disable dspi clocks dis_txf disable transmit fifo enables and disables the tx fifo. when the tx fi fo is disabled, the transmit part of the dspi operates as a simplified double-buffered spi. see section 26.6.3.3, fi fo disable operation for details. 0 tx fifo is enabled 1 tx fifo is disabled table 26-3. dspi x _mcr field descriptions (continued) field description
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 601 26.5.3 dspi transfer count register (dspi x _tcr) the dspi x _tcr contains a counter that i ndicates the number of spi transf ers made. the tr ansfer counter is intended to assist in queue management. the user must not write to the dspi x _tcr while the dspi is running. dis_rxf disable receive fifo enables and disables the rx fifo. when the rx fi fo is disabled, the receive part of the dspi operates as a simplified double-buffered spi. see section 26.6.3.3, fi fo disable operation for details. 0 rx fifo is enabled 1 rx fifo is disabled clr_txf clear tx fifo. clr_txf is used to flush the tx fifo. writing a 1 to clr_txf clears the tx fifo counter. the clr_txf bit is always read as zero. 0 do not clear the tx fifo counter 1 clear the tx fifo counter clr_rxf clear rx fifo. clr_rxf is used to flush the rx fifo. writing a 1 to clr_rxf clears the rx counter. the clr_rxf bit is always read as zero. 0 do not clear the rx fifo counter 1 clear the rx fifo counter smpl_pt sample point allows the host software to select when the dspi master samples sin in modified transfer format. figure 26-18 shows where the master can sample the sin pin. the following table lists the delayed sample points. halt halt provides a mechanism for software to start and stop dspi transfers. see section 26.6.2, start and stop of dspi transfers , for details on the operation of this bit. 0 start transfers 1 stop transfers table 26-3. dspi x _mcr field descriptions (continued) field description smpl_pt number of system clock cycles between odd-numbered edge of sck_ x and sampling of sin_ x 00 0 01 1 10 2 11 reserved
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 602 freescale semiconductor 26.5.4 dspi clock and transfer attributes registers 0?5 (dspi x _ctar n ) the dspi modules each contai n six clock and transfer attribute registers (dspi x _ctar n ), which are used to define different transfer at tribute configurations. each dspi x _ctar controls: ?frame size ? baud rate and transfer delay values ? clock phase ? clock polarity ? msb or lsb first dspi x _ctars support compatibility wi th the qspi module in the mp c5606bk family of mcus. at the initiation of an spi transfer, control logic selects the dspi x _ctar that contains the transfer?s attributes. do not write to the dspi x _ctars while the dspi is running. in master mode, the dspi x _ctar n registers define combinations of tran sfer attributes such as frame size, clock phase, and polarity, data bit ordering, baud rate, and various delays . in slave mode, a subset of the bit fields in the dspi x _ctar0 and dspi x _ctar1 registers are used to se t the slave transfer attributes. see the individual bit descriptions for detail s on which bits are used in slave modes. when the dspi is configured as an spi master, th e ctas field in the command portion of the tx fifo entry selects which of the dspi x _ctar registers is used on a per-frame basis. when the dspi is configured as an spi bus slave, the dspi x _ctar0 register is used. offset: 0x08 access: read/write 0123456789101112131415 r spi_tcnt w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 26-4. dspi transfer count register (dspix_tcr) table 26-4. dspi x _tcr field descriptions field description spi_tcn t spi transfer counter counts the number of spi transfers the dspi makes. the spi_tcnt field is incremented every time the last bit of an spi frame is transmitted. a value wri tten to spi_tcnt pr esets the counter to that value. spi_tcnt is reset to zero at the beginning of the frame when the ctcnt field is set in the executing spi command. the transfer counter wraps around, incrementing the counter past 65535 resets the counter to zero.
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 603 . offsets: 0x0c?0x20 (6 registers) access: read/write 0123456789101112131415 r dbr fmsz cpol cpha lsbfe pcssck pasc pdt pbr w reset0111100000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cssck asc dt br w reset0000000000000000 figure 26-5. dspi clock and transfer attributes registers 0?5 (dspi x _ctarn) table 26-5. dspi x _ctar n field descriptions field descriptions dbr double baud rate the dbr bit doubles the effective baud rate of the seri al communications clock (sck). this field is only used in master mode. it effectively halves the baud rate division ratio supporting faster frequencies and odd division ratios for the serial communications clock (sck). when the dbr bit is set, the duty cycle of the serial communications clock (sck) depends on the value in the baud rate prescaler and the clock phase bit as listed in table 26-12 . see the br[0:3] field description for details on how to compute the baud rate. if the overall baud rate is divide by tw o or divide by three of the system clock then neither the continuous sck enable or the modified timing format enable bits should be set. 0 the baud rate is computed normally with a 50/50 duty cycle 1 the baud rate is do ubled with the duty cycl e depending on the baud rate prescaler fmsz frame size the fmsz field selects the number of bits transferred per frame. the fmsz field is used in master mode and slave mode. table 26-13 lists the frame size encodings. cpol clock polarity the cpol bit selects the inactive st ate of the serial communications clock (sck). this bit is used in both master and slave mode. for successful communication between serial devices, the devices must have identical clock polarities. when the continuous selection format is selected, switching between clock polarities without stopping the dspi can cause e rrors in the transfer due to the peripheral device interpreting the switch of clock polarity as a valid clock edge. 0 the inactive state value of sck is low 1 the inactive state value of sck is high cpha clock phase the cpha bit selects which edge of sck causes da ta to change and which edge causes data to be captured. this bit is used in both master an d slave mode. for successful communication between serial devices, the devices must have identica l clock phase settings. continuous sck is only supported for cpha = 1. 0 data is captured on the leading edge of sck and changed on the following edge 1 data is changed on the leading edge of sck and captured on the following edge
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 604 freescale semiconductor lsbfe lsb first the lsbfe bit selects if the lsb or msb of the frame is transferred first. this bit is only used in master mode. 0 data is transferred msb first 1 data is transferred lsb first pcssck pcs to sck delay prescaler the pcssck field selects the prescaler value for the delay between assertion of pcs and the first edge of the sck. this field is only used in master mode. the table below lists the prescaler values. see the cssck field description for details on how to compute the pcs to sck delay. pasc after sck delay prescaler the pasc field selects the prescaler value for the delay between the last edge of sck and the negation of pcs. this field is only used in master mode. the table below lists the prescaler values. see the asc[0:3] field description for details on how to compute the after sck delay. pdt delay after transfer prescaler the pdt field selects the prescaler value for the delay between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginni ng of the next frame. the pdt field is only used in master mode. the table below lists the prescaler values. see the dt[0:3] fiel d description for details on how to compute the delay after transfer. table 26-5. dspi x _ctar n field descriptions (continued) field descriptions pcssck pcs to sck delay prescaler value 00 1 01 3 10 5 11 7 pasc after sck delay prescaler value 00 1 01 3 10 5 11 7 pdt delay after transfer prescaler value 00 1 01 3 10 5 11 7
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 605 pbr baud rate prescaler the pbr field selects the prescaler value for the baud rate. this field is only used in master mode. the baud rate is the frequency of the serial communicat ions clock (sck). the system clock is divided by the prescaler value before the baud rate selection takes place. the baud rate prescaler values are listed in the table below. see the br[0:3] field description for details on how to compute the baud rate. cssck pcs to sck delay scaler the cssck field selects the scaler value for the pcs to sck delay. this field is only used in master mode. the pcs to sck delay is the delay between the assertion of pcs and the first edge of the sck. table 26-14 list the scaler values.the pcs to sck delay is a multiple of the system clock period and it is computed according to the following equation: eqn. 26-1 see section 26.6.4.2, cs to sck delay (tcsc) , for more details. asc after sck delay scaler the asc field selects the scaler value for the after sc k delay. this field is only used in master mode. the after sck delay is the delay between the last edge of sck and the negation of pcs. table 26-15 lists the scaler values.the after sck delay is a mult iple of the system clock period, and it is computed according to the following equation: eqn. 26-2 see section 26.6.4.3, after sck delay (tasc) , for more details. dt delay after transfer scaler the dt field selects the delay after transfer scaler. th is field is only used in master mode. the delay after transfer is the time between the negation of the pcs signal at the end of a frame and the assertion of pcs at the beginning of the next frame. table 26-16 lists the scaler values. in the continuous serial communications clock operation the dt value is fi xed to one tsck. the delay after transfer is a multiple of the system clock pe riod and it is computed acco rding to the fo llowing equation: eqn. 26-3 see section 26.6.4.4, dela y after transfer (tdt) , for more details. table 26-5. dspi x _ctar n field descriptions (continued) field descriptions pbr baud rate prescaler value 00 2 01 3 10 5 11 7 t csc 1 f sys ---------- - pcssck cssck ? ? = t asc 1 f sys ----------- pasc ? asc ? = t dt 1 f sys ----------- pdt ? dt ? =
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 606 freescale semiconductor br baud rate scaler the br field selects the scaler value for the baud ra te. this field is only used in master mode. the prescaled system clock is divided by the baud ra te scaler to generate the frequency of the sck. table 26-17 lists the baud rate scaler values.the baud rate is computed according to the following equation: eqn. 26-4 see section 26.6.4.2, cs to sck delay (tcsc) , for more details. table 26-6. dspi sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 table 26-7. dspi transfer frame size fmsz frame size fmsz frame size 0000 reserved 1000 9 0001 reserved 1001 10 0010 reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16 table 26-5. dspi x _ctar n field descriptions (continued) field descriptions sck baud rate f sys pbr ----------- - 1dbr + br --------------------- - ? =
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 607 table 26-8. dspi pcs to sck delay scaler cssck pcs to sck delay scaler value cssck pcs to sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 26-9. dspi after sck delay scaler asc after sck delay scaler value asc after sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 26-10. dspi delay after transfer scaler dt delay after transfer scaler value dt delay after transfer scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 608 freescale semiconductor table 26-11. dspi baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 table 26-12. dspi sck duty cycle dbr cpha pbr sck duty cycle 0 any any 50/50 1 0 00 50/50 1 0 01 33/66 1 0 10 40/60 1 0 11 43/57 1 1 00 50/50 1 1 01 66/33 1 1 10 60/40 1 1 11 57/43 table 26-13. dspi transfer frame size fmsz frame size fmsz frame size 0000 reserved 1000 9 0001 reserved 1001 10 0010 reserved 1010 11 0011 4 1011 12 0100 5 1100 13 0101 6 1101 14 0110 7 1110 15 0111 8 1111 16
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 609 table 26-14. dspi pcs to sck delay scaler cssck pcs to sck delay scaler value cssck pcs to sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 26-15. dspi after sck delay scaler asc after sck delay scaler value asc after sck delay scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536 table 26-16. dspi delay after transfer scaler dt delay after transfer scaler value dt delay after transfer scaler value 0000 2 1000 512 0001 4 1001 1024 0010 8 1010 2048 0011 16 1011 4096 0100 32 1100 8192 0101 64 1101 16384 0110 128 1110 32768 0111 256 1111 65536
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 610 freescale semiconductor 26.5.5 dspi status register (dspi x _sr) the dspi x _sr contains status and flag bits. the bits are se t by the hardware and reflect the status of the dspi and indicate the occurrence of events that can generate interr upt or dma requests. software can clear flag bits in the dspi x _sr by writing a 1 to clear it (w1c). writ ing a 0 to a flag b it has no effect. this register may not be writable in module disable m ode due to the use of power saving mechanisms. table 26-17. dspi baud rate scaler br baud rate scaler value br baud rate scaler value 0000 2 1000 256 0001 4 1001 512 0010 6 1010 1024 0011 8 1011 2048 0100 16 1100 4096 0101 32 1101 8192 0110 64 1110 16384 0111 128 1111 32768 offset: 0x2c access: r/w 0123456789101112131415 r tcf txrxs 0 eoqf tfuf0tfff00000 rfof 0 rfdf 0 w w1c w1c w1c w1c w1c w1c reset0000001000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txctr txnxtptr rxctr popnxtptr w reset0000000000000000 figure 26-6. dspi status register (dspi x _sr)
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 611 table 26-18. dspi x _sr field descriptions field description tcf transfer complete flag indicates that all bits in a frame have been shifted out. the tcf bit is set after the last incoming data bit is sampled, but before the t asc delay starts. see section 26.6.5.1, classic spi transfer format (cpha = 0) for details. 0 transfer not complete 1 transfer complete txrxs tx and rx status reflects the status of the dspi. see section 26.6.2, start and stop of dspi transfers for information on what clears and sets this bit. 0 tx and rx operations are disabled (dspi is in stopped state) 1 tx and rx operations are enabl ed (dspi is in running state) eoqf end of queue flag indicates that transmission in prog ress is the last entry in a queue. the eoqf bit is set when tx fifo entry has the eoq bit set in t he command halfword and the end of the transfer is reached. see section 26.6.5.1, classic spi transfer format (cpha = 0) for details. when the eoqf bit is set, the txrxs bit is automatically cleared. 0 eoq is not set in the executing command 1 eoq bit is set in the executing spi command note: eoqf does not function in slave mode. tfuf transmit fifo underflow flag indicates that an underflow condition in the tx fi fo has occurred. the transmit underflow condition is detected only for dspi modules operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi o perating in spi slave mode is empty, and a transfer is initiated by an external spi master. 0 tx fifo underflow has not occurred 1 tx fifo underflow has occurred tfff transmit fifo fill flag indicates that the tx fifo can be filled. provides a method for the dspi to request more entries to be added to the tx fifo. the tfff bit is set whil e the tx fifo is not full. the tfff bit can be cleared by writing 1 to it, or an by acknowledgement from the edam controlle r when the tx fifo is full. 0 tx fifo is full 1 tx fifo is not full rfof receive fifo overflow flag indicates that an overflow conditi on in the rx fifo has occurred. th e bit is set when the rx fifo and shift register are full and a transfer is initiated. 0 rx fifo overflow has not occurred 1 rx fifo overflow has occurred
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 612 freescale semiconductor 26.5.6 dspi dma / interrupt reques t select and enable register (dspi x _rser) the dspi x _rser serves two purposes: ? it enables flag bits in the dspi x _sr to generate dma reque sts or interrupt requests. ? it selects the type of request to generate. see the bit descriptions for the t ype of requests that are supported. do not write to the dspi x _rser while the dspi is running. rfdf receive fifo drain flag indicates that the rx fifo can be drained. provi des a method for the dspi to request that entries be removed from the rx fifo. the bit is set while the rx fifo is not empty. the rfdf bit can be cleared by writing 1 to it, or by acknowledgement from the edam controller when the rx fifo is empty. 0 rx fifo is empty 1 rx fifo is not empty note: in the interrupt service routine, rfdf must be cleared only after the dspix_popr register is read. txctr tx fifo counter indicates the number of valid entries in the tx fi fo. the txctr is incremented every time the dspi _pushr is written. the txctr is decremented every time an spi command is executed and the spi data is transferred to the shift register. txnxtptr transmit next pointer indicates which tx fifo entry is transmitted during the next transfer. the txnxtptr field is updated every time spi data is transferred from the tx fifo to the shift register. see section 26.6.3.4, transmit first in fi rst out (tx fifo) bu ffering mechanism for more details. rxctr rx fifo counter indicates the number of entries in the rx fifo. the rxctr is decremented every time the dspi _popr is read. the rxctr is incremented after the last incoming data bit is sampled, but before the t asc delay starts. see section 26.6.5.1, classic spi transfer format (cpha = 0) for details. popnxtpt r pop next pointer contains a pointer to the rx fifo entry that is returned when the dspi x _popr is read. the popnxtptr is updated when the dspi x _popr is read. see section 26.6.3.5, receive first in first out (rx fifo) buffering mechanism for more details. table 26-18. dspi x _sr field descriptions (continued) field description
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 613 offset:0x30 access: read/write 0123456789101112131415 r tcf_re 00 eoqf_re tfuf_re 0 tfff_re tfff_dirs 0000 rfof_re 0 rfdf_re rfdf_dirs w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset0000000000000000 figure 26-7. dspi dma / interrupt request select and enable register (dspix_rser) table 26-19. dspix_rser field descriptions field description tcf_re transmission complete request enable enables tcf flag in the dspi x _sr to generate an interrupt request. 0 tcf interrupt requests are disabled 1 tcf interrupt requests are enabled eoqf_re dspi finished request enable enables the eoqf flag in the dspi x _sr to generate an interrupt request. 0 eoqf interrupt requests are disabled 1 eoqf interrupt requests are enabled tfuf_re transmit fifo underflow request enable the tfuf_re bit enables the tfuf flag in the dspi x _sr to generate an interrupt request. 0 tfuf interrupt requests are disabled 1 tfuf interrupt requests are enabled tfff_re transmit fifo fill request enable enables the tfff flag in the dspi x _sr to generate a request. the tfff_dirs bit selects between generating an interrupt request or a dma requests. 0 tfff interrupt requests or dma requests are disabled 1 tfff interrupt requests or dma requests are enabled tfff_dirs transmit fifo fill dma or interrupt request select selects between generating a dma request or an interrupt request. when the tfff flag bit in the dspi x _sr is set, and the tfff_re bit in the dspi x _rser is set, this bit selects between generating an interrupt request or a dma request. 0 interrupt request is selected 1 dma request is selected
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 614 freescale semiconductor 26.5.7 dspi push tx fifo register (dspi x _pushr) the dspi x _pushr provides a means to write to the tx fifo. data written to this register is transferred to the tx fifo. see section 26.6.3.4, transmit first in firs t out (tx fifo) buffering mechanism , for more information. write accesses of 8 or 16 bits to the dspi x _pushr transfers 32 bits to the tx fifo. note txdata is used in master and slave modes. rfof_re receive fifo overflow request enable enables the rfof flag in the dspi x _sr to generate an interrupt requests. 0 rfof interrupt requests are disabled 1 rfof interrupt requests are enabled rfdf_re receive fifo drain request enable enables the rfdf flag in the dspi x _sr to generate a request. t he rfdf_dirs bit selects between generating an interrupt request or a dma request. 0 rfdf interrupt requests or dma requests are disabled 1 rfdf interrupt requests or dma requests are enabled rfdf_dirs receive fifo drain dma or interrupt request select selects between generating a dma request or an in terrupt request. when the rfdf flag bit in the dspi x _sr is set, and the rfdf_re bit in the dspi x _rser is set, the rfdf_dirs bit selects between generating an interrupt request or a dma request. 0 interrupt request is selected 1 dma request is selected offset:0x34 access: read/write 0123456789101112131415 r cont ctas eoq ctcnt 00 00 pcs5 pcs4 pcs3 pcs2 pcs1 pcs0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r txdata w reset0000000000000000 figure 26-8. dspi push tx fifo register (dspi x _pushr) table 26-19. dspix_rser field descriptions (continued) field description
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 615 table 26-20. dspi x _pushr field descriptions field description cont continuous peripheral chip select enable selects a continuous selection format. the bit is used in spi master mode. the bit enables the selected cs signals to remain asserted between transfers. see section 26.6.5.5, cont inuous selection format , for more information. 0 return peripheral chip select signals to their inactive state between transfers 1 keep peripheral chip select signals asserted between transfers ctas clock and transfer attributes select selects which of the dspi x _ctars is used to set the transfer attrib utes for the spi frame. in spi slave mode, dspi x _ctar0 is used. the following table shows how the ctas values map to the dspi x _ctars. there are eight dspi x _ctars in the device dspi implementation. note: use in spi master mode only. eoq end of queue provides a means for host software to signal to the d spi that the current spi transfer is the last in a queue. at the end of the transfer the eoqf bit in the dspi x _sr is set. 0 the spi data is not the last data to transfer 1 the spi data is the last data to transfer note: use in spi master mode only. ctcnt clear spi_tcnt provides a means for host software to clear the spi transfer counter. the ctcnt bit clears the spi_tcnt field in the dspi x _tcr. the spi_tcnt field is cleared before transmission of the current spi frame begins. 0 do not clear spi_tcnt field in the dspi x _tcr 1 clear spi_tcnt field in the dspi x _tcr note: use in spi master mode only. ctas use clock and transfer attributes from 000 dspi x _ctar0 001 dspi x _ctar1 010 dspi x _ctar2 011 dspi x _ctar3 100 dspi x _ctar4 101 dspi x _ctar5 110 reserved 111 reserved
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 616 freescale semiconductor 26.5.8 dspi pop rx fifo register (dspi x _popr) the dspi x _popr allows you to read the rx fifo. see section 26.6.3.5, receive first in first out (rx fifo) buffering mechanism for a description of the rx fifo opera tions. eight- or 16-bit read accesses to the dspi x _popr fetch the rx fifo data, a nd update the counter and pointer. note reading the rx fifo field fetches da ta from the rx fifo. once the rx fifo is read, the read data pointer is moved to the next entry in the rx fifo. therefore, read dspi x _popr only when you need the data. for compatibility, configure the tlb entry for dspi x _popr as guarded. pcs x peripheral chip select x selects which cs x signals are asserted for the transfer. 0 negate the cs x signal 1 assert the cs x signal note: use in spi master mode only. t x data tr a n s m i t d a t a holds spi data for transfer according to the associated spi command. note: use txdata in master and slave modes. offset:0x38 access: read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset0000000000000000 figure 26-9. dspi pop rx fifo register (dspi x _popr) table 26-21. dspi x _popr field descriptions field description rxdata received data the rxdata field contains the spi data from the rx fifo entry pointed to by the pop next data pointer (popnxtptr). table 26-20. dspi x _pushr field descriptions (continued) field description
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 617 26.5.9 dspi transmit fifo registers 0?3 (dspi x _txfr n ) the dspi x _txfr n registers provide visibility into the tx fifo for debugging purposes . each register is an entry in the tx fifo. the registers are re ad-only and cannot be m odified. reading the dspi x _txfr n registers does not alter the state of the tx fifo. the mcu us es four registers to implement the tx fifo, that is dspi x _txfr0?dspi x _txfr3 are used. 26.5.9.1 dspi receive fifo registers 0?3 (dspi x _rxfr n ) the dspi x _rxfr n registers provide visibility into the rx fifo for debuggi ng purposes. each register is an entry in the rx fifo. the dspi x _rxfr registers are read-only. reading the dspi x _rxfr n registers does not alter the state of the rx fi fo. the device uses four registers to implement the rx fifo, that is dspi x _rxfr0?dspi x _rxfr3 are used. offsets: 0x3c?0x48 (4 registers) access: read 0123456789101112131415 rtxcmd w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rtxdata w reset0000000000000000 figure 26-10. dspi transmit fifo register 0?3 (dspi x _txfr n ) table 26-22. dspi x _txfr n field descriptions field description txcmd transmit command contains the command that sets the transfer attributes for the spi data. see section 26.5.7, dspi push tx fifo register (dspix_pushr) , for details on the command field. t x data tr a n s m i t d a t a contains the spi data to be shifted out.
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 618 freescale semiconductor 26.6 functional description the dspi supports full-duplex, s ynchronous serial communications between the mcu and peripheral devices. all communica tions are through an spi-like protocol. the dspi has one configuration, namely serial periphe ral interface (spi), in which the dspi operates as a basic spi or a queued spi. the dconf field in the dspi x _mcr register determines the dspi configuration. see table 26-3 for the dspi configuration values. the dspi x _ctar0?dspi x _ctar5 registers hold clock and transfer attributes.t he spi configuration can select which ctar to use on a frame by fram e basis by setting the ctas field in the dspi x _pushr. the 16-bit shift register in the master and the 16-bit shift register in the sl ave are linked by the sout_ x and sin_ x signals to form a distributed 32-bit register. when a data tran sfer operation is performed, data is serially shifted a predetermined number of bit pos itions. because the registers are linked, data is exchanged between the master and the slave; the data th at was in the master?s shift register is now in the shift register of the slave, a nd vice versa. at the end of a tr ansfer, the tcf bit in the dspi x _sr is set to indicate a completed transfer. figure 26-12 illustrates how master a nd slave data is exchanged. offsets: 0x7c?0x88 (4 registers) access: read 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rrxdata w reset0000000000000000 figure 26-11. dspi receive fifo registers 0?3 (dspi x _rxfr n ) table 26-23. dspi x _rxfr n field description field description rxdata receive data contains the received spi data.
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 619 figure 26-12. spi serial protocol overview the dspi has six peripheral chip select (cs x ) signals that are be used to select which of the slaves to communicate with. transfer protocols and timing propert ies are shared by the three dspi c onfigurations; these properties are described independently of the configuration in section 26.6.5, transfer formats . the transfer rate and delay settings are described in section 26.6.4, dspi baud rate and clock delay generation . see section 26.6.8, power saving features , for information on the power-s aving features of the dspi. 26.6.1 modes of operation the dspi modules have the foll owing available distinct modes: ? master mode ? slave mode ? module disable mode ? debug mode master, slave, and module disa ble modes are module- specific modes whereas debug mode is device-specific. the module-specific modes are de termined by bits in the dspi x _mcr. debug mode is a mode that the entire device can enter in parallel with the dspi be ing configured in one of its module-specific modes. 26.6.1.1 master mode in master mode the dspi can init iate communications with peripheral devices. the dspi operates as bus master when the mstr bit in the dspi x _mcr is set. the serial co mmunications clock (sck) is controlled by the master dspi. all three dspi configurations are va lid in master mode. in spi configuration, master mode tr ansfer attributes are c ontrolled by the spi command in the current tx fifo entry. the ctas field in the spi command selects which of the dspi x _ctars are used to set the transfer attributes. transfer attribut e control is on a frame by frame basis. see section 26.6.3, serial peripheral interface (spi) configuration for more details. dspi master shift register baud rate generator dspi slave shift register sout_ x sin_ x sout_ x sin_ x sck_ x sck_ x cs_ x cs0_ x
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 620 freescale semiconductor 26.6.1.2 slave mode in slave mode the dspi responds to transfers initiat ed by an spi master. the dspi operates as bus slave when the mstr bit in the dspi x _mcr is negated. the dspi slave is selected by a bus master by having the slave?s cs0_ x asserted. in slave mode the sck is provide d by the bus master. all transfer attributes are controlled by the bus master, ex cept the clock polarity, cl ock phase, and the number of bits to transfer, which must be configured in the dspi slave to communicate correctly. 26.6.1.3 module disable mode the module disable mode is used for mcu power management. the clock to the non-memory mapped logic in the dspi is stopped while in module disabl e mode. the dspi enters the module disable mode when the mdis bit in dspi x _mcr is set. see section 26.6.8, power saving features , for more details on the module disable mode. 26.6.1.4 debug mode the debug mode is used for system development a nd debugging. if the mcu ente rs debug mode while the frz bit in the dspi x _mcr is set, the dspi stops all serial transfers and enters a stopped state. if the mcu enters debug mode while th e frz bit is cleared, the ds pi behavior is unaffected and remains dictated by the module-specific mode and conf iguration of the dspi. the dspi enters debug mode when a debug request is asserted by an external controller. see figure 26-13 for a state diagram. 26.6.2 start and stop of dspi transfers the dspi has two operating states: stopped and running. the states are independent of dspi configuration. the default state of the dspi is stopped. in the sto pped state, no serial transfers are initiated in master mode and no tr ansfers are responded to in slave mode. the stopped state is also a safe state for writing the various c onfiguration registers of the dspi without causin g undetermined results. the txrxs bit in the dspi x _sr is cleared in this state. in the runn ing state, serial transfers take place. the txrxs bit in the dspix_sr is set in the running state. figure 26-13 shows a state diagram of the start and stop mechanism. figure 26-13. dspi start and stop state diagram the transitions are described in table 26-24 . running txrxs = 1 stopped txrxs = 0 reset power-on-reset 0 1 2
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 621 state transitions from running to stopped occur on the next frame boundary if a transfer is in progress, or on the next system clock cycle if no transfers are in progress. 26.6.3 serial peripheral in terface (spi) configuration the spi configuration transfers data se rially using a shift register and a selection of programmable transfer attributes. the dspi is in spi configuration when th e dconf field in the dspi x _mcr is 0b00. the spi frames can be from 4 to 16 bits long. the data to be transmitted can come from queues stored in sram external to the dspi. host software or an edma controller can transf er the spi data from the queues to a first-in first-out (fifo) buffer. the received data is stored in entries in the receive fifo (rx fifo) buffer. host software or an edma controll er transfers the received data from the rx fifo to memory external to the dspi. the fifo buffer operations are described in section 26.6.3.4, transmit first in first out (tx fifo) buffering mechanism , and section 26.6.3.5, receive firs t in first out (rx fifo) buffering mechanism . the interrupt and dma request conditions are described in section 26.6.7, interrupt/dma requests . the spi configuration supports two module-specific modes; master mode and slave mode. the fifo operations are similar for the master mode and slave mode. the main differ ence is that in master mode the dspi initiates and controls the transfer according to the fields in the spi command field of the tx fifo entry. in slave mode the dspi only responds to transfers initiated by a bus master external to the dspi and the spi command field of the tx fifo entry is ignored. 26.6.3.1 spi master mode in spi master mode the dspi initia tes the serial transfers by controll ing the serial communications clock (sck_ x ) and the peripheral chip select (cs x ) signals. the spi command fiel d in the executing tx fifo entry determines which ctars are used to set the transfer attributes and which cs x signal to assert. the command field also contains various bi ts that help with queue management and transfer protocol. the data field in the executing tx fifo entry is loaded into the shift register and shifted out on the serial out table 26-24. state transitions for start and stop of dspi transfers transition no. current state next state description 0 reset stopped generic power-on-reset transition 1 stopped running the dspi starts (transitio ns from stopped to running) when all of the following conditions are true: ? eoqf bit is clear ? debug mode is unselected or the frz bit is clear ? halt bit is clear 2 running stopped the dspi stops (transitions from running to stopped) after the current frame for any one of the following conditions: ? eoqf bit is set ? debug mode is selected and the frz bit is set ? halt bit is set
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 622 freescale semiconductor (sout _x ) pin. in spi master mode, each spi frame to be transmitted has a command associated with it allowing for transfer attribute control on a frame by frame basis. see section 26.5.7, dspi push tx fi fo register (dspix_pushr) , for details on the spi command fields. 26.6.3.2 spi slave mode in spi slave mode the dspi responds to transfers initiated by an spi bus master. the dspi does not initiate transfers. certain transfer attributes such as clock polarity, clock phase, and frame size must be set for successful communication with an spi master. the spi slave mode transfer attr ibutes are set in the dspi x _ctar0. 26.6.3.3 fifo disable operation the fifo disable mechanisms allo w spi transfers without using the tx fifo or rx fifo. the dspi operates as a double-buffered simplified spi when th e fifos are disabled. the tx and rx fifos are disabled separately. the tx fi fo is disabled by writing a 1 to the dis_txf bit in the dspi x _mcr. the rx fifo is disabled by writing a 1 to the dis_rxf bit in the dspi x _mcr. the fifo disable mechanisms are transparent to the user and to host software; transmit data and commands are written to the dspi x _pushr and receiv ed data is read from the dspi x _popr. when the tx fifo is disabled, the tfff, tfuf, and txctr fields in dspi x _sr behave as if th ere is a one-entry fifo but the contents of the dspi x _txfrs and txnxtptr are undefined. when the rx fifo is disabled, the rfdf, rfof, a nd rxctr fields in the dspi x _sr behave as if there is a one-entry fifo but the contents of the dspi x _rxfrs and popnxtptr are undefined. disable the tx and rx fifos only if the fifo must be disabled as a requirement of the application's operating mode. a fifo must be disabled before it is accessed. failure to disable a fifo prior to a first fifo access is not supported, and can result in incorrect results. 26.6.3.4 transmit first in first ou t (tx fifo) buffering mechanism the tx fifo functions as a buffer of spi data and spi commands fo r transmission. the tx fifo holds four entries, each consisting of a command field and a data field. spi co mmands and data are added to the tx fifo by writing to the dspi push tx fifo register (dspi x _pushr). tx fifo entries can only be removed from the tx fifo by bei ng shifted out or by flushing the tx fifo. for more information on dspix_pushr, see section 26.5.7, dspi push tx fi fo register (dspix_pushr) . the tx fifo counter field (txctr) in the dspi status register (dspi x _sr) indicates the number of valid entries in the tx fifo. the txctr is updated every time the dspi _pus hr is written or spi data is transferred into the shift register from the tx fifo. see section 26.5.5, dspi status register (dspix_sr) for more information on dspi x _sr. the txnxtptr field indicates which tx fifo entr y is transmitted during the next transfer. the txnxtptr contains the pos itive offset from dspi x _txfr0 in number of 32-bit registers. for example, txnxtptr equal to two means that the dspi x _txfr2 contains the spi data and command for the next
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 623 transfer. the txnxtptr field is incr emented every time spi da ta is transferred from the tx fifo to the shift register. 26.6.3.4.1 filling the tx fifo host software or the edma controller can add (push) entries to the tx fifo by writing to the dspi x _pushr. when the tx fifo is not full, the tx fifo fi ll flag (tfff) in the dspi x _sr is set. the tfff bit is cleared when the tx fifo is full and the edma controller indi cates that a write to dspi x _pushr is complete or alternatively by host so ftware writing a 1 to the tfff in the dspi x _sr. the tfff can generate a dma request or an interrupt request. see section 26.6.7.2, transmit fifo fill in terrupt or dma request (tfff) , for details. the dspi ignores attempts to push da ta to a full tx fifo; that is, th e state of the tx fifo is unchanged. no error condition is indicated. 26.6.3.4.2 draining the tx fifo the tx fifo entries are re moved (drained) by shifting spi data out through the sh ift register. entries are transferred from the tx fifo to the shift register and shifted out as l ong as there are valid entries in the tx fifo. every time an entry is tr ansferred from the tx fifo to the sh ift register, the tx fifo counter is decremented by one. at the end of a transfer, the tcf bit in the dspi x _sr is set to indicate the completion of a transfer. the tx fifo is flus hed by writing a 1 to the clr_txf bit in dspi x _mcr. if an external spi bus master init iates a transfer with a dspi slave while the slave?s dspi tx fifo is empty, the transmit fifo underflow flag (tfuf) in the slave?s dspi x _sr is set. see section 26.6.7.4, transmit fifo underf low interrupt request (tfuf) , for details. 26.6.3.5 receive first in first ou t (rx fifo) buff ering mechanism the rx fifo functions as a buffer for data receiv ed on the sin pin. the rx fifo holds four received spi data frames. spi data is added to the rx fifo at the completion of a transfer when the received data in the shift register is transferred into the rx fifo . spi data is removed (popped) from the rx fifo by reading the dspi x _popr register. rx fifo entries can only be removed from the rx fifo by reading the dspi x _popr or by flushing the rx fifo. see section 26.5.8, dspi pop rx fi fo register (dspix_popr) for more information on the dspi x _popr. the rx fifo counter field (rxctr) in the dspi status register (dspi x _sr) indicates the number of valid entries in the rx fifo. the rxctr is updated ev ery time the dspi _popr is read or spi data is copied from the shift re gister to the rx fifo. the popnxtptr field in the dspi x _sr points to the rx fifo entry that is returned when the dspi x _popr is read. the popnxtptr contains th e positive, 32-bit word offset from dspi x _rxfr0. for example, popnxtptr equal to two means that the dspi x _rxfr2 contains the received spi data that is returned when dspi x _popr is read. the popnxtptr fiel d is incremented every time the dspi x _popr is read. popnxtptr rolls ove r every four frames on the mcu.
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 624 freescale semiconductor 26.6.3.5.1 filling the rx fifo the rx fifo is filled with the rece ived spi data from the shift regist er. while the rx fifo is not full, spi frames from the shift re gister are transferred to the rx fifo. every time an spi frame is transferred to the rx fifo the rx fifo counter is incremented by one. if the rx fifo and shift register are full and a transfer is initiated, the rfof bit in the dspi x _sr is set indicating an overflow condition. depending on the state of the rooe bit in the dspi x _mcr, the data from the transfer that gene rated the overflow is ignored or put in the shift register . if the rooe bit is set, the incoming data is put in the shift register. if th e rooe bit is cleared, the incoming data is ignored. 26.6.3.5.2 draining the rx fifo host software or the edma ca n remove (pop) entries from th e rx fifo by reading the dspi x _popr. a read of the dspi x _popr decrements the rx fifo counter by one. attempts to pop data from an empty rx fifo are ignored, the rx fifo counter remains unchanged. the data returned from reading an empty rx fifo is undetermined. see section 26.5.8, dspi pop rx fifo register (dspix_popr) for more information on dspi x _popr. when the rx fifo is not empty, the rx fifo drain flag (rfdf) in the dspi x _sr is set. the rfdf bit is cleared when the rx_fifo is empty and the ed ma controller indicates that a read from dspi x _popr is complete; alternatively the rfdf bit ca n be cleared by the host writing a 1 to it. 26.6.4 dspi baud rate an d clock delay generation the sck_ x frequency and the delay values for serial transfer are genera ted by dividing the system clock frequency by a prescaler and a scaler wi th the option of doubling the baud rate. figure 26-14 shows conceptually how th e sck signal is generated. figure 26-14. communications cl ock prescalers and scalers 26.6.4.1 baud rate generator the baud rate is the frequency of the serial communication clock (sck_ x ). the system clock is divided by a baud rate prescaler (defined by dspi x _ctar[pbr]) and baud rate scaler (defined by dspi x _ctar[br]) to produce sck_ x with the possibility of doubling the baud rate. the dbr, pbr, and br fields in the dspi x _ctars select the frequency of sck_ x using the following formula: table 26-25 shows an example of a computed baud rate. prescaler 1 scaler 1 + dbr system clock sck_x sck baud rate f sys pbrprescalervalue ---------------------------------------------------------- 1dbr + brscalervalue -------------------------------------------- =
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 625 26.6.4.2 cs to sck delay (t csc ) the cs _x to sck _x delay is the length of time from assertion of the cs _x signal to the first sck _x edge. see figure 26-16 for an illustration of the cs _x to sck _x delay. the pcssck and cssck fields in the dspi x _ctar n registers select the cs _x to sck _x delay, and the relations hip is expressed by the following formula: table 26-26 shows an example of the computed cs to sck _x delay. 26.6.4.3 after sck delay (t asc ) the after sck _x delay is the length of time between the last edge of sck _x and the negation of cs _x . see figure 26-16 and figure 26-17 for illustrations of the after sck _x delay. the pasc a nd asc fields in the dspi x _ctar n registers select the after sck delay. the re lationship between these variables is given in the following formula: table 26-27 shows an example of the computed after sck delay. 26.6.4.4 delay after transfer (t dt ) the delay after transfer is the lengt h of time between negation of the cs x signal for a frame and the assertion of the cs x signal for the next frame. the pdt and dt fields in the dspi x _ctar n registers select the delay after transfer. see figure 26-16 for an illustration of the delay after transfer. the following formula expresses the pdt/ dt/delay after transfer relationship: table 26-25. baud rate computation example f sys pbr prescaler value br scaler value dbr value baud rate 64 mhz 0b00 2 0b0000 2 0 16 mbit/s 20 mhz 0b00 2 0b0000 2 1 10 mbit/s table 26-26. cs to sck delay computation example pcssck prescaler valu e cssck scaler value f sys cs to sck delay 0b01 3 0b0100 32 64 mhz 1.5 s table 26-27. after sck delay computation example pasc prescaler value asc scaler value f sys after sck delay 0b01 3 0b0100 32 64 mhz 1.5 s t csc = f sys cssck ? pcssck 1 ? asc = f sys asc ? pasc 1 ?
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 626 freescale semiconductor table 26-28 shows an example of the computed delay after transfer. 26.6.4.5 peripheral chip sele ct strobe enable (cs5_ x ) the cs5 _x signal provides a delay to allow the cs x signals to settle after transitioning thereby avoiding glitches. when the dspi is in master mode and pcsse bit is set in the dspi x _mcr, cs5 _x provides a signal for an external demul tiplexer to decode the cs4_ x signals into as many as 32 glitchfree cs x signals. figure 26-15 shows the timing of the cs5 _x signal relative to cs signals. figure 26-15. peripheral chip select strobe timing the delay between the assertion of the cs x signals and the assertion of cs5 _x is selected by the pcssck field in the dspi x _ctar based on the following formula: at the end of the transfer the delay between cs5 _x negation and cs x negation is selected by the pasc field in the dspi x _ctar based on the following formula: table 26-29 shows an example of the computed t pcssck delay. table 26-30 shows an example of the computed the t pasc delay. table 26-28. delay after transfer computation example pdt prescaler value dt scaler value f sys delay after transfer 0b01 3 0b1110 32768 64 mhz 1.54 ms table 26-29. peripheral chip select strobe assert computation example pcssck prescaler f sys delay before transfer 0b11 7 64 mhz 109.4 ns t dt = f sys dt ? pdt 1 ? x csx t pcssck t pasc t pcssck = pcssck ? f sys 1 t pa s c = pasc ? f sys 1
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 627 26.6.5 transfer formats the spi serial communication is controlled by the serial communications clock (sck_ x ) signal and the cs x signals. the sck_ x signal provided by the master device synchronizes shifting and sampling of the data by the sin_ x and sout_ x pins. the cs x signals serve as enable si gnals for the slave devices. when the dspi is the bus master, the cpol and cpha bits in the dspi clock and transfer attributes registers (dspi x _ctar n ) select the polarity and phase of the serial clock, sck_ x . the polarity bit selects the idle state of the sck_ x . the clock phase bit selects if the data on sout_ x is valid before or on the first sck_ x edge. when the dspi is the bus slave, cpol and cpha bits in the dspi x _ctar0 (spi slave mode) select the polarity and phase of the serial clock. even though th e bus slave does not control the sck signal, clock polarity, clock phase and number of b its to transfer must be identical for the master device and the slave device to ensure proper transmission. the dspi supports four different transfer formats: ? classic spi with cpha = 0 ? classic spi with cpha = 1 ? modified transfer format with cpha = 0 ? modified transfer format with cpha = 1 a modified transfer format is supported to allow for high-speed communication with peripherals that require longer setup times. the dspi can sample the incoming data later than halfway through the cycle to give the peripheral more set up time. the mtfe bit in the dspi x _mcr selects between classic spi format and modified transf er format. the classic spi formats are described in section 26.6.5.1, classic spi transfer format (cpha = 0) , and section 26.6.5.2, classic spi tr ansfer format (cpha = 1) . the modified transfer formats are described in section 26.6.5.3, modified spi transf er format (mtfe = 1, cpha = 0) , and section 26.6.5.4, modified spi transf er format (mtfe = 1, cpha = 1) . in the spi configuration, the dspi provides the option of keeping the cs signals asserted between frames. see section 26.6.5.5, continuous selection format for details. table 26-30. peripheral chip select strobe negate computation example pasc prescaler f sys delay after transfer 0b11 7 64 mhz 109.4 ns
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 628 freescale semiconductor 26.6.5.1 classic spi tran sfer format (cpha = 0) the transfer format shown in figure 26-16 is used to communicate with peripheral spi slave devices where the first data bit is available on the first clock edge. in this format , the master and slave sample their sin_ x pins on the odd-numbered sck_ x edges and change the data on their sout_ x pins on the even-numbered sck_ x edges. figure 26-16. dspi transfer timing diagram (mtfe = 0, cpha = 0, fmsz = 8) the master initiates the transfer by placing its first data bit on the sout_ x pin and asserting the appropriate peripheral chip select signals to the slav e device. the slave responds by placing its first data bit on its sout_ x pin. after the t csc delay has elapsed, the master outputs the first edge of sck_ x . this is the edge used by the mast er and slave devices to samp le the first input data bit on their se rial data input signals. at the second edge of the sck_ x the master and slave devices place their second data bit on their serial data output signals. for th e rest of the frame the master and the slave sample their sin_ x pins on the odd-numbered clock edges and cha nges the data on their sout_ x pins on the even-numbered clock edges. after the last clock edge occurs a delay of t asc is inserted before the mast er negates the cs signals. a delay of t dt is inserted before a new frame tran sfer can be initiated by the master. for the cpha = 0 condition of the master, tcf and eoqf are set and the rxctr counter is updated at the next to last serial clock edge of the frame (edge 15) of figure 26-16 . for the cpha = 0 condition of the sl ave, tcf is set and the rxctr count er is updated at the last serial clock edge of the frame (edge 16) of figure 26-16 . sck (cpol = 0) pcs x / ss t asc sck (cpol = 1) master and slave sample master sout / slave sin master sin / slave sout bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb lsb t dt t csc t csc msb first (lsbfe = 0): lsb first (lsbfe = 1): t csc = cscs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs idle time). master (cpha = 0): tcf and eoqf are set and rxctr counter is updated at next to last sck edge of frame (edge 15) slave (cpha = 0): tcf is set and rxctr counter is updated at last sck edge of frame (edge 16) 1234567891011121314 16 15
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 629 26.6.5.2 classic spi transfer format (cpha = 1) this transfer format shown in figure 26-17 is used to communicate with pe ripheral spi slav e devices that require the first sck_ x edge before the firs t data bit becomes avai lable on the slave sout_ x pin. in this format the master and slave devices change the data on their sout_ x pins on the odd-numbered sck_ x edges and sample the data on their sin_ x pins on the even-numbered sck_ x edges. figure 26-17. dspi transfer timing diagram (mtfe = 0, cpha = 1, fmsz = 8) the master initiates the tr ansfer by asserting the cs x signal to the slave. after the t csc delay has elapsed, the master generates the first sck_ x edge and at the same time pla ces valid data on the master sout_ x pin. the slave responds to the first sck_ x edge by placing its first da ta bit on its slave sout_ x pin. at the second edge of the sck_ x the master and slave sample their sin_ x pins. for the rest of the frame the master and the slave change the data on their sout_ x pins on the odd-numbered clock edges and sample their sin_ x pins on the even-numbered clock edges. afte r the last clock edge occurs a delay of t asc is inserted before the master negates the cs x signal. a delay of t dt is inserted before a new frame transfer can be ini tiated by the master. for cpha = 1 the master eoqf and tcf and slave tcf ar e set at the last serial clock edge (edge 16) of figure 26-17 . for cpha = 1 the master and slave rxctr counters are updated on the same clock edge. slave (cpha = 1): tcf is set and rxctr counter is updated at last sck edge of frame (edge 16) sck 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (cpol = 0) pcsx / ss t asc sck (cpol = 1) master and slave sample master sout/ slave sin master sin/ slave sout bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb lsb t dt t csc msb first (lsbfe = 0): lsb first (lsbfe = 1): t csc = cs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs negation time). master (cpha = 1): tcf and eoqf are set and rxctr counter is updated at last sck edge of frame (edge 16) 16
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 630 freescale semiconductor 26.6.5.3 modified spi transfer format (mtfe = 1, cpha = 0) in this modified transfer format bot h the master and the slave sample later in the sck period than in classic spi mode to allow for delays in device pads and boa rd traces. these delays become a more significant fraction of the sck period as the sck pe riod decreases with increasing baud rates. note for the modified transfer format to operate correctly, you must thoroughly analyze the spi link timing budget. the master and the slave place data on the sout_ x pins at the assertion of the cs x signal. after the cs x to sck_ x delay has elapsed the first sck_ x edge is generated. the slave samples the master sout_ x signal on every odd numbered sck_ x edge. the slave also places new data on the slave sout_ x on every odd numbered clock edge. the master places its second data bit on the sout_ x line one system clock after odd numbered sck_ x edge. the point where the master samples the slave sout_ x is selected by writing to the smpl_pt field in the dspi x _mcr. table 26-31 lists the number of system clock cycles between the active edge of sck_ x and the master sample point for different values of the smpl_pt bit field. the master sample point can be delayed by one or two system clock cycles. figure 26-18 shows the modified transfer format for cpha = 0. only the condition where cpol = 0 is illustrated. the delayed master sample points are indicated with a lighter shaded arrow. table 26-31. delayed master sample point smpl_pt number of system clock cycles between odd-numbered edge of sck and sampling of sin 00 0 01 1 10 2 11 invalid value
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 631 figure 26-18. dspi modified transfer format (mtfe = 1, cpha = 0, f sck = f sys / 4) 26.6.5.4 modified spi transfer format (mtfe = 1, cpha = 1) at the start of a transfer the dspi asserts the cs signal to the slave de vice. after the cs to sck delay has elapsed the master and the slave put data on their sout pins at the firs t edge of sck. the slave samples the master sout signal on the even numbered edges of sck. the mast er samples the slave sout signal on the odd numbered sck edges starting with the third sck edge. the slave samples the last bit on the last edge of the sck. the master samples the last sl ave sout bit one half sck cycle after the last edge of sck. no clock edge is visible on the master sck pin during the sampling of the last bit. the sck to cs delay must be greater or e qual to half of the sck period. note for the modified transfer format to operate correctly, you must thoroughly analyze the spi link timing budget. figure 26-19 shows the modified transfer format for cpha = 1. only the condition where cpol = 0 is described. t csc = cs to sck delay. t asc = after sck delay. system clock 123456 cs x t asc sck master sample slave sout master sout system clock system clock slave sample t csc
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 632 freescale semiconductor figure 26-19. dspi modified transfer format (mtfe = 1, cpha = 1, f sck = f sys / 4) 26.6.5.5 continuous selection format some peripherals must be deselected between every transfer. other peripherals must remain selected between several sequential se rial transfers. the continuous selectio n format provides the flexibility to handle both cases. the conti nuous selection format is enabled for the spi configuration by setting the cont bit in the spi command. when the cont bit = 0, the dspi drives the asserted ch ip select signals to their idle states in between frames. the idle states of the chip select si gnals are selected by the pcsis field in the dspi x _mcr. figure 26-20 shows the timing diagram for two 4-b it transfers with cpha = 1 and cont = 0. figure 26-20. example of non-continuous format (cpha = 1, cont = 0) t csc = cs to sck delay. t asc = after sck delay. system clock 123456 cs t asc sck master sample master sout slave sout slave sample t csc sck (cpol = 0) csx t asc sck (cpol = 1) master sout t dt t csc t csc = cs to sck delay. t asc = after sck delay. t dt = delay after transfer (minimum cs negation time). master sin t csc
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 633 when the cont = 1 and the cs signal for the next transf er is the same as for the current transfer, the cs signal remains asserted for the duration of the two transfers. the delay between transfers (t dt ) is not inserted between the transfers. figure 26-21 shows the timing diagram for two 4-b it transfers with cpha = 1 and cont = 1. figure 26-21. example of continuous transfer (cpha = 1, cont = 1) in figure 26-21 , the period length at th e start of the next transfer is the sum of t asc and t csc ; that is, it does not include a half-clock period. the default settings for these provide a total of four system clocks. in many situations, t asc and t csc must be increased if a full half-clock period is required. switching ctars between frames whil e using continuous selection can cau se errors in the transfer. the cs signal must be negated before ctar is switched. when the cont bit = 1 and the cs sign als for the next transfer are differ ent from the present transfer, the cs signals behave as if the cont bit was not set. note you must fill the txfifo with th e number of entries that will be concatenated together under one pcs assertion for both master and slave before the txfifo becomes empty. for example; while transmitting in master mode, ensure that the last en try in the txfifo, after which txfifo becomes empty, has cont = 0 in the command frame. when operating in slave mode, ensure that when the last entry in the txfifo is completely transmitted (i.e. the corresponding tcf flag is asserted and txfifo is empty) the slav e is deselected for any further serial communication; otherwise, an underflow error occurs. 26.6.5.6 clock polarity switch ing between dspi transfers if it is desired to switch polar ity between non-continuous dspi frames, the edge generated by the change in the idle state of the clock occurs one system clock before the assertio n of the chip select for the next frame. sck (cpol = 0) cs t asc sck (cpol = 1) master sout t csc t csc t csc = cs to sck delay. t asc = after sck delay. master sin
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 634 freescale semiconductor see section 26.5.4, dspi clock and transfer a ttributes registers 0?5 (dspix_ctarn) . in figure 26-22 , time a shows the one clock interval. time b is user programmable from a minimum of two system clocks. figure 26-22. polarity switching between frames 26.6.6 continuous serial communications clock the dspi provides the option of ge nerating a continuous sck signal for slave peripherals that require a continuous clock. continuous sck is enabled by setti ng the cont_scke bit in the dspi x _mcr. continuous sck is valid in all configurations. continuous sck is only supported fo r cpha = 1. setting cpha = 0 is i gnored if the cont_scke bit is set. continuous sck is supported for modified transfer format. clock and transfer attributes fo r the continuous sck mode are set according to the following rules: ? the tx fifo must be cleared before initiating any spi conf iguration transfer. ? when the dspi is in spi confi guration, ctar0 is used initially. at the start of each spi frame transfer, the ctar specified by the ctas for the frame should be ctar0. ? in all configurations, the currentl y selected ctar remains in use until the start of a frame with a different ctar specified, or the c ontinuous sck mode is terminated. the device is designed to use the same baud rate for all transfers ma de while using the continuous sck. switching clock polarity between frames while using continuous sck can cause errors in the transfer. continuous sck operation is not guaranteed if the dspi is put into module disable mode. enabling continuous sck disables the cs to sck delay and th e after sck delay. the delay after transfer is fixed at one sck cycle. figure 26-23 shows timing diagram for continuous sck format with continuous selection disabled. note when in continuous sck mode, always use ctar0 for the spi transfer, and clear the txfifo using the mcr[ clr_txf] field before initiating transfer. cs system clock sck frame 1 frame 0 cpol = 0 cpol = 1 ab
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 635 figure 26-23. continuous sc k timing diagram (cont= 0) if the cont bit in the tx fifo entry is set, cs rema ins asserted between the tr ansfers when the cs signal for the next transfer is the same as for the current transfer. figure 26-24 shows timing diagram for continuous sck format with continuous selection enabled. figure 26-24. continuous sck timing diagram (cont=1) 26.6.7 interrupt/dma requests the dspi has five conditions that can generate interrupt requests only, and two conditions that can generate interrupt or dma requests. table 26-32 lists the seven conditions. table 26-32. interrupt and dma request conditions condition flag interrupt dma end of transfer queue has been reached (eoq) eoqf x tx fifo is not full tfff x x sck (cpol = 0) cs sck (cpol = 1) master sout t dt t dt = 1 sck master sin sck (cpol = 0) cs sck (cpol = 1) master sout master sin transfer 1 transfer 2
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 636 freescale semiconductor each condition has a flag bit and a request enab le bit. the flag bits are described in the section 26.5.5, dspi status register (dspix_sr) , and the request enable bits are described in the section 26.5.6, dspi dma / interrupt request select and enable register (dspix_rser) . the tx fifo fill flag (tfff) and rx fifo drain flag (rfdf) gene rate interrupt requests or dma requests depending on the tfff_dirs and rfdf_dirs bits in the dspi x _rser. 26.6.7.1 end of queue interrupt request (eoqf) the end of queue request indicates th at the end of a transmit queue is reached. the end of queue request is generated when the eoq bit in the executing spi command is asserted and the eoqf_re bit in the dspi x _rser is set. see the eoq bit description in section 26.5.5, dspi status register (dspix_sr) . see figure 26-16 and figure 26-17 that illustrate when eoqf is set. 26.6.7.2 transmit fifo fill in terrupt or dma request (tfff) the transmit fifo fill request indicates that the tx fifo is not full. the transmit fifo fill request is generated when the number of entries in the tx fifo is less than the maximum number of possible entries, and the tfff_re bit in the dspi x _rser is set. the tfff_ dirs bit in the dspi x _rser selects whether a dma request or an interrupt request is generated. 26.6.7.3 transfer complete interrupt request (tcf) the transfer complete request indicates the end of the transfer of a serial frame. the transfer complete request is generated at the end of each frame transfer when the tcf_re bit is set in the dspi x _rser. see the tcf bit description in section 26.5.5, dspi status register (dspix_sr) . see figure 26-16 , and figure 26-17 that illustrate when tcf is set. 26.6.7.4 transmit fifo underf low interrupt request (tfuf) the transmit fifo unde rflow request indicates that an underflow condition in th e tx fifo has occurred. the transmit underflow condition is detected only fo r dspi modules operating in slave mode and spi configuration. the tfuf bit is set when the tx fifo of a dspi operating in slave mode and spi configuration is empty, and a transfer is initiated from an external spi master. if the tfuf bit is set while the tfuf_re bit in the dspi x _rser is set, an interrupt request is generated. current frame transfer is complete tcf x tx fifo underflow has occurred tfuf x rx fifo is not empty rfdf x x rx fifo overflow occurred rfof x a fifo overrun occurred 1 tfuf ored with rfof x 1 the fifo overrun condition is created by oring the tfuf and rfof flags together. table 26-32. interrupt and dma request conditions (continued) condition flag interrupt dma
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 637 26.6.7.5 receive fifo drain in terrupt or dma request (rfdf) the receive fifo drain reque st indicates that the rx fifo is not empty. the r eceive fifo drain request is generated when the number of entries in the rx fifo is not zero, and the rfdf_re bit in the dspi x _rser is set. the rfdf_dirs bit in the dspi x _rser selects whether a dma request or an interrupt request is generated. 26.6.7.6 receive fifo overfl ow interrupt request (rfof) the receive fifo overflow request in dicates that an overflow condition in the rx fifo has occurred. a receive fifo overflow request is generated when rx fi fo and shift register are full and a transfer is initiated. the rfof_re bit in the dspi x _rser must be set for the inte rrupt request to be generated. depending on the state of the rooe bit in the dspi x _mcr, the data from the tr ansfer that generated the overflow is either ignored or shifted in to the shift re gister. if the rooe bit is set, the incoming data is shifted in to the shift register. if the rooe bit is negated, the incoming data is ignored. 26.6.7.7 fifo overrun request (tfuf) or (rfof) the fifo overrun request indicates th at at least one of th e fifos in the dspi has exceeded its capacity. the fifo overrun request is generated by logically or ing together the rx fifo overflow and tx fifo underflow signals. 26.6.8 power saving features the dspi supports the follow ing power-saving strategies: ? module disable mode?clock gating of non-memory mapped logic ? clock gating of slave interface signals and clock to memory-mapped logic 26.6.8.1 module disable mode module disable mode is a module-specific mode that the dspi can enter to save power. host software can initiate the module disable mode by writ ing a 1 to the mdis bit in the dspi x _mcr. in module disable mode, the dspi is in a dormant state, but the memory mapped registers are still accessible. certain read or write operations have a different affect when the dspi is in the module disa ble mode. reading the rx fifo pop register does not change the state of the rx fifo. likewise, writi ng to the tx fifo push register does not change the state of the tx fifo. cl earing either of the fifos does not have any effect in the module disable mode. changes to the dis_txf a nd dis_rxf fields of the dspi x _mcr does not have any affect in the module disable mode. in the mo dule disable mode, all status bits and register flags in the dspi return the correct values when read, but writing to them has no affect. writing to the dspi x _tcr during module disable mode does not have an effect. interrupt and dma request signals cannot be cleared while in the module disable mode.
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 638 freescale semiconductor 26.6.8.2 slave interface signal gating the dspi module enable signal is used to gate sl ave interface signals such as address, byte enable, read/write, and data. this prevents toggling slave interface signals from consuming power unless the dspi is accessed. 26.7 initialization and application information 26.7.1 how to change queues dspi queues are not part of the dspi module, but the dspi includes features in support of queue management. queues are primarily s upported in spi configuration. this section presents an example of how to change queues for the dspi. 1. the last command word from a queue is execute d. the eoq bit in the command word is set to indicate to the dspi that this is the last entry in the queue. 2. at the end of the tran sfer, corresponding to the command word with eoq set is sampled, the eoq flag (eoqf) in the dspi x _sr is set. 3. the setting of the eoqf flag di sables both serial tran smission and serial rece ption of data, putting the dspi in the stopped state. the txrxs bi t is negated to indicate the stopped state. 4. the edma continues to fill tx fifo until it is full or step 5 occurs. 5. disable dspi dma transfers by disabling the dma enable request for the dma channel assigned to tx fifo and rx fifo. this is done by clea ring the corresponding dma en able request bits in the edma controller. 6. ensure all received data in rx fifo has been transferred to me mory receive queue by reading the rxcnt in dspi x _sr or by checking rfdf in the dspi x _sr after each read operation of the dspi x _popr. 7. modify dma descriptor of tx and rx channels for new queues. 8. flush tx fifo by writing a 1 to the clr_txf bit in the dspi x _mcr register and flush the rx fifo by writing a 1 to the clr_rxf bit in the dspi x _mcr register. 9. clear transfer count eith er by setting ctcnt bit in the command word of the first entry in the new queue or via cpu writing directly to spi_tcnt field in the dspi x _tcr. 10. enable dma channel by enabling the dma enable request for th e dma channel assigned to the dspi tx fifo, and rx fifo by setting th e corresponding dma set enable request bit. 11. enable serial transmissi on and serial reception of data by clearing the eoqf bit. 26.7.2 baud rate settings table 26-33 shows the baud rate that is ge nerated based on the combination of the baud rate prescaler pbr and the baud rate scaler br in the dspi x _ctars. the values are calculated at a 64 mhz system frequency.
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 639 table 26-33. baud rate values baud rate divider prescaler values (dspi_ctar[pbr]) 2357 baud rate scaler values (dspi_ctar[br]) 2 16.0 mhz 10.7 mhz 6.4 mhz 4.57 mhz 4 8 mhz 5.33 mhz 3.2 mhz 2.28 mhz 6 5.33 mhz 3.56 mhz 2.13 mhz 1.52 mhz 8 4 mhz 2.67 mhz 1.60 mhz 1.15 mhz 16 2 mhz 1.33 mhz 800 khz 571 khz 32 1 mhz 670 khz 400 khz 285 khz 64 500 khz 333 khz 200 khz 142 khz 128 250 khz 166 khz 100 khz 71.7 khz 256 125 khz 83.2 khz 50 khz 35.71 khz 512 62.5 khz 41.6 khz 25 khz 17.86 khz 1024 31.2 khz 20.8 khz 12.5 khz 8.96 khz 2048 15.6 khz 10.4 khz 6.25 khz 4.47 khz 4096 7.81 khz 5.21 khz 3.12 khz 2.23 khz 8192 3.90 khz 2.60 khz 1.56 khz 1.11 khz 16384 1.95 khz 1.31 khz 781 hz 558 hz 32768 979 hz 653 hz 390 hz 279 hz
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 640 freescale semiconductor 26.7.3 delay settings table 26-34 shows the values for the delay after transfer (t dt ) that can be generated based on the prescaler values and the scaler values set in the dspi x _ctars. the values calculated assume a 64 mhz system frequency. 26.7.4 calculation of fifo pointer addresses the user has complete visibility of the tx and rx fifo contents th rough the fifo registers, and valid entries can be identified through a memory mapped pointer and a memory mapped counter for each fifo. the pointer to the first-in entry in each fifo is me mory mapped. for the tx fifo the first-in pointer is the transmit next pointer (txnxtpt r). for the rx fifo the first-in pointer is the pop next pointer (popnxtptr). table 26-34. delay values delay prescaler values (dspi_ctar[pdt]) 1357 delay scaler values (dspi_ctar[dt]) 2 31.25 ns 93.75 ns 156.25 ns 218.75 ns 4 62.5 ns 187.5 ns 312.5 ns 437.5 ns 8 125 ns 375 ns 625 ns 875 ns 16 250 ns 750 ns 1.25 s 1.75 s 32 0.5 s 1.5 s 2.5 s 3.5 s 64 1 s 3 s 5 s 7 s 128 2 s 6 s 10 s 14 s 256 4 s 12 s 20 s 28 s 512 8 s 24 s 40 s 56 s 1024 16 s 48 s 80 s 112 s 2048 32 s 96 s 160 s 224 s 4096 64 s 192 s 320 s 448 s 8192 128 s 384 s 640 s 896 s 16384 256 s 768 s 1.28 ms 1.79 ms 32768 512 s 1.54 ms 2.56 ms 3.58 ms 65536 1.02 ms 3.07 ms 5.12 ms 7.17 ms
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 641 see section 26.6.3.4, transmit first in first out (tx fifo) buffering mechanism , and section 26.6.3.5, receive first in first out (rx fifo) buffering mechanism , for details on the fifo operation. the tx fifo is chosen for the illustration, but the concepts carry over to the rx fifo. figure 26-25 illustrates the concept of first-in and last -in fifo entries along with the fifo counter. figure 26-25. tx fifo pointers and counter 26.7.4.1 address calculation for the first-i n entry and last-in en try in the tx fifo the memory address of the first-in entry in th e tx fifo is computed by the following equation: first-in entry address = tx fifo base + 4 (txnxtptr) the memory address of the last-in entry in the tx fifo is computed by the following equation: last-in entry address = txfifo base + 4 [(txctr + txnxtptr ? 1) modulo txfifo depth] where: txfifo base = base a ddress of transmit fifo txctr = transmit fifo counter txnxtptr = transmit next pointer tx fifo depth = transmit fifo depth, implementation specific 26.7.4.2 address calculation for the first-i n entry and last-in en try in the rx fifo the memory address of the first-in entry in th e rx fifo is computed by the following equation: first-in entry address = rxfifo base + 4 (popnxtptr) the memory address of the last-in entry in th e rx fifo is computed by the following equation: last-in entry address = rxfifo base + 4 [(rxctr + popnxtptr ? 1) modulo rxfifo depth] where: rxfifo base = base a ddress of receive fifo entry c entry a (first in) ? 1 entry b entry d (last in) tx fifo base push tx fifo tx fifo counter shift register sout register transmit next data pointer ? ? ? ? + 1 (txnxtptr)
chapter 26 deserial serial peripheral interface (dspi) MPC5606BK microcontroller reference manual, rev. 2 642 freescale semiconductor rxctr = receive fifo counter popnxtptr = pop next pointer rx fifo depth = receive fifo depth, implementation specific
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 643 ??? timers ???
MPC5606BK microcontroller reference manual, rev. 2 644 freescale semiconductor this page is intent ionally left blank.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 645 chapter 27 timers 27.1 introduction this chapter describes the timer modul es implemented on the microcontroller: ? system timer module (stm) ? enhanced modular io subsystem (emios) ? periodic interrupt timer (pit) the microcontroller also has a real time clock / autonomous periodic interrupt (rtc/api) module. the main purpose of this is to provi de a periodic device wakeup source. 27.2 technical overview this section gives a technical overview of each of the timers as well as detailing the pins that can be used to access the timer peripherals if applicable. figure 27-1 details the interaction between the tim ers and the edma, intc, ctu, and adc.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 646 freescale semiconductor figure 27-1. interaction between timers and relevant peripherals
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 647 27.2.1 overview of the stm the stm is a 32-bit free ru nning up-counter clocked by the system cl ock with a configurable 8-bit clock prescaler (divide by 1 to 256). the c ounter is disabled out of reset and must therefore be enabled by software prior to use. the counter value can be read at any time. the stm has four 32-bit compare channels. each cha nnel can generate a unique interrupt on an exact match event with the free running counter. the stm is often used to analyze c ode execution times. by starting the stm and reading the timer before and after a task or function, you can ma ke an accurate measur ement of the time taken in clock cycles to perform the task. the stm can be configured to stop (f reeze) or continue to run in debug mode and is available for use in all operating mode where the system clock is present (not standby or certain stop mode configurations) there are no external pins associated with the stm. 27.2.2 overview of the emios each emios offers a combination of pwm, output capture, and input comp are functions. there are different types of channel implemented and not every channel supports ev ery emios function. the channel functionality also differ s between each em ios module. see section 27.4, enhanced modular io subsystem (emios) , for more details. each channel has its own independent 16-bit counter . to allow synchronization between channels, there are a number of shared counter busses that can be us ed as a common timing refere nce. these counter buses can be used in combination with the individual channel counters to pr ovide advanced features such as centre aligned pwm with dead time insertion. once configured, the emios needs ve ry little cpu intervention. interrupts, edma requests, and ctu trigger requests can be raised base d on emios flag and timeout events. the emios is clocked from the system clock via peripheral clock group 3 (with a maximum permitted clock frequency of 64 mhz). the emios can be used in all modes where the system clock is available (which excludes standby mode and stop mode when the system clock is turned off). the emios has an option to allow the emios counters to fre eze or to continue running in debug mode. the ctu allows an emios event to trigger a si ngle adc conversion via the ctu without any cpu intervention. without the ct u, the emios would have to trigger an interrupt request. the respective isr would then perform a software triggered adc conve rsion. this not only uses cpu resource, but also increases the latency between the emios event and the adc trigger. the emios output pulse width modulation with trigger mode (see section 27.4.4.1.1.12, output pulse width modulation with trigger (opwmt) mode ) allows a customizable trigge r point to be defined at any point in the waveform period. this is extremely useful for led lighting applications where the trigger can be set to a point where the pwm output is high but after the initial inru sh current to the led has occurred. the pwm trigger can then cause the ctu to perfor m a single adc conversion, which in turn measures the operating conditions of the led to ensure it is working within specification. a watchdog feature on
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 648 freescale semiconductor the adc allows channels to be moni tored. if the results fall outside a specific range, an interrupt is triggered. this means that all of the measurement is without cp u intervention if the results are within range. to make it easier to plan wh ich pins to use for the emios, table 27-1 and table 27-2 show the emios channel numbers that are availabl e on each pin. the color shading ma tches the channel configuration diagram in the emios section. table 27-1. emios_0 channel to pin mapping channel pin function channel pin function alt1 alt2 alt3 alt1 alt2 alt3 uc[0] pa [ 0 ] pa [ 1 4 ] uc[16] pe[0] uc[1] pa [ 1 ] pa [ 1 5 ] uc[17] pe[1] uc[2] pa [ 2 ] uc[18] pe[2] uc[3] pa[3], pb[11] pc[8] uc[19] pe[3] uc[4] pa[4], pb[12] uc[20] pe[4] uc[5] pa[5], pb[13] uc[21] pe[5] uc[6] pa[6], pb[14] uc[22] pe[6], pf[5] pe[8] uc[7] pa[7], pb[15] pc[9] uc[23] pe[7], pf[6] pe[9] uc[8] pa [ 8 ] uc[24] pe[11], pg[10] pd[12] uc[9] pa [ 9 ] uc[25] pg[11] pd[13] uc[10] pa[10], pf[0] uc[26] pg[12] pd[14] uc[11] pa[11], pf[1] uc[27] pg[13] pd[15] uc[12] pc[12], pf[2] uc[28] pi[0] pa[12] uc[13] pc[13], pf[3] pa [ 0 ] uc[29] pi[1] pa[13] uc[14] pc[14], pf[4] pa [ 8 ] uc[30] pi[2] pb[0] pb[2] uc[15] pc[15] uc[31] pb[3], pi[3] pb[1] table 27-2. emios_1 channel to pin mapping channel pin function channel pin function alt1 alt2 alt3 alt1 alt2 alt3 uc[0] pg[14] uc[16] pg[7] uc[1] pf[9], pg[15] uc[17] pg[8] ph[15] uc[2] ph[0] pf[10] uc[18] pg[9] pj[4] uc[3] ph[1] pf[11] uc[19] pe[12] uc[4] pf[15], ph[2] uc[20] pe[13] uc[5] ph[3] ph[11] uc[21] pe[14] uc[6] ph[4] uc[22] pe[15] uc[7] ph[5] uc[23] pg[0] uc[8] ph[6] uc[24] pg[1] uc[9] ph[7] uc[25] pf[12] ph[12] uc[10] ph[8] uc[26] pf[13] ph[13] uc[11] pg[2] uc[27] pf[14] ph[14] uc[12] pg[3] uc[28] pi[4] pc[6]
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 649 27.2.3 overview of the pit the pit module consists of 8 periodic interrupt timers (pits) clocked from the system clock. out of reset, the pit is disabled. th ere is a global disable control bit for all of the pit timers. before using the timers, software must clear th e appropriate disabled bit. each of the pit timers are effectively standalone entities and each have th eir own timer and control registers. the pit timers are 32-bit count down timers. to use them, you must first program an initial value into the ldval register. the timer wi ll then start to count down and can be read at any time. once the timer reaches 0x0000_0000, a flag is set and the previous va lue is automatically reloaded into the ldval register and the countdown starts again. the flag even t can be routed to a dedicated intc interrupt if desired. the pit is also used to trigger other events: ? four of the pit channels can be used as an edma trigger ? two pit channels can be used to trigger a ctu adc conversion (single) ? two pit channels (one per adc module) can be us ed to directly trigger injected conversions on the adc the timers can be configured to st op (freeze) or to continue to run in debug mode. the pit is available in all modes where a system clock is generated. there are no external pins associated with the pit. 27.3 system timer module (stm) 27.3.1 introduction 27.3.1.1 overview the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). uc[13] pg[4] uc[29] pi[5] pc[7] uc[14] pg[5] uc[30] pi[6] pg[7] pe[10] uc[15] pg[6] uc[31] pc[4], pi[7] pg[10] table 27-2. emios_1 channel to pin mapping (continued) channel pin function channel pin function alt1 alt2 alt3 alt1 alt2 alt3
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 650 freescale semiconductor 27.3.1.2 features the stm has the following features: ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 27.3.1.3 modes of operation the stm supports two device modes of operation: nor mal and debug. when the st m is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the stm_cr register. if the frz bi t is set, the counter is stopped in debug mode, otherwise it continues to run. 27.3.2 external signal description the stm does not have any external interface signals. 27.3.3 memory map and register definition the stm programming model has fourt een 32-bit registers. the stm regi sters can only be accessed using 32-bit (word) accesses. attempted refe rences using a different size or to a reserved address generates a bus error termination. 27.3.3.1 memory map the stm memory map is shown in table 27-3 . table 27-3. stm memory map base address: 0xfff3_c000 address offset register location 0x0000 stm control register (stm_cr) on page 651 0x0004 stm counter value (stm_cnt) on page 652 0x0008?0x000c reserved 0x0010 stm channel 0 control register (stm_ccr0) on page 652 0x0014 stm channel 0 interrupt register (stm_cir0) on page 653 0x0018 stm channel 0 compare register (stm_cmp0) on page 654 0x001c reserved 0x0020 stm channel 1 control register (stm_ccr1) on page 652 0x0024 stm channel 1 interrupt register (stm_cir1) on page 653 0x0028 stm channel 1 compare register (stm_cmp1) on page 654
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 651 27.3.3.2 register descriptions the following sections detail the individua l registers within the stm programming model. 27.3.3.2.1 stm control register (stm_cr) the stm control register (stm_cr) includes the prescale value, freeze control, and timer enable bits. 0x002c reserved 0x0030 stm channel 2 control register (stm_ccr2) on page 652 0x0034 stm channel 2 interrupt register (stm_cir2) on page 653 0x0038 stm channel 2 compare register (stm_cmp2) on page 654 0x003c reserved 0x0040 stm channel 3 control register (stm_ccr3) on page 652 0x0044 stm channel 3 interrupt register (stm_cir3) on page 653 0x0048 stm channel 3 compare register (stm_cmp3) on page 654 0x004c?0x3fff reserved offset: 0x000 access: read/write 0 1 2 3 4 5 6 7 8 9 101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cps 0 0 00 00 frz ten w reset0000000000000000 figure 27-2. stm control register (stm_cr) table 27-3. stm memory map (continued) base address: 0xfff3_c000 address offset register location
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 652 freescale semiconductor 27.3.3.2.2 stm count register (stm_cnt) the stm count register (stm_cnt) holds the timer count value. 27.3.3.2.3 stm channel cont rol register (stm_ccrn) the stm channel control register (stm_ccrn) has the enable bit for channel n of the timer. table 27-4. stm_cr field descriptions field description cps counter prescaler. selects the clock divide value for the prescaler (1?256). 0x00 = divide system clock by 1 0x01 = divide system clock by 2 ... 0xff = divide system clock by 256 frz freeze. allows the timer counter to be stopped when the device enters debug mode. 0 = stm counter continues to run in debug mode. 1 = stm counter is stopped in debug mode. ten timer counter enabled. 0 = counter is disabled. 1 = counter is enabled. offset: 0x004 access: read/write 012345678910111213141516171819202122232425262728293031 r cnt w reset00000000000000000000000000000000 figure 27-3. stm count register (stm_cnt) table 27-5. stm_cnt field descriptions field description cnt timer count value used as the time base for all chan nels. when enabled, the counter increments at the rate of the system clock divided by the prescale value.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 653 27.3.3.2.4 stm channel interr upt register (stm_cirn) the stm channel interrupt register (stm_cirn) has the interrupt flag for channel n of the timer. offset: 0x10+0x10 n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000 cen w reset0000000000000 0 00 figure 27-4. stm channel control register (stm_ccrn) table 27-6. stm_ccrn field descriptions field description cen channel enable. 0 = the channel is disabled. 1 = the channel is enabled. offset: 0x14+0x10 n access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000000 0 0 0 000cif w w1c reset0000000000000 0 00 figure 27-5. stm channel interrupt register (stm_cirn) table 27-7. stm_cirn field descriptions field description cif channel interrupt flag 0 = no interrupt request. 1 = interrupt request due to a match on the channel.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 654 freescale semiconductor 27.3.3.2.5 stm channel com pare register (stm_cmpn) the stm channel compare regi ster (stm_cmpn) holds the compare value for channel n. 27.3.4 functional description the system timer module (stm) is a 32-bit timer designed to suppor t commonly required system and application software timing func tions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the stm has one 32-bit up counter (stm_cnt) that is used as the time base for all channels. when enabled, the counter increments at the system clock frequency divided by a prescale value. the stm_cr[cps] field sets the divider to any value in the range from 1 to 256. the counter is enabled with the stm_cr[ten] bit. when enabled in normal m ode the counter continuously increments. when enabled in debug mode the coun ter operation is controlled by the stm_cr[frz] bit. when the stm_cr[frz] bit is set, the counter is stopped in debug mode, otherw ise it continues to run in debug mode. the counter rolls over at 0xffff_ffff to 0x0000_0000 with no restrictions at this boundary. the stm has four identical compare channels. e ach channel includes a channel control register (stm_ccrn), a channel interrupt re gister (stm_cirn) and a channe l compare register (stm_cmpn). the channel is enabled by setting the stm_ccrn[cen ] bit. when enabled, the channel will set the stm_cir[cif] bit and generate an interrupt request when the channel compare register matches the timer counter. the interrupt request is cl eared by writing a 1 to the stm_cirn[cif] bit. a write of 0 to the stm_cirn[cif] bit has no effect. note stm counter does not advance when the system clock is stopped. offset: 0x18+0x10 n access: read/write 012345678910111213141516171819202122232425262728293031 r cmp w reset00000000000000000000000000000000 figure 27-6. stm channel compare register (stm_cmpn) table 27-8. stm_cmpn field descriptions field description cmp compare value for channel n. if the stm_ccrn[cen] bit is set and the stm_cmpn register matches the stm_cnt register, a channel interrupt request is generated and the stm_cirn[cif] bit is set.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 655 27.4 enhanced modular io subsystem (emios) 27.4.1 introduction 27.4.1.1 overview of the emios module the emios provides functionality to generate or measure time events. the emios uses timer channels that are reduced versions of th e unified channel (uc) module used on mpc555x devices. each channel provides a subset of the functionalit y available in the unified channel, at a resolution of 16 bits, and provides a user interface that is consiste nt with previous emios implementations. 27.4.1.2 features of the emios module ? two emios blocks with 32 channels each ? all 64 channels with opwmt, which can be connected to the ctu ? both emios blocks can be synchronized ? one global prescaler ? 16-bit data registers ? 10 16-bit wide counter buses ? counter buses b, c, d, and e can be driven by unified channel 0, 8, 16, and 24, respectively ? counter bus a is driven by the unified channel 23 ? several channels have their own time base, alternative to the counter buses ? shared timebases through the counter buses ? synchronization among timebases ? control and status bits grouped in a single register ? shadow flag register ? state of the uc can be frozen for debug purposes ? motor control capability 27.4.1.3 modes of operation the unified channels can be configured to operate in the following modes: ? general purpose input/output ? single action input capture ? single action output compare ? input pulse width measurement ? input period measurement ? double action output compare ? modulus counter ? modulus counter buffered
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 656 freescale semiconductor ? output pulse width and frequency modulation buffered ? output pulse width modulation buffered ? output pulse width modulation with trigger ? center aligned output pulse width modulation buffered these modes are described in section 27.4.4.1.1, uc modes of operation . each channel can have a specific set of mode s implemented, according to device requirements. if an unimplemented mode (reserved) is selected, the results are unpredic table such as writing a reserved value to mode[0:6] in section 27.4.3.2.8, emios uc contro l register (emiosc[n]) . 27.4.1.4 channel implementation figure 27-7 shows the channel configur ation of the emios blocks.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 657 key daoc dual action output compare gpio general purpose input output ipm input period measurement ipwm input pulse width measurement mc modulus counter mcb buffered modulus counter opwmb buffered output pulse width modulation opwmt buffered output pulse width modulation with trigger opwfmb buffered output pulse width and frequency modulation opwmcb center aligned output pwm buffered with dead time saic single action input capture saoc single action output compare ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ch16 ch17 ch18 ch19 ch24 ch20 ch21 ch22 ch23 global prescaler 8-bit counter counter bus_b counter bus_a counter bus_c counter bus_d counter bus_e bus clk channel functionality type x type y ?mc, mcb ?opwmt ?opwmb ?opwfmb ? saic, saoc ?gpio type h ?opwmt ?opwmb ? ipwm, ipm ?daoc ? saic, saoc ?gpio ?opwmt ?opwmb ? saic, saoc ?gpio emios_0 ch0 ch1 ch2 ch3 ch4 ch5 ch6 ch7 ch8 ch9 ch10 ch11 ch12 ch13 ch14 ch15 ch16 ch17 ch18 ch19 ch24 ch25 ch26 ch27 ch20 ch21 ch22 ch23 global prescaler 8-bit counter counter bus_b counter bus_a counter bus_c counter bus_d counter bus_e bus clk emios_1 type g ?mcb ?opwmt ?opwmb ?opwfmb ?opwmcb ? ipwm, ipm ?daoc ? saic, saoc ?gpio ch28 ch29 ch30 ch31 ch25 ch26 ch27 ch28 ch29 ch30 ch31
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 658 freescale semiconductor figure 27-7. channel configuration 27.4.1.4.1 channel mode selection channel modes are selected using th e mode selection bits mode[0:6] in the emios uc control register (emiosc[n]). table 27-21 provides the specific mode selection settings for the emios implementation on this device. 27.4.2 external signal description for information on emios external signa ls on this device, please refer to chapter 4, signal description . 27.4.3 memory map and register description 27.4.3.1 memory maps the overall address map or ganization is shown in table 27-9 . 27.4.3.1.1 unified channel memory map table 27-9. emios memory map base addresses: 0xc3fa_0000 (emios_0) 0xc3fa_4000 (emios_1) address offset description location 0x000?0x003 emios module configuration register (emiosmcr) on page 659 0x004?0x007 emios global flag (emiosgflag) register on page 660 0x008?0x00b emios output update disable (emiosoudis) register on page 661 0x00c?0x00f emios disable channel (emiosucdis) register on page 662 0x010?0x01f reserved ? 0x020?0x11f channel [0] to channel [7] ? 0x120?0x21f channel [8] to channel [15] ? 0x220?0x31f channel [16] to channel [23] ? 0x320?0x41f channel [24] to channel [31] 0x420?0xfff reserved
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 659 addresses of unified channe l registers are specified as offsets from the channel? s base address; otherwise the emios base address is used as reference. table 27-10 describes the unified channel memory map. 27.4.3.2 register description all control registers are 32 bits wide. data registers and count er registers are 16 bits wide. 27.4.3.2.1 emios module config uration register (emiosmcr) the emiosmcr contains global co ntrol bits for the emios block. table 27-10. unified channel memory map uc[n] base address description location 0x00 emios uc a register (emiosa[n]) on page 663 0x04 emios uc b register (emiosb[n]) on page 663 0x08 emios uc counter re gister (emioscnt[n]) on page 664 0x0c emios uc control re gister (emiosc[n]) on page 665 0x10 emios uc status register (emioss[n]) on page 669 0x14 emios uc alternate a register (emiosalta[n]) on page 670 0x18?0x1f reserved ? address: emios base address +0x00 0123456789101112131415 r0 mdis frz gtbe 0 gpren 0000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r gpre 00000000 w reset0000000000000000 figure 27-8. emios module configuration register (emiosmcr) table 27-11. emiosmcr field descriptions field description mdis module disable puts the emios in low power mode. the mdis bit is used to stop the clock of the block, except the access to registers emiosmcr, emiosoudis, and emiosucdis. 1 = enter low power mode 0 = clock is running
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 660 freescale semiconductor 27.4.3.2.2 emios global fla g (emiosgflag) register the emiosgflag is a read-only regi ster that groups the flag bits (f[31:0]) from all channels. this organization improves interrupt handling on simpler de vices. each bit relates to one channel. for unified channels these bits are mirrors of the flag bits in the emioss[n] register. frz freeze enables the emios to freeze the registers of the unified channels when debug mode is requested at mcu level. each unified channel should have fren bit set in order to enter freeze state. while in freeze state, the emios continues to operate to allow the mcu access to the unified channels registers. the unified channel will remain frozen un til the frz bit is written to 0 or the mcu exits debug mode or the unified channel fren bit is cleared. 1 = stops unified channels operation when in debug mode and the fren bit is set in the emiosc[n] register 0 = exit freeze state gtbe global time base enable the gtbe bit is used to export a global time base enable from the module and provide a method to start time bases of several blocks simultaneously. 1 = global time base enable out signal asserted 0 = global time base enable out signal negated note: the global time base enable input pin controls the internal counters. when asserted, internal counters are enabled. when negated, internal counters disabled. gpren global prescaler enable the gpren bit enables the prescaler counter. 1 = prescaler enabled 0 = prescaler disabled (no clock) and prescaler counter is cleared gpre global prescaler the gpre bits select the clock divider value for the global prescaler, as shown in table 27-12 . table 27-12. global prescaler clock divider gpre divide ratio 00000000 1 00000001 2 00000010 3 00000011 4 . . . . . . . . 11111110 255 11111111 256 table 27-11. emiosmcr field descriptions (continued) field description
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 661 27.4.3.2.3 emios output update disable (emiosoudis) register address: emios base address +0x04 0123456789101112131415 r f31 f30 f29 f28 f27 f26 f25 f24 f23 f22 f21 f20 f19 f18 f17 f16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rf15f14f13f12f11f10f9f8f7f6f5f4f3f2f1f0 w reset0000000000000000 figure 27-9. emios global fla g (emiosgflag) register table 27-13. emiosgflag field descriptions field description fn channel [n] flag bit address: emios base address +0x08 0123456789101112131415 r ou31 ou30 ou29 ou28 ou27 ou26 ou25 ou24 ou23 ou22 ou21 ou20 ou19 ou18 ou17 ou16 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ou15 ou14 ou13 ou12 ou11 ou10 ou9 ou8 ou7 ou6 ou5 ou4 ou3 ou2 ou1 ou0 w reset0000000000000000 figure 27-10. emios output update disable (emiosoudis) register
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 662 freescale semiconductor 27.4.3.2.4 emios disable ch annel (emiosucdis) register table 27-14. emiosoudis field descriptions field description oun channel [n] output update disable bit when running mc, mcb or an output mode, values are written to registers a2 and b2. ou[n] bits are used to disable transfers from registers a2 to a1 and b2 to b1. each bit controls one channel. 1 = transfers disabled 0 = transfer enabled. depending on the operation mode, transfer may occur immediately or in the next period. unless stated otherwise, transfer occurs immediately. address: emios base address +0x0c 0123456789101112131415 r chdis31 chdis30 chdis29 chdis28 chdis27 chdis26 chdis25 chdis24 chdis23 chdis22 chdis21 chdis20 chdis19 chdis18 chdis17 chdis16 w reset 000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chdis15 chdis14 chdis13 chdis12 chdis11 chdis10 chdis9 chdis8 chdis7 chdis6 chdis5 chdis4 chdis3 chdis2 chdis1 chdis0 w reset0000000000000000 figure 27-11. emios enable channel (emiosucdis) register table 27-15. emiosucdis field descriptions field description chdisn enable channel [n] bit the chdis[n] bit is used to disable each of the channels by stopping its respective clock. 1 = channel [n] disabled 0 = channel [n] enabled
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 663 27.4.3.2.5 emios uc a register (emiosa[n]) depending on the mode of operation, in ternal registers a1 or a2, used for matches and captures, can be assigned to address emiosa[n]. both a1 and a2 are cleared by reset. figure 27-16 summarizes the emiosa[n] writing and reading accesses for all operation mode s. for more information see section 27.4.4.1.1, uc modes of operation . 27.4.3.2.6 emios uc b register (emiosb[n]) depending on the mode of operation, internal registers b1 or b2 can be assigned to address emiosb[n]. both b1 and b2 are cleared by reset. table 27-16 summarizes the emiosb[n] writing and reading accesses for all operation modes. for more information see section 27.4.4.1.1, uc mo des of operation . depending on the channel configuration, it may have emiosb register or not. this means that, if at least one mode that requires the register is implemented, then the register is present; otherwis e it is absent. address: uc[n] base address + 0x00 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r a w reset0000000000000000 figure 27-12. emios uc a register (emiosa[n]) address: uc[n] base address + 0x04 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r b w reset0000000000000000 figure 27-13. emios uc b register (emiosb[n])
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 664 freescale semiconductor 27.4.3.2.7 emios uc counter register (emioscnt[n]) the emioscnt[n] register contains th e value of the internal counter. when gpio mode is selected or the channel is frozen, the emioscnt[n] re gister is read/write. for all others modes, the emioscnt[n] is a read-only register. when entering some operation modes, this register is automatically cleared (refer to section 27.4.4.1.1, uc modes of operation , for details). depending on the channel configuration it may have an internal counter or not. it means that if at least one mode that requires the counter is implemented, then the counter is present; otherwise it is absent. table 27-16. emiosa[n], emiosb[n] and emiosalta[n] values assignment operation mode register access write read write read alt write alt read gpio a1, a2 a1 b1,b2 b1 a2 a2 saic 1 ?a2b2b2? ? saoc 1 1 in these modes, the register emiosb[n] is not used, but b2 can be accessed. a2 a1 b2 b2 ? ? ipwm ? a2 ? b1 ? ? ipm ? a2 ? b1 ? ? daoc a2 a1 b2 b1 ? ? mc 1 a2 a1 b2 b2 ? ? opwmt a1a1b2b1a2a2 mcb 1 a2 a1 b2 b2 ? ? opwfmb a2 a1 b2 b1 ? ? opwmcb a2 a1 b2 b1 ? ? opwmb a2a1b2b1 ? ? address: uc[n] base address + 0x08 0123456789101112131415 r0000000000000000 w 1 1 in gpio mode or freeze action, this register is writable. reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rc w 1 reset0000000000000000 figure 27-14. emios uc counter register (emioscnt[n])
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 665 channels of type x and g have the internal counter en abled, so their timebase can be selected by channel?s bsl[1:0]=11:emios_a?channels 0 to 8, 16, 23, a nd 24, emios_b?channels 0, 8, 16, 23, and 24. other channels from the above list don't have internal counters. 27.4.3.2.8 emios uc contro l register (emiosc[n]) the control register gathers bits reflecting the stat us of the uc input/output signals and the overflow condition of the internal counter, as we ll as several read/write control bits. address: uc[n] base address + 0x0c 0123456789101112131415 r fren odis odissl ucpre ucpren dma 0 if fck fen 0 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000 bsl edsel edpol mode w forcma forcmb reset0000000000000000 figure 27-15. emios uc control register (emiosc[n]) table 27-17. emiosc[n] field descriptions field description fren freeze enable bit the fren bit, if set and validated by frz bit in emiosmcr register allows the channel to enter freeze state, freezing all registers values when in debug mode and allowing the mcu to perform debug functions. 1 = freeze uc registers values 0 = normal operation odis output disable this bit allows disabling the output pin when runni ng any of the output modes with the exception of gpio mode. 1 = if the selected output disable input signal is asserted, the output pin goes to edpol for opwfmb and opwmb modes and to the complement of edpol for other output modes, but the unified channel continues to operate normally (that is, it continues to produce flag and matches). when the selected output disable input signal is negated, the output pin operates normally. 0 = the output pin operates normally. odissl output disable select this field selects one of the four out put disable input signals, as follows: 00 = output disable input 0 01 = output disable input 1 10 = output disable input 2 11 = output disable input 3
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 666 freescale semiconductor ucpre prescaler bits the ucpre bits select the clock divider value fo r the internal prescaler of unified channel, as shown in ta b l e 2 7 - 1 8 . ucpren prescaler enable bit the ucpren bit enables the prescaler counter. 1 = prescaler enabled 0 = prescaler disabled (no clock) dma direct memory access bit the dma bit selects if the flag generation will be used as an interrupt request, as a dma request or as a ctu trigger. the choice between a dma re quest or a ctu trigger is determined by the value of bit tm in the register ctu_evtcfgrx (refer to chapter 29, cross triggering unit (ctu) ). 1 = flag/overrun assigned to dma request or ctu trigger 0 = flag/overrun assigned to interrupt request if input filter the if field controls the programma ble input filter, selecting the mi nimum input pulse width that can pass through the filter, as shown in ta b l e 2 7 - 1 9 . for output modes, these bits have no meaning. fck filter clock select bit the fck bit selects the clock source for the programmable input filter. 1 = main clock 0 = prescaled clock fen flag enable bit the fen bit allows the unified channel flag bit to generate an interrupt signal or a dma request signal or a ctu trigger signal (the type of si gnal to be generated is defined by the dma bit). 1 = enable (flag will generate an interrupt request or dma request or a ctu trigger) 0 = disable (flag does not generate an interrupt request or dma request or a ctu trigger) forcma force match a bit for output modes, the forcma bit is equivalent to a successful comparison on comparator a (except that the flag bit is not set). this bit is cleared by reset and is always read as zero. this bit is valid for every output operation mode that us es comparator a, othe rwise it has no effect. 1 = force a match at comparator a 0 = has no effect note: for input modes, the forcma bit is not used and writing to it has no effect. forcmb force match b bit for output modes, the forcmb bit is equivalent to a successful comparison on comparator b (except that the flag bit is not set). this bit is cleared by reset and is always read as zero. this bit is valid for every output operation mode that us es comparator b, otherwise it has no effect. 1 = force a match at comparator b 0 = has not effect note: for input modes, the forcmb bit is not used and writing to it has no effect. bsl bus select the bsl field is used to select either one of the counter buses or the internal counter to be used by the unified channel. refer to table 27-20 for details. table 27-17. emiosc[n] field descriptions (continued) field description
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 667 edsel edge selection bit for input modes, the edsel bit selects whether the internal counter is triggered by both edges of a pulse or just by a single edge as defined by the edpol bit. when not shown in the mode of operation description, this bit has no effect. 1 = both edges triggering 0 = single edge triggering defined by the edpol bit for gpio in mode, the edsel bit selects if a flag can be generated. 1 = no flag is generated 0 = a flag is generated as defined by the edpol bit for saoc mode, the edsel bit selects the behavior of the output flip-flop at each match. 1 = the output flip-flop is toggled 0 = the edpol value is transferred to the output flip-flop edpol edge polarity bit for input modes, the edpol bit asserts which edge triggers either the internal counter or an input capture or a flag. when not shown in the mode of operation description, this bit has no effect. 1 = trigger on a rising edge 0 = trigger on a falling edge for output modes, the edpol bit is used to select the logic level on the output pin. 1 = a match on comparator a sets the output flip -flop, while a match on comparator b clears it 0 = a match on comparator a clears the output f lip-flop, while a match on comparator b sets it mode mode selection the mode field selects the mode of operation of the unified channel, as shown in table 27-21 . note: if a reserved value is written to mode the results are unpredictable. table 27-18. uc internal prescaler clock divider ucpre divide ratio 00 1 01 2 10 3 11 4 table 27-19. uc input filter bits if 1 minimum input pulse width [flt_clk periods] 0000 bypassed 2 0001 02 0010 04 0100 08 1000 16 all others reserved table 27-17. emiosc[n] field descriptions (continued) field description
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 668 freescale semiconductor 1 filter latency is 3 clock edges. 2 the input signal is synchronized before arriving to the digital filter. table 27-20. uc bsl bits bsl selected bus 00 all channels: counter bus[a] 01 channels 0 to 7: counter bus[b] channels 8 to 15: counter bus[c] channels 16 to 23: counter bus[d] channels 24 to 27: counter bus[e] 10 reserved 11 all channels: internal counter table 27-21. channel mode selection mode 1 mode of operation 0000000 general purpose inpu t/output mode (input) 0000001 general purpose inpu t/output mode (output) 0000010 single action input capture 0000011 single action output compare 0000100 input pulse width measurement 0000101 input period measurement 0000110 double action output compare (with flag set on b match) 0000111 double action output com pare (with flag set on both match) 0001000 ? 0001111 reserved 001000b modulus counter (up counter with clear on match start) 001001b modulus counter (up counter with clear on match end) 00101bb modulus counter (up/down counter) 0011000 ? 0100101 reserved 0100110 output pulse width modulation with trigger 0100111 ? 1001111 reserved 101000b modulus counter buffered (up counter) 101001b reserved 10101bb modulus counter buffered (up/down counter) 10110b0 output pulse width and frequency modulation buffered 10110b1 reserved 10111b0 center aligned output pulse width modulati on buffered (with trailing edge dead time) 10111b1 center aligned output pulse width modulati on buffered (with leading edge dead time)
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 669 27.4.3.2.9 emios uc stat us register (emioss[n]) 11000b0 output pulse width modulation buffered 1100001 ? 1111111 reserved 1 b = adjust parameters for the mode of operation. refer to section 27.4.4.1.1, uc modes of operation for details. address: uc[n] base address + 0x10 0123456789101112131415 rovr000000000000000 ww1c reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ovfl 000000000000ucin ucout flag ww1c w1c reset0000000000000000 figure 27-16. emios uc status register (emioss[n]) table 27-22. emioss[n] field descriptions field description ovr overrun bit the ovr bit indicates that flag generation occurred when the flag bit was already set. 1 = overrun has occurred 0 = overrun has not occurred ovfl overflow bit the ovfl bit indicates that an overflow has occurred in the internal counter. ovfl must be cleared by software writing a 1 to the ovflc bit. 1 = an overflow had occurred 0 = no overflow ucin unified channel input pin bit the ucin bit reflects the input pin state after being filtered and synchronized. ucout ucout ? unified channel output pin bit the ucout bit reflects the output pin state. flag flag bit the flag bit is set when an input capture or a match event in the comparators occurred. 1 = flag set event has occurred 0 = flag cleared note: when dma bit is set, the flag bit can be cleared by the dma controller or the ctu. table 27-21. channel mode selection (continued) mode 1 mode of operation
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 670 freescale semiconductor 27.4.3.2.10 emios uc alternat e a register (emiosalta[n]) the emiosalta[n] register provides an alternate address to access a2 channel registers in restricted modes (gpio, opwmt) only. if em iosa[n] register is used along with emiosalta[n], both a1 and a2 registers can be accessed in these modes. figure 27-16 summarizes the emiosalta[n] writing and reading accesses for all opera tion modes. please, see section 27.4.4.1.1.1, general purpose input/output (gpio) mode , section 27.4.4.1.1.12, output pulse width modul ation with trigger (opwmt) mode for a more detailed description of th e use of emiosalta[n] register. 27.4.4 functional description the four types of channels of the emios (types x, y, g, and h) can operate in the modes as listed in figure 27-7 . the emios provides inde pendently operating unified channels (uc) that can be configured and accessed by a host mcu. as many as three time bases 1 can be shared by the channels through five counter buses 2 and each unified channel can generate its own time base 3 . the emios block is reset at positive edge of the clock (synchronous re set). all registers are cleared on reset. 27.4.4.1 unified channel (uc) each unified channel consists of: ? counter bus selector, which selects the time base to be used by the channel for all timing functions ? a programmable clock prescaler address: uc[n] base address + 0x14 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r alta w reset0000000000000000 figure 27-17. emios uc alternate a register (emiosalta[n]) 1. time bases can be supplied by: a) channel 23 to all unified channels b) channel 0 to channels 0 to 7, by channel 8 to channels 8 to 15, by channel 16 to channels 16 to 23, by channel 24 to channel s 24 to 31 c) channel's internal counter when available. 2. internal emios architecture have one global counter bus a and fo ur local counter buses b, c, d, and e, that distribute the ti me bases described in note 1 (a) and (b). 3. channels of type x and g have the internal counter enabled, so their timebase can be selected by channel's bsl[1:0]=11: emios_a?channels 0 to 8, 16, 23, and 24 emios_b?channels 0, 8, 16, 23, and 24.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 671 ? two double buffered data register s a and b that allow as many as two input capture and/or output compare events to occur before software intervention is needed. ? two comparators (equal on ly) a and b, which compare the select ed counter bus with the value in the data registers ? internal counter, which can be used as a local time base or to count input events ? programmable input filter, which ensures that only valid pin transitions are received by channel ? programmable input edge de tector, which detects the ri sing, falling, or either edges ? an output flip-flop, which holds the logic level to be applied to the output pin ? emios status and control register 27.4.4.1.1 uc m odes of operation the mode of operation of the unified channel is dete rmined by the mode select bits mode[0:6] in the emios uc control register (emiosc[n]) (see figure 27-15 for details). as the internal counter emioscnt[n] continues to run in all modes (excep t for gpio mode), it is possible to use this as a time base if the re source is not used in the current mode. in order to provide smooth waveform generation even if a and b registers are ch anged on the fly, it is available the mcb, opwfmb, opwm b, and opwmcb modes. in thes e modes a and b registers are double buffered. 27.4.4.1.1.1 general purpose input/output (gpio) mode in gpio mode, all input capture and output compare functions of the uc are disabled, the internal counter (emioscnt[n] register) is cleared a nd disabled. all control bits remain accessible. in order to prepare the uc for a new operation mode, writing to register s emiosa[n] or emiosb[n] stores the same value in registers a1/a2 or b1/b2, respectively. writing to register emiosalta[n] stores a value only in register a2. mode[6] bit selects between input (mode[6] = 0) and output (mode[6] = 1) modes. it is required that when changing m ode[0:6], the application software goes to gpio mode first in order to reset the uc?s internal functions properly. failure to do this could lead to invalid and unexpected output compare or input capture results or the flags being set incorrectly. in gpio input mode (mode[0:6] = 0000000), the flag generation is de termined according to edpol and edsel bits, and the input pin status ca n be determined by reading the ucin bit. in gpio output mode (mode[0:6] = 0000001), the unifie d channel is used as a single output port pin, and the value of the edpol bit is permanen tly transferred to the output flip-flop. 27.4.4.1.1.2 single action in put capture (saic) mode in saic mode (mode[0:6] = 0000010), when a triggering event occurs on the input pin, the value on the selected time base is captured into register a2. the flag bit is set along with the capture event to indicate that an input capture has occurred. register emiosa[n ] returns the value of register a2. as soon as the saic mode is entered comin g out from gpio mode the channel is re ady to capture events. the events are
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 672 freescale semiconductor captured as soon as they occur thus reading register a always returns the value of the latest captured event. subsequent captures are enabled with no need of further reads from em iosa[n] register. the flag is set at any time a new event is captured. the input capture is triggered by a ri sing, falling or either edges in th e input pin, as c onfigured by edpol and edsel bits in emiosc[n] register. figure 27-18 and figure 27-19 show how the unified channel can be used for input capture. figure 27-18. single action input captur e with rising edge triggering example figure 27-19. single action input capture with both edges triggering example 27.4.4.1.1.3 single action ou tput compare (saoc) mode in saoc mode (mode[0:6] = 0000011) a match value is loaded in register a2, and then immediately transferred to register a1 to be compared with the selected time ba se. when a match occurs, the edsel bit selects whether the output flip-fl op is toggled or the value in edpo l is transferred to it. along with the match the flag bit is set to indicate that the out put compare match has occurr ed. writing to register emiosa[n] stores the value in regist er a2 and reading to re gister emiosa[n] returns the value of register a1. an output compare match can be simulated in so ftware by setting the forcma bit in emiosc[n] register. in this case, the flag bit is not set. when saoc mode is entered coming out from gpio mo de the output flip-flop is set to the complement of the edpol bit in the emiosc[n] register. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 flag pin/register a2 (captured) value 2 0xxxxxxx 0x001000 0x001250 0x0016a0 input signal 1 edge detect edge detect edge detect notes: 1. after input filter 2. emiosa[n] ? a2 edsel = 0 edpol = 1 selected counter bus 0x001000 0x001102 flag set event a2 (captured) value 2 0xxxxxxx 0x001000 input signal 1 edge detect notes: 1. afte r input filter 2. emiosa[n] ? a2 0x001103 0x001108 0x001104 0x001105 0x001106 0x001107 0x001001 flag pin/register edge detect flag clear edge detect 0x001103 0x001108 edsel = 1 edpol = x
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 673 counter bus can be either internal or extern al and is selected through bits bsl[0:1]. figure 27-20 and figure 27-21 show how the unified channel can be used to perform a single output compare with edpol value being transferred to the output flip-flop and toggli ng the output flip-flop at each match, respectively. note that once in saoc m ode the matches are enabled thus the desired match value on register a1 must be written before the mode is entered. a1 register can be updated at any time, thus modifying the match value that will reflect in the out put signal generated by th e channel. subsequent matches are enabled with no need of further writes to emiosa[n] register. the flag is set at the same time a match occurs (see figure 27-22 ). note the channel internal counter in sa oc mode is free-running. it starts counting as soon as the saoc mode is entered. figure 27-20. saoc example with edpol value being transferred to the output flip-flop figure 27-21. saoc example toggling the output flip-flop selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 output flip-flop update to a1 a1 value 1 0xxxxxxx 0x001000 flag pin/register 0x001000 0x001000 0x001000 a1 match a1 match a1 match notes: 1. emiosa[n] = a2 edsel = 0 edpol = 1 a2 = a1 according to ou[n] bit selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 0x001000 a1 value 1 0xxxxxxx 0x001000 output flip-flop update to a1 flag pin/register a1 match a1 match a1 match 0x001000 0x001000 0x001000 notes: 1. emiosa[n] = a2 edsel = 1 edpol = x a2 = a1 according to ou[n] bit
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 674 freescale semiconductor figure 27-22. saoc example with flag behavior 27.4.4.1.1.4 input pulse widt h measurement (ipwm) mode the ipwm mode (mode[0:6] = 0000100) al lows the measurement of the wi dth of a positiv e or negative pulse by capturing the leadi ng edge on register b1 and the trailing edge on register a2. successive captures are done on consecutive edges of opposite polarity. the leading edge sensit ivity (that is, pul se polarity) is selected by edpol bit in the em iosc[n] register. registers emiosa[n] and emiosb[n] return the values in register a2 and b1, respectively. the capture function of register a2 remains disabled until the first leading edge triggers the first input capture on register b2. when this leading edge is det ected, the count value of th e selected time base is latched into register b2; the flag bit is not set. when the trailing edge is detected, the count value of the selected time base is latched into register a2 and, at the same time, the flag bi t is set and the content of register b2 is transferred to re gister b1 and to register a1. if subsequent input capture events occur while the corresponding flag bit is set, registers a2, b1, and a1 will be updated with the latest captured values and the flag will remain set. registers emiosa[n] and emiosb[n] return the value in registers a2 and b1, respectively. in order to guarantee coherent access, reading em iosa[n] forces b1 be updated with the content of register a1. at the same time tran sfers between b2 and b1 are disabled until the next r ead of emiosb[n] register. reading emiosb[n] register forces b1 be updated with a1 register content and reenables transfers from b2 to b1, to take effect at the next trailing edge capture. transfer s from b2 to a1 are not blocked at any time. the input pulse width is calculated by subtracting the value in b1 from a2. figure 27-23 shows how the unified channel can be used for input pulse width measurement. selected counter bus 0x0 0x2 flag set event a2 value 1 0x1 output flip-flop note: 1. emiosa[n] ? a2 0x0 0x2 0x1 0x2 0x0 0x1 0x1 flag pin/register flag clear edsel = 1 system clock a1 match edpol = x
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 675 figure 27-23. input pulse wi dth measurement example figure 27-24 shows the a1 and b1 updates when emiosa[n] and emiosb[n] register reads occur. note that a1 register has always coherent data related to a2 register. note also that when emiosa[n] read is performed b1 register is loaded with a1 register content. this guarantee that the data in register b1 has always the coherent data related to the last emiosa [n] read. the b1 register updates remains locked until emiosb[n] read occurs. if emiosa[n] read is performed b1 is updated w ith a1 register content even if b1 update is locked by a prev ious emiosa[n] read operation. figure 27-24. b1 and a1 updates at emiosa[n] and emiosb[n] reads reading emiosa[n] followed by emiosb[n] always pr ovides coherent data. if not coherent data is required for any reason, the sequence of reads should be inverted, therefore em iosb[n] should be read prior to emiosa[n] register. note that even in th is case b1 register update s will be blocked after emiosa[n] read, thus a second emiosb[n] is requi red in order to release b1 register updates. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 b2(captured) value b1 value 3 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001100 0x001525 0xxxxxxx 0x001000 0x001250 input signal 1 babab 1. after input filter notes: flag pin/register 2. emiosa[n] = a2 3. emiosb[n] = b1 edpol = 1 a1 value 3 0xxxxxxx 0x001000 0x001250 selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 b2(captured) value b1 value 3 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001100 0x001525 0xxxxxxx 0x001000 input signal 1 babab 1. after input filter notes: flag pin/register 2. emiosa[n] = a2 edpol = 1 a1 value 3 0xxxxxxx 0x001000 0x001250 0x001000 0x001250 read emiosa[n] read emiosb[n] 3. emiosb[n] = b1
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 676 freescale semiconductor 27.4.4.1.1.5 input period measurement (ipm) mode the ipm mode (mode[0:6] = 0000101) allows the measurement of th e period of an input signal by capturing two consecutive ri sing edges or two consecutive falling e dges. successive in put captures are done on consecutive edges of the same polarity. the edge polarity is defined by the edpol bit in the emiosc[n] register. when the first edge of selected polarity is detected, th e selected time base is latched into the registers a2 and b2, and the data previously held in register b2 is transferred to re gister b1. on this first capture the flag line is not set, and the values in registers b1 is meaningless. on the second and subsequent captures, the flag line is set and data in regist er b2 is transferred to register b1. when the second edge of the same polarity is detecte d, the counter bus value is latched into registers a2 and b2, the data previously held in register b2 is tr ansferred to data register b1 and to register a1. the flag bit is set to indicate the star t and end points of a co mplete period have been captured. this sequence of events is repeated for each subsequent capture. registers emiosa[n] and emiosb[n] return the values in register a2 and b1, respectively. in order to allow coherent data, reading emiosa[n] fo rces a1 content be transferred to b1 register and disables transfers between b2 and b 1. these transfers are disabled until the next read of the emiosb[n] register. reading emiosb[n] register forces a1 conten t to be transferred to b1 and reenables transfers from b2 to b1, to take eff ect at the next edge capture. the input pulse period is calculated by subtracting the value in b1 from a2. figure 27-25 shows how the unified channel can be used for input period measurement. figure 27-25. input period measurement example figure 27-26 describes the a1 and b1 regi ster updates when emiosa[n] and emiosb[n] read operations are performed. when emiosa[n] read occurs the cont ent of a1 is transferred to b1 thus providing coherent data in a2 and b1 regist ers. transfers from b2 to b1 are th en blocked until em iosb[n] is read. after emiosb[n] is read, register a1 content is transferred to register b1 and the transfers from b2 to b1 are reenabled to occur at the transfer edges, which is the leading edge in the figure 27-26 example. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 a1 value b2 (captured) value 0xxxxxxx 0x001000 0x001250 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001000 0x001250 0x0016a0 input signal 1 edpol = 1 flag pin register notes: 1. after input filter 2. emiosa[n] = a2 3. emiosb[n] = b1 a a a b1 value 3 0xxxxxxx 0x001000 0x001250
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 677 figure 27-26. a1 and b1 updates at emiosa[n] and emiosb[n] reads 27.4.4.1.1.6 double action ou tput compare (daoc) mode in the daoc mode, the leading and trailing edges of the variable pulse widt h output are generated by matches occurring on comparators a and b. there is no restriction concerning th e order in which a and b matches occur. when the daoc mode is entered, coming out from gp io mode both comparators are disabled and the output flip-flop is set to the complement of the edpol bit in the emiosc[n] register. data written to a2 and b2 are transf erred to a1 and b1, resp ectively, on the next syst em clock cycle if bit ou[n] of the emiosoudis register is cleared (see figure 27-29 ). the transfer is bl ocked if bit ou[n] is set. comparator a is enabled only after the transfer to a1 register occurs and is disabled on the next a match. comparator b is enabled only af ter the transfer to b1 register oc curs and is disabl ed on the next b match. comparators a and b are enab led and disabled independently. the output flip-flop is set to the value of edpol when a match occurs on comparator a and to the complement of edpol when a match occurs on comparator b. mode[6] controls if the flag is set on both ma tches (mode[0:6] = 0000111) or just on the b match (mode[0:6] = 0000110). flag bit asserti on depends on comparator enabling. if subsequent enabled output compares occur on registers a1 and b1, pulse s will continue to be generated, regardless of the state of the flag bit. at any time, the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a comparison event in comparator a or b, respectively. note that the flag bit is not affected by these forced operations. selected counter bus 0x000500 0x001000 0x001100 0x001250 0x001525 0x0016a0 a2(captured) value 2 b2(captured) value b1 value 3 0xxxxxxx 0x001000 0x001250 0x0016a0 0xxxxxxx 0x001000 0xxxxxxx 0x001000 input signal 1 a aa flag pin/register edpol = 1 a1 value 0xxxxxxx 0x001000 0x001000 0x001250 0x001250 read emiosa[n] read emiosb[n] 0x001250 notes: 1. after input filter 2. emiosa[n] = a2 3. emiosb[n] = b1 0x0016a0
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 678 freescale semiconductor note if both registers (a1 and b1) are loaded with the same value, the b match prevails concerning the output pin stat e (output flip-flop is set to the complement of edpol), the flag bi t is set and both comparators are disabled. figure 27-27 and figure 27-28 show how the unified channel can be used to generate a single output pulse with flag bit being set on the sec ond match or on both matches, respectively. figure 27-27. double action output compare with flag set on the second match figure 27-28. double action output compare with flag set on both matches selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 a1 value 1 b1 value 2 0xxxxxxx 0x001100 0x001100 0x001100 0xxxxxxx 0x001000 0x001000 0x001000 output flip-flop a1 match b1 match update to a1 and b1 flag pin/register a1 match b1 match notes: 1. emiosa[n] = a1 (when reading) 2. emiosb[n] = b1 (when reading) a2 = a1according to ou[n] bit b2 = b1according to ou[n] bit mode selected counter bus 0x000500 0x001000 0x001100 0x001000 0x001100 a1 value 1 b1 value 2 0xxxxxxx 0x001100 0x001100 0x001100 0xxxxxxx 0x001000 0x001000 0x001000 output flip-flop a1 match b1 match update to a1 and b1 flag pin/register a1 match b1 match notes: 1. emiosa[n] = a1 (when reading) 2. emiosb[n] = b1 (when reading) a2 = a1according to ou[n] bit b2 = b1according to ou[n] bit mode
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 679 figure 27-29. daoc with transfer disabling example 27.4.4.1.1.7 modulus counter (mc) mode the mc mode can be used to provide a time base for a counter bus or as a general purpose timer. bit mode[6] selects internal or external clock source when cleared or set, respectively. when external clock is selected, the input signal pin is used as the source and the tri ggering polarity edge is selected by the edpol and edsel in the emiosc[n] register. the internal counter counts up from th e current value until it matches the value in regi ster a1. register b1 is cleared and is not accessible to the mcu. bit mo de[4] selects up mode or up/down mode, when cleared or set, respectively. when in up count mode, a match betw een the internal counter and regist er a1 sets the flag and clears the internal counter. the timing of those events va ries according to the mc mode setup as follows: ? internal counter clearing on match start (mode[0:6] = 001000b) ? external clock is selected if mode [6] is set. in this case the in ternal counter clears as soon as the match signal occurs. the channe l flag is set at the same time the match occurs. note that by having the internal counter cleared as soon as the match occurs and incremented at the next input event a shorter zero count is generated. see figure 27-52 and figure 27-53 . ? internal clock source is selected if mode[6] is cleared. in this case the counter clears as soon as the match signal occurs. the channel flag is set at the same time the match occurs. at the next prescaler tick after the match the intern al counter remains at zero and only resumes counting on the following tick. see figure 27-52 and figure 27-54 . ? internal counter clearing on match end (mode[0:6] = 001001b) selected counter bus 0x0 0x2 flag set event a1 value 2 0xx output flip-flop 2. emiosa[n] = a1 (when reading) 0x0 0x2 0x1 0x2 0x0 0x1 0x1 flag pin/register flag clear edsel = 1 system clock enabled a1 match edpol = x b2 value 5 0x2 b1 value 4 0xx a2 value 3 0x1 ou 1 enabled b1 match 0x1 0xx 0xx 0x2 0x1 write to a2 0x2 0x2 0x1 0x2 0x1 0x1 0x2 write to b2 write to a2 write to b2 write to a2 write to b2 mode[0]=1 3. emiosa[n] = a2 (when writing) 4. emiosb[n] = b1 (when reading) 5. emiosb[n] = b2 (when writing) note: 1. ou[n] bit of emiosoudis register
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 680 freescale semiconductor ? external clock is selected if mode[6] is set. in this case the internal counter clears when the match signal is asserted and the input event occu rs. the channel flag is set at the same time the counter is cleared. see figure 27-52 and figure 27-55 . ? internal clock source is selected if mode[6] is cleared. in this case the internal counter clears when the match signal is asserted and the prescal er tick occurs. the channel flag is set at the same time the counter is cleared. see figure 27-52 and figure 27-55 . note if the internal clock source is select ed and the prescaler of the internal counter is set to 1, the mc mode be haves the same way even in clear on match start or clear on match end submodes. when in up/down count mode (mod e[0:6] = 00101bb), a match between the internal counter and register a1 sets the flag and changes the counter directi on from increment to decrement. a match between register b1 and the internal counter changes the count er direction from decremen t to increment and sets the flag only if mode[5] bit is set. only values different than 0x0 must be written at a register. loading 0x0 lead s to unpredictable results. updates on a register or counter in mc mode may cause loss of match in the current cycle if the transfer occurs near the match. in this ca se, the counter may rollover and re sume operation in the next cycle. register b2 has no effect in mc m ode. nevertheless, register b2 can be accessed for reads and writes by addressing emiosb. figure 27-30 and figure 27-31 show how the unified ch annel can be used as mo dulus counter in up mode and up/down mode, respectively. figure 27-30. modulus counter up mode example 0xffffff 0x000303 0x000000 emioscnt[n] time match a1 a1 value 1 0x000303 0x000303 0x000200 write to a2 match a1 write to a2 0x000200 match a1 match a1 0xxxxxxx flag pin/register notes: 1. emiosa[n] = a1 0x000303 0x000200 a2 = a1according to ou[n] bit mode
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 681 figure 27-31. modulus counter up/down mode example 27.4.4.1.1.8 modulus count er buffered (mcb) mode the mcb mode provides a time base that can be shared with other channels through th e internal counter buses. register a1 is double buffere d thus allowing smooth transitions between cycles when changing a2 register value on the fly. a1 register is updated at th e cycle boundary, which is defined as when the internal counter transitions to 0x1. the internal counter values operates within a range from 0x1 to the value in regist er a1. if when entering mcb mode coming out from gpio mode, the internal counter value is not within that range, then the a match will not occur, causing the channel internal c ounter to wrap at the maximum counter value, which is 0xffff for a 16-bit counter. after the counter wrap occurs, it retu rns to 0x1 and resumes normal mcb mode operation. thus in order to avoid the counter wr ap condition, make sure its value is within the 0x1 to a1 register value range when the mcb mode is entered. bit mode[6] selects internal clock sour ce if cleared or external if set. when external clock is selected the input channel pin is used as the channel clock source. the active edge of this clock is defined by edpol and edsel bits in the emiosc[n] channel register. when entering in mcb mode, if up counter is selected by mode[4] = 0 (mode[0:6] = 101000b), the internal counter starts c ounting from its current value to up direct ion until a1 match occurs. the internal counter is set to 0x1 when its value matches a1 value and a clock tick occurs (either prescaled clock or input pin event). if up/down counter is selected by setting mode[4] = 1, the counter cha nges direction at a1 match and counts down until it reaches the valu e 0x1. after it has reache d 0x1 it is set to count in up direction again. b1 register is used to generate a match in order to set the internal c ounter in up-count di rection if up/down mode is selected. register b1 cannot be changed while this mode is selected. note that differently fro m the mc mode, the mcb mo de counts between 0x1 and a1 register value. only values greater than 0x1 must be written at a1 re gister. loading values other than those leads to unpredictable results. the counter cycle period is equal to a1 value in up counter mode. if in up/down counter mode the peri od is defined by the expression: (2 a1) ? 2. figure 27-32 describes the counter cycle for several a1 valu es. register a1 is loaded with a2 register value at the cycle boundary. thus any value written to a2 register within cycle n will be updated to a1 at 0xffffff 0x000303 0x000000 emioscnt[n] time match a1 a1 value 1 0x000303 0x000303 0x000200 write to a2 match b1(=0) write to a2 0x000200 match a1 match b1(=0) 0xxxxxxx notes: 1. emiosa[n] = a1 0x000200 0x000200 flag pin/register a2 = a1according to ou[n] bit mode
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 682 freescale semiconductor the next cycle boundary and ther efore will be used on cycle n+1 . the cycle boundary between cycle n and cycle n+1 is defined as when the internal count er transitions from a1 value in cycle n to 0x1 in cycle n+1 . note that the flag is generated at the cycle boundary and has a s ynchronous operation, meaning that it is asserted one system clock cycle after the flag set event. figure 27-32. modulus counter buffered (mcb) up count mode figure 27-33 describes the mcb in up/down counter mo de (mode[0:6] = 10101bb). a1 register is updated at the cycle boundary. if a2 is written in cycle n , this new value will be used in cycle n+1 for a1 match. flags are generated on ly at a1 match start if mode[5] is 0. if mode[5] is set to 1 flags are also generated at the cycle boundary. figure 27-33. modulus counter buffered (mcb) up/down mode figure 27-34 describes in more detail the a1 register update process in up counter mode. the a1 load signal is generated at the last syst em clock period of a counter cycle. thus, a1 is updated with a2 value at the same time that the counter (emioscnt[n]) is loaded with 0x1. the load signal pulse has the emioscnt[n] time write to a2 match a1 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n cycle n+1 cycle n+2 flag clear emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000007 flag set event a1 value 0x000006 0x000005 0x000007 0x000005 0x000007 a2 value flag pin/register prescaler ratio = 1 cycle n+1 cycle n+2 cycle n flag clear
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 683 duration of one system clock period. if a2 is written within cycle n its value is available at a1 at the first clock of cycle n+1 and the new value is used for match at cycle n+1 . the update disable bits ou[n] of emiosoudis register can be used to control the update of this regist er, thus allowing to delay the a1 register update for synchronization purposes. figure 27-34. mcb mode a1 register update in up counter mode figure 27-35 describes the a1 register update in up/down co unter mode. note that a2 can be written at any time within cycle n in order to be used in cycle n+1 . thus a1 receives this new value at the next cycle boundary. note that the update disabl e bits ou[n] of emiosoudis regist er can be used to disable the update of a1 register. figure 27-35. mcb mode a1 register update in up/down counter mode 27.4.4.1.1.9 output pulse width and frequency modulatio n buffered (opwfmb) mode this mode (mode[0:6] = 10110b0) provides waveforms with variable duty cycle and frequency. the internal channel counter is automatica lly selected as the time base when this mode is selected. a1 register indicates the duty cycle and b1 register the frequenc y. both a1 and b1 registers are double buffered to a1 value 0x000008 0x000008 0x000001 internal counter 0x000004 0x000006 a2 value 0x000008 0x000004 0x000006 0x000002 0x000004 0x000006 write to a2 write to a2 match a1 match a1 a1 load signal 8 4 6 match a1 counter = a1 time cycle n cycle n+1 cycle n+2 prescaler ratio = 2 a1 value 0x000006 a2 value 0x000006 0x000005 0x000006 0x000005 a1 load signal counter = 2 emioscnt[n] time write to a2 match a1 match a1 write to a2 0x000001 0x000005 0x000006 0x000006 cycle n cycle n+1 cycle n+2 prescaler ratio = 2
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 684 freescale semiconductor allow smooth signal generation when changing the regi sters values on the fly. 0% and 100% duty cycles are supported. at opwfmb mode entry the output flip-flop is set to the value of the edpol bit in the emiosc[n] register. if when entering opwfmb mode co ming out from gpio mode the intern al counter value is not within that range then the b match will not occur causing th e channel internal counter to wrap at the maximum counter value, which is 0xffff for a 16-bit counter. after the counter wr ap occurs it returns to 0x1 and resume normal opwfmb mode operation. thus in orde r to avoid the counter wrap condition make sure its value is within the 0x1 to b1 register va lue range when the opwfmb mode is entered. when a match on comparator a occurs the output register is set to the value of edpol. when a match on comparator b occurs the output register is set to th e complement of edpol. b1 match also causes the internal counter to transition to 0x1, thus restarting the counter cycle. only values greater than 0x1 are allowed to be written to b1 register. loading valu es other than those leads to unpredictable results. if you want to configure the module for opwfmb mode , ensure that the b1 register is modified before the mode is set. figure 27-36 describes the operation of the opwfmb mode regarding output pin transitions and a1/b1 registers match events. note that the output pin tran sition occurs when the a1 or b1 match signal is deasserted, which is indicated by the a1 match negedge detection signal. if register a1 is set to 0x4 the output pin transitions 4 count er periods after the cycle had started, plus one system clock cycle. note that in the example shown in figure 27-36 the internal counter prescaler has a ratio of two. figure 27-36. opwfmb a1 and b1 match to output register delay figure 27-37 describes the generated output signal if a1 is set to 0x0. since the counter does not reach zero in this mode, the channel internal logic infers a match as if a1 = 0x1 with the difference that in this case, the posedge of the matc h signal is used to trigge r the output pin transition in stead of the negedge used when a1 = 0x1. note that a1 pos edge match signal from cycle n+1 occurs at the same time as b1 negedge 8 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler prescaler ratio = 2
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 685 match signal from cycle n . this allows to use the a1 posedge match to mask the b1 negedge match when they occur at the same time. the result is that no tr ansition occurs on the output flip-flop and a 0% duty cycle is generated. figure 27-37. opwfmb mode with a1 = 0 (0% duty cycle) figure 27-38 describes the timing for the a1 and b1 regist ers load. the a1 and b1 load use the same signal, which is generated at the la st system clock period of a counter cycle. thus, a1 and b1 are updated respectively with a2 and b2 values at the same time that the counter (emioscnt[n]) is loaded with 0x1. this event is defined as the cycle boundary. the load signal pulse has the duration of one system clock period. if a2 and b2 ar e written within cycle n their values are available at a1 and b1, respectively, at the first clock of cycle n+1 and the new values are used for matches at cycle n+1 . the update disable bits ou[n] of emiosoudis regist er can be used to control the update of these registers, thus allowing to delay the a1 and b1 registers update for synchronization purposes. in figure 27-38 it is assumed that both the channel and global prescalers ar e set to 0x1 (each divide ratio is two), meaning that the channel internal counter tr ansitions at every four sy stem clock cycles. flags can be generated only on b1 matches when mode[5] is cleared, or on both a1 and b1 matches when mode[5] is set. since b1 flag occurs at the cycle bounda ry, this flag can be used to indicate that a2 or b2 data written on cycle n were loaded to a1 or b1, respectiv ely, thus generating matches in cycle n+1 . note that the flag has a synchronous operation, meaning that it is assert ed one system cl ock cycle after the flag set event. 1 4 match a1 negedge detection 5 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 emioscnt time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 system clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection no transition at this point 1 cycle n cycle n+1 prescaler ratio = 2
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 686 freescale semiconductor figure 27-38. opwfmb a1 and b1 registers update and flags the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on comparators a or b respectively. simi larly to a b1 match forcmb sets the internal counter to 0x1. the flag bit is not set by the forcma or forcmb bits being asserted. figure 27-39 describes the genera tion of 100% and 0% dut y cycle signals. it is assumed edpol = 0 and the resultant prescaler value is 1. initially a1 = 0x8 and b1 = 0x8. in this case, b1 match has precedence over a1 match, thus the output flip-flop is set to th e complement of edpol bit. this cycle corresponds to a 100% duty cycle signal. the same output signal can be generated for any a1 value greater or equal to b1. figure 27-39. opwfmb mode from 100% to 0% duty cycle a 0% duty cycle signal is gene rated if a1 = 0x0 as shown in figure 27-39 cycle 9. in this case b1 = 0x8 match from cycle 8 occurs at the same time as the a1 = 0x0 match from cycle 9. please, refer to edpol = 0 cycle n cycle n+1 cycle n+2 a1 value 1 b1 value b2 value 0x8 0x2 0x6 0x8 0x1 internal counter 0x4 0x6 a2 value 1 0x2 0x4 0x6 0x2 0x4 0x6 0x8 0x6 output pin write to b2 write to a2 write to a2 match a1 match a1 match b1 match b1 match b1 a1/b1 load signal due to b1 match cycle n-1 flag set event flag pin/register prescaler ratio = 4 flag clear mode 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% emioscnt edpol = 0 a1 value b1 value output pin 0x000008 prescaler ratio = 1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value 0x000008 0x000001
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 687 figure 27-37 for a description of the a1 and b1 match generation. in this case a1 match has precedence over b1 match and the output signal transitions to edpol. 27.4.4.1.1.10 center aligned output pwm buffered with dead time (opwmcb) mode this operation mode generates a center aligned pwm with dead time insertion to the leading (mode[0:6] = 10111b1) or trailing edge (mode[ 0:6] = 10111b0). a1 and b1 registers are double buffered to allow smooth output si gnal generation when changing a2 or b2 registers values on the fly. bits bsl[0:1] select the time base. the time base selected for a channel configured to opwmcb mode should be a channel configured to mcb up/down mode, as shown in figure 27-33 . it is recommended to start the mcb channel time base af ter the opwmcb mode is entered in order to avoid missing a matches at the very first duty cycle. register a1 contains the ideal duty cycle for the pwm signal and is compar ed with the selected time base. register b1 contains the dead time value and is compared against the internal counter. fo r a leading edge dead time insertion, the output pwm duty cycle is equal to the difference between register a1 and register b1, and for a trailing edge dead time insertion, the output pwm duty cy cle is equal to the sum of register a1 and register b1. bit mode[6] selects between trai ling and leading dead time insertion, respectively. note the internal counter runs in the intern al prescaler ratio, while the selected time base may be running in a different prescaler ratio. when opwmcb mode is entered, coming out from gp io mode, the output flip-flop is set to the complement of the edpol bit in the emiosc[n] register. the following basic steps summari ze proper opwmcb start up, assuming the channels are initially in gpio mode: 1. [global] disable global prescaler; 2. [mcb channel] disable channel prescaler; 3. [mcb channel] write 0x1 at internal counter; 4. [mcb channel] set a register; 5. [mcb channel] set channel to mcb up mode; 6. [mcb channel] set prescaler ratio; 7. [mcb channel] enable channel prescaler; 8. [opwmcb channel] disable channel prescaler; 9. [opwmcb channel] set a register; 10. [opwmcb channel] set b register; 11. [opwmcb channel] select time base input through bsl[1:0] bits; 12. [opwmcb channel] enter opwmcb mode; 13. [opwmcb channel] set prescaler ratio; 14. [opwmcb channel] enable channel prescaler; 15. [global] enable global prescaler.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 688 freescale semiconductor figure 27-40 describes the load of a1 and b1 registers that occurs when the selected counter bus transitions from 0x2 to 0x1. this ev ent defines the cycle boundary. note that values written to a2 or b2 within cycle n are loaded into a1 or b1 re gisters, respectively, and used to generate matches in cycle n+1 . figure 27-40. opwmcb a1 and b1 registers load bit ou[n] of the emiosoudis register can be used to disable the a1 and b1 updates, thus allowing to synchronize the load on these registers with the load of a1 or b1 registers in others channels. note that using the update disable bit a1 and b1 registers can be updated at the same counter cycle thus allowing to change both registers at the same time. in this mode a1 matches always se ts the internal counter to 0x1. when operating with leading edge dead time insertion the first a1 match sets the internal counter to 0x1. when a match occurs between register b1 and the internal time base, the output flip-flop is set to the value of the edpol bit. in the following match between register a1 and the se lected time base, the output flip-flop is set to the complement of the edpol bit. this sequence repeats continuously. the internal counter should not reach 0x0 as consequence of a rollover. in order to avoid it the user should not write to the emiosb register a value greater than twice the difference between external count up limit and emiosa value. figure 27-41 shows two cycles of a center aligned pwm signal. note that bot h a1 and b1 register values are changing within the same cycle, which allows to vary at the same time the duty cycle and dead time values. a1 value 0x000020 a2 value 0x000020 0x000015 0x000016 0x000015 a1/b1 load signal selected counter == 2 selected time write to a2 write to b2 write to b2 write to a2 0x000001 0x000005 0x000006 0x000016 cycle n cycle n+1 cycle n+2 counter bus b1 value 0x000004 b2 value 0x000004 0x000005 0x000006 0x000005 0x000006 prescaler ratio = 2 system clock
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 689 figure 27-41. opwmcb with lead dead time insertion when operating with trailing edge dead time inserti on, the first match between a1 and the selected time base sets the output flip-flop to the value of the ed pol bit and sets the internal counter to 0x1. in the second match between register a1 a nd the selected time base, the inte rnal counter is set to 0x1 and b1 matches are enabled. when the match between register b1 and the select ed time base occurs the output flip-flop is set to the complement of the ed pol bit. this sequenc e repeats continuously. edpol = 1 internal time base internal counter is set to 1 on a1 match dead time a1 value a2 value b1 value b2 value write to b2 selected counter bus 0x000002 0x000004 0x000002 0x000004 0x000015 0x000015 write to a2 0x000013 0x000013 0x000001 0x000002 0x000004 0x000015 0x000013 0x000020 dead time output flip-flop flag pin/register 0x000001
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 690 freescale semiconductor figure 27-42. opwmcb with trail dead time insertion flag can be generated in the trailing edge of th e output pwm signal when m ode[5] is cleared, or in both edges, when mode[5] is set. if subsequent matches occur on comparator s a and b, the pwm pulses continue to be generated, regardle ss of the state of the flag bit. note in opwmcb mode, forcma and forcmb do not have the same behavior as a regular match. instead, they force the output flip-flop to a constant value that depends upon the se lected dead time insertion mode, lead or trail, and the value of the edpol bit. forcma has different behaviors depe nding upon the selected dead time inse rtion mode, lead or trail. in lead dead time insertion forcma fo rce a transition in the output flip-flop to the opposite of edpol. in trail dead time insertion the output flip-f lop is forced to the value of edpol bit. if bit forcmb is set, th e output flip-flop value depends upon the se lected dead time insertion mode. in lead dead time insertion forcmb forces the output f lip-flop to transition to edpol bit value. in trail dead time insertion the output flip-flop is forced to the opposite of edpol bit value. note forcma bit set does not se t the internal time-base to 0x1 as a regular a1 match. the flag bit is not set either in cas e of a forcma or forcmb or even if both forces are issued at the same time. edpol = 1 internal time base internal counter is set to 1 on a1 match dead time a1 value a2 value b1 value b2 value write to b2 selected counter bus 0x000002 0x000004 0x000002 0x000004 0x000015 0x000015 write to a2 0x000013 0x000013 0x000001 0x000002 0x000004 0x000015 0x000013 0x000020 dead time output flip-flop flag pin/register 0x000001
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 691 note forcma and forcmb have the same behavior even in freeze or normal mode regarding the output pin transition. when forcma is issued along with forcmb the out put flip-flop is set to the opposite of edpol bit value. this is equivalent of saying that.forcm a has precedence over forcmb when lead dead time insertion is selected and forcmb has precedence ove r forcma when trail de ad time insertion is selected. duty cycle from 0% to 100% can be generated by se tting appropriate values to a1 and b1 registers relatively to the period of the external time base. setting a1 = 1 generates a 100% duty cycle waveform. assuming edpol is set to 1 and opwm cb mode with trail dead time insertion, 100% duty cycle signals can be generated if b1 occurs at or after the cycle boundary (external counter = 1). if a1 is greater than the maximum value of the selected counter bus period, then a 0% duty cycle is produced, only if the pin starts the current cycle in the op posite of edpol value. in case of 100% duty cycle, the transition from edpol to the opposite of edpol may be obtained by forcing pin, using forcma or forcmb, or both. note if a1 is set to 0x1 at opwmcb en try the 100% duty cycle may not be obtained in the very first pwm cycle due to the pin condition at mode entry. only values different than 0x0 are allowed to be writte n to a1 register. if 0x0 is loaded to a1 the results are unpredictable. note a special case occurs when a1 is se t to (external counter bus period)/2, which is the maximum value of the exte rnal counter. in this case the output flip-flop is constantly set to the edpol bit value. the internal channel logic prevents matches from one cycle to propagate to the next cycle. in trail dead time insertion b1 match from cycle n could eventually cross the cy cle boundary and occur in cycle n+1 . in this case b1 match is masked out and does not cause the output flip-f lop to transition. therefore matches in cycle n+1 are not affected by the late b1 matches from cycle n . figure 27-43 shows a 100% duty cycle output signal generated by setting a1 = 4 and b1 = 3. in this case the trailing edge is positi oned at the boundary of cycle n+1 , which is actually consid ered to belong to cycle n+2 and therefore does not cause th e output flip-flip to transition.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 692 freescale semiconductor figure 27-43. opwmcb with 100% duty cycle (a1 = 4 and b1 = 3) it is important to notice that, such as in opwmb and opwfmb modes, the match signal used to set or clear the channel output flip-flop is generated on the deassertion of the channel combinational comparator output signal, which compares the selected time base with a1 or b1 register values. please refer to figure 27-36 , which describes the delay from matches to output flip-flop trans ition in opwfmb mode. the operation of opwmcb mode is similar to op wfmb regarding matches and output pin transition. 27.4.4.1.1.11 output pulse width modulation buffered (opwmb) mode opwmb mode (mode[0:6] = 11000b0) is used to generate pulses wi th programmable leading and trailing edge placement. an external counter driven in mcb up mode must be selected from one of the counter buses. a1 register value de fines the first edge and b1 the s econd edge. the output signal polarity is defined by the edpol bit. if edpol is zero, a ne gative edge occurs when a1 matches the selected counter bus and a positive edge occurs wh en b1 matches the selected counter bus. the a1 and b1 registers are double buffered and updated from a2 and b2, respectively, at the cycle boundary. the load operation is similar to the opwfmb mode. please refer to figure 27-38 for more information about a1 and b1 registers update. flag can be generated at b1 matches, when mode[5 ] is cleared, or in both a1 and b1 matches, when mode[5] is set. if subsequent matches occur on co mparators a and b, the pwm pulses continue to be generated, regardless of the state of the flag bit. forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a1 or b1 respectively. flag bi t is not set by the forcma and forcmb operations. at opwmb mode entry the output flip-flop is set to the value of the edpol bit in the emiosc[n] register. 0x000001 dead time 0x000020 dead time dead time write to a2 selected counter bus internal time base 0x000004 a1 value a2 value b1 value b2 value 0x000004 0x000001 output flip-flop 0x000003 0x000015 0x000003 0x000015 0x000003 cycle n cycle n+1 cycle n+2
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 693 some rules applicable to the opwmb mode are: ? b1 matches have precedence over a1 matches if they occur at the same time within the same counter cycle ? a1 = 0 match from cycle n has precedence over b1 match from cycle n?1 ? a1 matches are masked out if they occur after b1 match within the same cycle ? any value written to a2 or b2 on cycle n is loaded to a1 and b1 re gisters at the following cycle boundary (assuming ou[n] bit of emioso udis register is not asserted ). thus the new values will be used for a1 and b1 matches in cycle n+1 figure 27-44 describes the operation of the opwmb mode regarding a1 and b1 matches and the transition of the channel output pin. in this example edpol is set to 0. figure 27-44. opwmb mode matches and flags note that the output pin transiti ons are based on the negedges of the a1 and b1 match signals. figure 27-44 shows in cycle n+1 the value of a1 register being set to 0. in this case th e match posedge is used instead of the negedge to transition the output flip-flop. figure 27-45 describes the channel operation for 0% duty cy cle. note that the a1 match posedge signal occurs at the same time as the b1 = 0x8 negedge si gnal. in this case a1 match has precedence over b1 match, causing the output pin to rema in at edpol bit value, thus generating a 0% duty cycle signal. 1 4 match a1 negedge detection 6 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000006 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 6 flag set event selected counter bus flag pin/register
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 694 freescale semiconductor figure 27-45. opwmb mode with 0% duty cycle figure 27-46 shows a waveform changing from 100% to 0% duty cycle. edpol in this case is zero. in this example b1 is programmed to the same value as the period of the external selected time base. figure 27-46. opwmb mode from 100% to 0% duty cycle in figure 27-46 if b1 is set to a value lower than 0x8 it is not possible to achieve 0% duty cycle by only changing a1 register value. since b1 matches have precedence ove r a1 matches the out put pin transitions to the opposite of edpol bit at b1 match. note also that if b1 is set to 0x9, for inst ance, b1 match does not occur, thus a 0% duty cycle signal is generated. 1 4 match a1 negedge detection 8 a1 value 0x000004 a1 match a1 match negedge detection output pin edpol = 0 selected time match b1 negedge detection b1 match b1 match negedge detection b1 value 0x000008 clock prescaler a2 value 0x000000 write to a2 0x000000 a1 match posedge detection match a1 posedge detection 1 cycle n cycle n+1 8 counter bus flag set event flag pin/register 0x000008 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 0% 100% selected edpol = 0 a1 value b1 value output pin 0x000008 prescaler = 1 cycle 1 cycle 2 cycle 3 cycle 4 cycle 5 cycle 6 cycle 7 cycle 8 cycle 9 counter bus 0x000007 0x000006 0x000005 0x000004 0x000003 0x000002 0x000001 0x000000 a2 value
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 695 27.4.4.1.1.12 output pulse width m odulation with trigger (opwmt) mode opwmt mode (mode[0:6] = 0100110) is intended to s upport the generation of pulse width modulation signals where the period is not modified while the sign al is being output, but wh ere the duty cycle will be varied and must not create glitches. the mode is inte nded to be used in conjunction with other channels executing in the same mode and sharing a common timebase. it wi ll support each channel with a fixed pwm leading edge position with respec t to the other channels and the ability to generate a trigger signal at any point in the period that can be output from the module to initiate activity in ot her parts of the device such as starting adc conversions. an external counter driven in eith er mc up or mcb up mode must be selected from one of the counter buses. register a1 defines the leading edge of the pwm output pulse and as such the beginning of the pwm?s period. this makes it possible to insure that the lead ing edge of multiple channels in opwmt mode can occur at a specific time with respect to the other cha nnels when using a shared timebase. this can allow the introduction of a fixed offset for each channel, wh ich can be particularly useful in the generation of lighting pwm control signals where it is desirable that edges are not coin cident with each other to help eliminate noise generation. th e value of register a1 represents the shift of the pwm channel with respect to the selected timebase. a1 can be configured with any value within th e range of the selected time base. note that registers loaded with 0x0 will not produce matches if the timebase is driv en by a channel in mcb mode. a1 is not buffered as the shift of a pwm channel mu st not be modified whil e the pwm signal is being generated. in case a1 is modified it is imme diately updated and one pw m pulse could be lost. emiosb[n] address gives access to b2 re gister for write and b1 register for read. register b1 defines the trailing edge of the pwm output pul se and as such the duty cycle of the pwm signal. to synchronize b1 update with the pwm signal a nd so ensure a co rrect output pulse generation the transfer from b2 to b1 is done at every match of register a1. emiosoudis register affects tr ansfers between b2 and b1 only. in order to account for the shift in the leading edge of the waveform defined by register a1 it will be necessary that the trailing edge, held in register b1, can roll over into the next period. this means that a match against the b1 register should not have to be qualified by a match in the a1 register. the impact of this would mean that incorrectly setting register b1 to a value less that register a1 will result in the output being held over a cycle boundary until the b1 value is encountered. this mode provides a buffered update of the trailing edge by upda ting register b1 with register b2 contents only at a match of register a1. the value loaded in register a1 is compared with the value on the selected time base. when a match on comparator a1 occurs, the output flip-flop is set to the value of the edpol bit. when a match occurs on comparator b, the output flip-flop is se t to the complement of the edpol bit. note that the output pin and flag tr ansitions are based on th e posedges of the a1, b1 and a2 match signals. please, refer to figure 27-44 at section 27.4.4.1.1.11, output pulse width modulation buffered (opwmb) mode , for details on match posedge.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 696 freescale semiconductor register a2 defines the generation of a trigger event within the pwm period. a2 should be configured with any value within the range of the selected time base. otherwise, no trigger wi ll be generated. a match on the comparator will generate the flag signal but it has no effect on the pwm output signal generation. the typical setup to obtain a trigger with flag is to enable dma and to drive the channel?s ipd_done input high. a2 is not buffered and therefore its update is immediate. if the channel is running when a change is made, this could cause either the loss of one trigger event or the generation of two trigger events within the same period. register a2 can be accessed by reading or writing th e emios uc alternate a register (emiosalta) at uc[n] base address +0x14. flag signal is set only at match on the comparator with a2. a match on the comparator with a1 or b1 or b2 has no effect on flag. at any time, the forcma and forcmb bits allow the software to force the output flip-flop to the level corresponding to a match on a or b respectively. any forcma and/or forcmb has priority over any simultaneous match regarding to output pin transitions. note that the load of b2 content on b1 register at an a match is not inhibited due to a simultaneous forcma/forcmb assertion. if both forcma and forcmb are asserted simu ltaneously the output pin goes to the oppos ite of edpol value such as if a1 and b1 registers had the same value. forcma assertion causes the tr ansfer from register b2 to b1 such as a regular a match, regard less of forcmb assertion. if subsequent matches occur on comparators a1 a nd b, the pwm pulses continue to be generated, regardless of the state of the flag bit. at opwmt mode entry the output flip-flop is set to the complement of the edpol bit in the emiosc[n] register. in order to achieve 0% duty cycle both registers a1 and b must be set to the same value. when a simultaneous match on comparators a and b occur, th e output flip-flop is set at every period to the complement value of edpol. in order to achieve 100% duty cycle th e register b1 must be set to a va lue greater than maximum value of the selected time base. as a consequence, if 100% duty cycle must be implem ented, the maximum counter value for the time base is 0xfffe for a 16-bit counter . when a match on comparat or a1 occurs the output flip-flop is set at every period to the value of edpol bi t. the transfer from regi ster b2 to b1 is still triggered by the match at comparator a. figure 27-47 shows the unified channel running in opwm t mode with trigger event generation and duty cycle update on next period update.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 697 figure 27-47. opwmt example figure 27-48 shows the unified channel running in opwm t mode with trigger event generation and 0% duty. figure 27-48. opwmt with 0% duty cycle figure 27-49 shows the unified channel running in opwm t mode with trigger event generation and 100% duty cycle. 0x0011ff 0x001000 0x000000 selected counter bus time output flip-flop a1 value 1 write to b2 0x000400 b1 value b2 value 2 0x000700 match b1 write to a1 0xxxxxxx 0x000400 0x001000 0x000700 and b2 0x001000 match a1 match b1 match a1 notes: 1. emiosa[n] = a1 2. emiosb[n] = b2 for write, b1 for read 0x000700 notes: a2 value 0x000500 0x000500 flag pin/register match a2 match a2 0x0011ff 0x001000 0x000000 selected counter bus time output flip-flop a1 value 1 write to b2 0x000400 b1 value b2 value 2 0x000400 match b1 write to a1 0xxxxxxx 0x000400 0x001000 and b2 0x001000 match a1 match b1 match a1 notes: 1. emiosa[n] = a1 2. emiosb[n] = b2 for write, b1 for read 0x000400 notes: a2 value 0x000500 0x000500 flag pin/register match a2 match a2
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 698 freescale semiconductor figure 27-49. opwmt with 100% duty cycle 27.4.4.1.2 input programmable filter (ipf) the ipf ensures that only valid i nput pin transitions are received by the unified channel edge detector. a block diagram of the ipf is shown in figure 27-50 . the ipf is a 5-bit programmable up counter that is in cremented by the selected clock source, according to bits if[0:3] in emiosc[n] register. figure 27-50. lnput programmable filter submodule diagram the input signal is synchronized by sy stem clock. when a state change occurs in this signal, the 5-bit counter starts counti ng up. as long as the new state is stable on the pin, the counter remains incrementing. if a counter overflows occurs , the new pin value is valida ted. in this case, it is transmitted as a pulse edge to the edge detector. if the opposite edge appears on the pin before validation (o verflow), the counter is reset. at the next pin tran sition, the counter starts coun ting again. any pulse that is shorter than a full range of the masked counter is regarded as a glitch and it is not passed on to the edge de tector. a timing diagram of the input filter is shown in figure 27-51 . 0x0011ff 0x001000 0x000000 selected counter bus time output flip-flop a1 value 1 write to b2 0x000400 b1 value b2 value 2 0x001200 match b1 does not occur write to a1 0xxxxxxx 0x000400 0x001000 and b2 0x001000 match a1 match b1 match a1 notes: 1. emiosa[n] = a1 2. emiosb[n] = b2 for write, b1 for read 0x001200 notes: a2 value 0x000500 0x000500 flag pin/register match a2 match a2 if3 filter out ipg_clk prescaled clock if2 if1 if0 clk fck emiosi 5-bit up counter synchronizer clock
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 699 figure 27-51. input programmable filter example the filter is not disabled during eith er freeze state or negated gtbe input. 27.4.4.1.3 clock prescaler (cp) the cp divides the gcp output signal to generate a cl ock enable for the internal counter of the unified channels. the gcp output signal is prescaled by the value defined in figure 27-18 according to the ucpre[0:1] bits in emiosc[n] re gister. the prescaler is enabled by setting the ucpren bit in the emiosc[n] and can be stopped at any time by clearing this bit, thereby stopping the internal counter in the unified channel. in order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. write 0 at both gpren bit in em iosmcr register and ucpren bi t in emiosc[n] register, thus disabling prescalers. 2. write the desired value for pr escaling rate at ucpre[0:1] bits in emiosc[n] register. 3. enable channel prescaler by writing 1 at ucpren bit in emiosc[n] register. 4. enable global prescaler by writing 1 at gpren bit in emiosmcr register. the prescaler is not disabl ed during either freeze stat e or negated gtbe input. 27.4.4.1.4 effect of fr eeze on the unified channel when in debug mode, bit frz in th e emiosmcr and bit fren in the emiosc[n] register are both set, the internal counter, and the unified channel capture and compare functions are ha lted. the uc is frozen in its current state. during freeze, all registers are accessi ble. when the unified channel is operating in an output mode, the force match functions remain available, allowing the software to force the output to the desired level. note that for input modes, any i nput events that may occur while the channel is frozen are ignored. when exiting debug mode or freeze enable bit is cleared (frz in the emio smcr or fren in the emiosc[n] register) the channel acti ons resume, but may be inconsistent until channel enters gpio mode again. time selected clock emiosi 5-bit counter filter out if[0:3]
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 700 freescale semiconductor 27.4.4.2 ip bus interface unit (biu) the biu provides the interface betw een the internal interface bus (iib ) and the peripheral bus, allowing communication among a ll submodules and this ip interface. the biu allows 8-, 16-, and 32-bit access. they are performed over a 32-bit data bus in a single cycle clock. 27.4.4.2.1 effect of freeze on the biu when the frz bit in the emiosmcr is set and the module is in debug mode, the operation of biu is not affected. 27.4.4.3 global clock pr escaler submodule (gcp) the gcp divides the system clock to generate a clock for the cps of the channels. the main clock signal is prescaled by the value defined in figure 27-12 according to bits gpre[0:7] in the emiosmcr. the global prescaler is enabled by setting the gpren bi t in the emiosmcr and can be stopped at any time by clearing this bit, thereby stopping the internal counters in all the channels. in order to ensure safe working and avoid glitches the following steps must be performed whenever any update in the prescaling rate is desired: 1. write 0 at gpren bit in emiosmcr, thus disabling global prescaler. 2. write the desired value fo r prescaling rate at gpre [0:7] bits in emiosmcr. 3. enable global prescaler by writin g 1 at gpren bit in emiosmcr. the prescaler is not disabl ed during either freeze stat e or negated gtbe input. 27.4.4.3.1 effect of freeze on the gcp when the frz bit in the emiosmcr is set and the module is in debug mode, the operation of gcp submodule is not affected, that is, there is no freeze function in this submodule. 27.4.5 initialization/ap plication information on resetting the emios the unified channels enter gpio input mode. 27.4.5.1 considerations before changing an operating mode, the uc must be programmed to gpio mode and emiosa[n] and emiosb[n] registers must be updated with the corr ect values for the next operating mode. then the emiosc[n] register can be written with the new operating mode. if a uc is changed from one mode to another without performing this proc edure, the first operation cycle of the selected time base can be random, that is, matches can occur in random time if the contents of emiosa[n] or emiosb[n] were not updated with the correct value before the time base matches the previous c ontents of emiosa[n] or emiosb[n].
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 701 when interrupts are enabled, the software must clear the flag bits before exi ting the interrupt service routine. 27.4.5.2 application information correlated output signals can be generated by all output operation mode s. bits ou[n] of the emiosoudis register can be used to co ntrol the update of these output signals. in order to guarantee that the inte rnal counters of correlated channels are incremented in the same clock cycle, the internal prescalers must be set up before en abling the global prescaler. if the internal prescalers are set after enabling the global presca ler, the internal counters may increment in the same ratio, but at a different clock cycle. 27.4.5.2.1 time base generation for mc with internal clock sour ce operation modes, the internal counter rate can be modified by configuring the clock prescaler ratio. figure 27-52 shows an example of a time base with prescaler ratio equal to one. note mcb and opwfmb modes have a different behavior. figure 27-52. time base period when running in the fastest prescaler ratio if the prescaler ratio is greater than one or external clock is selected, the c ounter may behave in three different ways dependi ng on the channel mode: ? if mc mode and clear on match start and external clock source are selected, the internal counter behaves as described in figure 27-53 . ? if mc mode and clear on match st art and internal clock source ar e selected, the internal counter behaves as described in figure 27-54 . ? if mc mode and clear on match end are selected, the internal counter behaves as described in figure 27-55 . system clock input event/prescaler clock enable = 1 internal counter match value = 3 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 pre scaled clock ratio = 1 (bypassed) see note 1 flag set event note 1: when a match occurs, the first clock cycle is used to clear the internal counter, starting another period. flag pin/register flag clear
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 702 freescale semiconductor note mcb and opwfmb modes have a different behavior. figure 27-53. time base generation with external clock and clear on match start figure 27-54. time base generation with internal clock and clear on match start system clock input event internal counter match value = 3 1 2 3 0 see note 1 note 1: when a match occurs, the first system clock cycle is used to clear the internal counter, and at the next edge of prescaler clock enable 1 2 the counter will start counting. 1 2 3 0 flag set event flag clear flag pin/register system clock prescaler clock enable internal counter match value = 3 0 1 3 0 2 0 3 0 prescaled clock ratio = 3 see note 1 note 1: when a match occurs, the first clock cycle is used to clear the internal counter, and only after a second edge of pre scaled clock 1 2 the counter will start counting. flag set event flag clear flag pin/register
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 703 figure 27-55. time base generation with clear on match end 27.4.5.2.2 coherent accesses it is highly recommended that the software wait s for a new flag set event before start reading emiosa[n] and emiosb[n] registers to get a new measurement. the fl ag indicates that new data has been captured and it is the only way to assure data coherency. the flag set event can be detected by polling the fl ag bit or by enabling the interrupt request or dma request or ctu trigger generation. reading the emiosa[n] register again in the same period of th e last read of emiosb [n] register may lead to incoherent results. this will occur if the last re ad of emiosb[n] register o ccurred after a disabled b2 to b1 transfer. 27.4.5.2.3 channel/modes initialization the following basic steps summarize basic output mode startup, assuming the cha nnels are initially in gpio mode: 1. [global] disable global prescaler. 2. [timebase channel] disable channel prescaler. 3. [timebase channel] write initial value at internal counter. 4. [timebase channel] set a/b register. 5. [timebase channel] set channel to mc(b) up mode. 6. [timebase channel] set prescaler ratio. 7. [timebase channel] enable channel prescaler. 8. [output channel] disable channel prescaler. 9. [output channel] set a/b register. 10. [output channel] select timebase input through bits bsl[1:0]. 11. [output channel] enter output mode. system clock input event/prescaler clock enable internal counter match value = 3 0 1 3 2 0 prescaled clock ratio = 3 see note 1 note 1: the match occurs only when the input event/prescaler clock enable is active. then, the internal counter is immediately cleared. 1 2 3 flag set event flag clear flag pin/register
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 704 freescale semiconductor 12. [output channel] set prescaler ratio (same ratio as timebase channel). 13. [output channel] enable channel prescaler. 14. [global] enable global prescaler. 15. [global] enable global time base. the timebase channel and the output channel may be the same for some applications such as in opwfm(b) mode or whenever the output channe l is intended to run the timebase itself. the flags can be configured at any time. 27.5 periodic interrupt timer (pit) 27.5.1 introduction the pit is an array of timers that can be used to raise interrupts and trigger dma channels. figure 27-56 shows the pit block diagram. figure 27-56. pit block diagram 27.5.2 features the main features of this block are: ? timers can generate dma trigger pulses timer 7 timer 0 . . . pit registers peripheral interrupts pit . . . triggers bus system clock
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 705 ? timers can generate interrupts ? all interrupts are maskable ? independent timeout periods for each timer 27.5.3 signal description the pit module has no external pins. 27.5.4 memory map and register description this section provides a detailed description of all registers accessi ble in the pit module. 27.5.4.1 memory map table 27-23 gives an overview of the pit registers. see the chip memory map for the pit base address. table 27-23. pit memory map base address: 0xc3ff_0000 address offset use location 0x000 pit module control register (pitmcr) on page 706 0x004?0x0fc reserved 0x100?0x10c timer channel 0 see table 27-24 0x110?0x11c timer channel 1 see table 27-24 0x120?0x12c timer channel 2 see table 27-24 0x130?0x13c timer channel 3 see table 27-24 0x140?0x14c timer channel 4 see table 27-24 0x150?0x15c timer channel 5 see table 27-24 0x160?0x16c timer channel 6 see table 27-24 0x170?0x17c timer channel 7 see table 27-24 table 27-24. timer channel n address offset use location channel + 0x00 timer load value register (ldval) on page 706 channel + 0x04 current timer value register (cval) on page 707 channel + 0x08 timer control register (tctrl) on page 708 channel + 0x0c timer flag register (tflg) on page 708
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 706 freescale semiconductor note register address = base address + a ddress offset, where the base address is defined at the mcu level and the a ddress offset is defined at the module level. note reserved registers will read as 0, writes will have no effect. 27.5.4.2 pit module control register (pitmcr) this register controls whether the timer clocks s hould be enabled and whether the timers should run in debug mode. 27.5.4.3 timer load value register (ldval) this register selects the timeout period for the timer interrupts. offset: 0x000 access: read/write 0123456789101112131415 r 0 0 0 0 0 00000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0000 0 00 0 0 mdis frz w reset0000000000000010 figure 27-57. pit module control register (pitmcr) table 27-25. pitmcr field descriptions field description mdis module disable this is used to disable the module clock. this bit should be enabled before any other setup is done. 0 clock for pit timers is enabled 1 clock for pit timers is disabled (default) frz freeze allows the timers to be stopped when the device enters debug mode. 0 = timers continue to run in debug mode. 1 = timers are stopped in debug mode.
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 707 27.5.4.4 current timer value register (cval) this register indicates the current timer position. offset: channel_base + 0x00 access: read/write 0123456789101112131415 r tsv[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tsv[15:0] w reset0000000000000000 figure 27-58. timer load value register (ldval) table 27-26. ldval field descriptions field description tsv time start value this field sets the timer start value. the timer counts down until it reaches 0, then it generates an interrupt and loads this register value again. writing a new val ue to this register does not restart the timer, instead the value is loaded once the timer expires. to abort the current cycle and start a timer period with the new value, the timer must be disabled and enabled again (see figure 27-63 ). offset: channel_base + 0x04 access: read 0123456789101112131415 rtvl[31:16] w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tvl[15:0] w reset0000000000000000 figure 27-59. current timer value register (cval) table 27-27. cval field descriptions field description tvl current timer value this field represents the current timer valu e. note that the timer uses a downcounter. note: the timer values will be frozen in debug mode if the frz bit is set in the pit module control register (see figure 27-2 ).
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 708 freescale semiconductor 27.5.4.5 timer contro l register (tctrl) this register contains the control bits for each timer. 27.5.4.6 timer flag register (tflg) this register holds the pit interrupt flags. offset: channel_base + 0x08 access: read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000000000 tie ten w reset0000000000000000 figure 27-60. timer control register (tctrl) table 27-28. tctrl field descriptions field description tie timer interrupt enable bit 0 interrupt requests from timer x are disabled 1 interrupt will be request ed whenever tif is set when an interrupt is pending (tif set), enabling the interrupt will immediately cause an interrupt event. to avoid this, the associated tif flag must be cleared first. ten timer enable bit 0 timer will be disabled 1 timer will be active offset: channel_base + 0x0c access: read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000000000000 tif w w1c reset0000000000000000 figure 27-61. timer flag register (tflg)
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 709 27.5.5 functional description 27.5.5.1 general this section gives detailed informat ion on the internal operati on of the module. each timer can be used to generate trigger pulses as well as to generate inte rrupts, each interrupt will be available on a separate interrupt line. 27.5.5.1.1 timers the timers generate triggers at periodic intervals, wh en enabled. they load their start values, as specified in their ldval registers, then count down until they reach 0. then they load their respective start value again. each time a timer reaches 0, it will gene rate a trigger pulse and set the interrupt flag. all interrupts can be enabled or masked (by setting th e tie bits in the tctrl re gisters). a new interrupt can be generated only after th e previous one is cleared. if desired, the current counter value of the timer can be read via the cval registers. the counter period can be restarte d, by first disabling, then enabling the timer with the ten bit (see figure 27-62 ). the counter period of a running time r can be modified, by first disabli ng the timer, setting a new load value, and then enabling the timer again (see figure 27-63 ). it is also possible to change th e counter period without restarting the timer by wr iting the ldval register with the new load value. this value will then be loaded after the next trigger event (see figure 27-64 ). figure 27-62. stopping and starting a timer table 27-29. tflg field descriptions field description tif time interrupt flag tif is set to 1 at the end of the timer period. this flag can be cleared only by writing it with a 1. writing a 0 has no effect. if enabled (tie = 1), tif causes an interrupt request. 0 timeout has not yet occurred 1 timeout has occurred p1 p1 timer enabled disable timer p1 start value = p1 trigger event p1 re-enable timer
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 710 freescale semiconductor figure 27-63. modifying running timer period figure 27-64. dynamically setting a new load value 27.5.5.1.2 debug mode in debug mode the timers will be frozen. this is intended to aid so ftware development, allowing the developer to halt the proces sor, investigate the current state of the system (for example, the timer values) and then continue the operation. 27.5.5.2 interrupts all of the timers support interrupt generation. see chapter 18, interrupt controller (intc) , for related vector addresses and priorities. timer interrupts can be disabled by setting the tie bits to zero. the timer interrupt flags (tif) are set to 1 when a timeout occurs on the associated timer, a nd are cleared to 0 by writing a 1 to that tif bit. 27.5.6 initialization and application information 27.5.6.1 example configuration in the example configuration: ? the pit clock has a frequency of 50 mhz ? timer 1 creates an interrupt every 5.12 ms ? timer 3 creates a trigger event every 30 ms first the pit module needs to be act ivated by programming pit_mcr[mdis] = 0. the 50 mhz clock frequency equates to a clock pe riod of 20 ns. timer 1 needs to trigger every 5.12 ms/20 ns = 256000 cycles and timer 3 every 30 ms/20 ns = 1500000 cycles. the value for the ldval register trigger would be calcu lated as (period / clock period) ? 1. p1 timer enabled disable timer, start value = p1 trigger event re-enable timer p1 set new load value p2 p2 p2 p1 p1 timer enabled new start value p2 set p1 p2 start value = p1 p2 trigger event
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 711 the ldval registers must be set as follows: ? ldval for timer 1 is set to 0x0003e7ff ? ldval for timer 3 is set to 0x0016e35f the interrupt for timer 1 is enabled by setting tie in the tctrl1 register. the ti mer is started by writing a 1 to bit ten in the tctrl1 register. timer 3 shall be used only for triggering. therefore ti mer 3 is started by writi ng a 1 to bit ten in the tctrl3 register; bit tie stays at 0. the following example code matches the described setup: // turn on pit pit_ctrl = 0x00; // timer 1 pit_ldval1 = 0x0003e7ff; // setup timer 1 for 256000 cycles pit_tctrl1 = tie; // enable timer 1 interrupts pit_tctrl1 |= ten; // start timer 1 // timer 3 pit_ldval3 = 0x0016e35f; // setup timer 3 for 1500000 cycles pit_tctrl3 = ten; // start timer 3
chapter 27 timers MPC5606BK microcontroller reference manual, rev. 2 712 freescale semiconductor this page is intent ionally left blank.
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 713 ??? adc system ???
MPC5606BK microcontroller reference manual, rev. 2 714 freescale semiconductor this page is intent ionally left blank.
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 715 chapter 28 analog-to-digital converter (adc) 28.1 overview 28.1.1 device-specific features ? two adc modules, (adc_0 with 10-bit reso lution and adc_1 with 12-bit resolution) ? 0?v dd common mode conversion range ? independent reference supplies for each adc ? 53 single-ended input channels (depending on pa ckage type), expandable to 81 channels via external multiplexing ? internally multiplexed channels ? 16 precision channels shared between 10-bit and 12-bit adcs ? three standard channels shared between 10-bit and 12-bit adcs ? five dedicated standard channels on 12-bit adc ? as many as 29 dedicated standard channels on 10-bit adc ? externally multiplexed channels ? internal control to support generation of external analog multiplexer selection ? four internal channels optionally used to support extern ally multiplexed inputs, providing transparent control for additional adc channels ? each of the four channels supports as ma ny as eight externally multiplexed inputs ? three independently configurable sample and conversion times for high precision channels, standard precision channels, and externally multiplexed channels ? dedicated result registers avai lable for every channel. conversi on information, such as mode of operation (normal, injected or ctu) , is associated to data value. ? one shot/scan modes ? chain injection mode ? conversion triggering sources: ? software ?ctu ? pit channel 2 and 6 (for injected conversion) ? conversion triggering support ? inte rnal conversion triggering from periodic interrupt timer (pit) or timed i/o module (emios) ? power-down mode for analog portion of adc ? supports dma transfer of results based on the end of conversion ? 6 + 3 analog watchdogs (6 on 10-bit adc, 3 on 12-bit adc) with interrupt capability for continuous hardware monitoring
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 716 freescale semiconductor 28.1.2 device-specific implementation figure 28-1. implementation of adc_0 and adc_1 as many as 32 standard channels (3 pins shared with adc 12b) 16 precision channels (same pins as adc 12b) adc0_s[27] (ch 59) adc0_s[0] (ch 32) adc0_p[15] (ch 15) adc0_p[0] (ch 0) emios0_0 emios0_22 emios0_24 emios0_31 pit7 adc control adc trigger adc done 2 interrupts adc_eoc & adc_wd ctu digital interface analog switch emios pit intc d a mux 32 mux 16 adc_0 (10-bit) ch0 trig ch22 trig ch24 trig ch31 trig . . . . . . pit3 16 precision channels (same pins as adc 10b) adc_1_p[15] (ch 15) adc_1_p[0] (ch 0) 2 interrupts adc_eoc & adc_wd digital interface analog switch intc d a mux 16 adc_1 (12-bit) . . . emios1_0 emios1_22 emios1_24 emios1_31 ch32 trig ch54 trig ch56 trig ch63 trig ch23 trig ch55 trig pit6 pit2 adc control adc trigger adc done injection trigger injection tr i g g e r adc_1_s[7] (ch 39) adc_1_s[0] (ch 32) . . . mux 8 as many as 8 standard channels (3 pins shared with adc 10b) . . . . . . . . . . . . . . . . . . . . . . . . as many as 32 extended channels through external mux adc0_x[3] adc0_x[0] ma[2:0] mux 8 mux 8 3 adc0_x[2] adc0_x[1] mux 8 mux 8 (ch 88?95) (ch 64?71) (ch 80?87) (ch 72?79)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 717 28.2 introduction the analog-to-digital converter (adc ) block provides accurate and fast conversions for a wide range of applications. the adc contains advanced features for normal or injected conversion. it provides support for edma (direct memory access) mode operation. a conversion can be triggered by software or hardware (cross triggering unit or pit). there are three types of input channels: ? internal precision, adc x _p[ n ] (internally multiplexed precision channels) ? internal standard, adc x _s[ n ] (internally multiplexed standard channels) ? external adc x _x[ n ] (externally multiplexed standard channels) the mask registers present within the adc can be programmed to configure wh ich channel has to be converted. three external decode signals ma[2 :0] (multiplexer addre ss) are provided for exte rnal channel selection and are available as alternate functions on gpio. the ma[0:2] are controlled by the adc itself and are set automatically by the hardware. a conversion timing register for configuring different sampling and c onversion times is as sociated to each channel type. analog watchdogs allow conti nuous hardware monitoring. 28.3 functional description 28.3.1 analog channel conversion three conversion modes are available within the adc: ? normal conversion ? injected conversion ? ctu triggered conversion 28.3.1.1 normal conversion this is the normal conversion that the user program s by configuring the normal conversion mask registers (ncmr). each channel can be individually enable d by setting 1 in the co rresponding field of ncmr registers. mask registers must be programmed before starting the conve rsion and cannot be changed until the conversion of all the sel ected channels ends (nstart bit in the main status register (msr) is reset). 28.3.1.2 start of normal conversion the conversion chain starts when the nstart bit in the main configuration register (mcr) is set.
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 718 freescale semiconductor the msr[nstart] status bit is automatically set when the normal conversion starts. at the same time the mcr[nstart] bit is reset, allo wing the software to program a new start of conversion. in that case the new requested conversion starts afte r the running conversion is completed. if the content of all the normal conversion mask regi sters is zero (that is, no channel is selected) the conversion operation is c onsidered completed and the interrupt ech (see chapter 18, interrupt controller (intc) , for further details) is immediately issued after the start of conversion. 28.3.1.3 normal conversion operating modes two operating modes are available for the normal conversion: ? one shot ?scan to enter one of these modes, it is necessary to program the mcr[mode] bit. the first phase of the conversion process involves sampling the analog channel and the next phase involves the conversion phase when the sampled analog value is c onverted to digital as shown in figure 28-2 . figure 28-2. normal conversion flow in one shot mode (mode = 0) a sequential conversion specified in the ncmr registers is performed only once. at the end of ea ch conversion, the digital re sult of the conversion is stored in the corresponding data register. example 28-1. one shot mode (mode = 0) channels a-b-c-d-e-f-g-h are present in the devi ce where channels b-d-e are to be converted in the one shot mode. mode = 0 is set for one s hot mode. conversion star ts from the channel b followed by conversion of channels d-e. at the end of conversion of ch annel e the scanning of channels stops. the nstart status bit in the msr is automatically set when the normal convers ion starts. at the same time the mcr[nstart] bit is reset, allowing the softwa re to program a new start of conversion. in that case the new requested conversion starts after the running conversion is completed. in scan mode (mode = 1), a sequential conversion of n cha nnels specified in the ncmr registers is continuously performed. as in the pr evious case, at the end of each c onversion the digital result of the conversion is stored into th e corresponding data register. the msr[nstart] status bit is automatically set wh en the normal conversion starts. unlike one shot mode, the mcr[nstart] bit is not reset. it can be reset by software when the user needs to stop scan mode. in that case, the adc completes the current s can conversion and, after th e last conversion, also resets the msr[nstart] bit. sample b convert b sample c sample d convert d sample e convert e convert c
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 719 example 28-2. scan mode (mode = 1) channels a-b-c-d-e-f-g-h are present in the devi ce where channels b-d-e are to be converted in the scan mode. mode = 1 is se t for scan mode. conversion starts from the channel b followed by conversion of the channels d-e. at the end of conversion of ch annel e the scanning of channel b starts followed by conversion of the channels d-e. this sequence repeats itself till the mcr[nstart] bit is cleared by software. at the end of each conversion an end of conversion interr upt is issued (if enab led by the corresponding mask bit) and at the end of the co nversion sequence an end of chain inte rrupt is issued (if enabled by the corresponding mask bit in the imr register). 28.3.1.4 injected channel conversion a conversion chain can be injected into the ongoi ng normal conversion by configuring the injected conversion mask registers (jcmr). as normal conversion, each channe l can be individually selected. this injected conversion (which can only occur in one shot mode ) interrupts the normal conversion (which can be in one shot or scan mode). when an injected conversion is inserted, ongoing normal channel conversion is aborted and the injected channel request is processe d. after the last channel in the injected chain is converted, normal conversion resume s from the channel at which the normal conversion was aborted as shown in figure 28-3 . figure 28-3. injected sample/conversion sequence the injected conversion can be started using two options: ? by software setting the mcr[jstart]; the curren t conversion is suspended and the injected chain is converted. at the end of the chain, the jstart bit in the msr is reset and the normal chain conversion is resumed. ? by an internal trigger signal from the pit when mcr[jtrgen] is se t; a programmed event (rising/falling edge depending on mcr[jedge]) on the signal coming fr om pit starts the injected conversion by setting the msr[jstart]. at the end of the chain, the msr[jstart] is cleared and the normal conversion chain is resumed. the msr[jstart] is automatically set when the in jected conversion starts. at the same time the mcr[jstart] is reset, allowing the software to program a new start of conversion. in that case the new requested conversion starts after the r unning injected convers ion is completed. the ongoing channel conversion is interrupted and the injected conversion chain is processed first. after the injected chain is converted the normal chain conversion resumes from the channel at which normal conversion was aborted. injected conversion of channels i and j normal conversion resumes from the last aborted channel. sample b convert b sample c sample d convert d sample e convert e convert c sample c abort c sample i sample j convert j sample c convert c convert i
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 720 freescale semiconductor at the end of each injected conversion, an end of in jected conversion (jeoc) interrupt is issued (if enabled by the imr[mskjeoc]) and at the end of the sequence an end of injected chain (jech) interrupt is issued (if enabled by the imr[mskjeoc]). if the content of all the injected c onversion mask registers (j cmr) is zero (that is, no channel is selected) the jech interrupt is immediately i ssued after the start of conversion. 28.3.1.5 abort conversion two different abort functions are provided. ? the user can abort the ongoing conversion by setting the mcr[abort] bit. the current conversion is aborted and the conve rsion of the next channel of th e chain is immediately started. in the case of an abort operation, the nstart/jst art bit remains set and the abort bit is reset after the conversion of the next channel starts . the eoc interrupt corr esponding to the aborted channel is not generated. this beha vior is true for normal or inject ed conversion modes. if the last channel of a chain is aborted, the end of ch ain is reported generating an ech interrupt. ? it is also possible to abort the current chai n conversion by setting the mcr[abortchain] bit. in that case the behavior of the adc depends on the mode bit. if scan mode is disabled, the nstart bit is automatically reset together with the mcr[abortchain] bit. otherwise, if the scan mode is enabled, a new ch ain conversion is started. the eoc interrupt of the current aborted conversion is not generated but an ech interrupt is generated to signal the end of the chain. when a chain conversion abort is requested (a bortchain bit is set) while an injected conversion is running over a suspended normal conversion, both injected chain and normal conversion chain are aborted (both the nsta rt and jstart bits are also reset). 28.3.2 analog clock generator and conversion timings the clock frequency can be selected by programming the mcr[ adclksel]. when this bit is set to 1 the adc clock has the same freque ncy as the peripheral set 3 clock. otherw ise, the adc clock is half of the peripheral set 3 clock frequency. the adclksel bit can be written onl y in power-down mode. when the internal divider is not enabled (adcclksel = 1), it is important th at the associated clock divider in the clock generation module is 1. this is needed to ensure 50% clock duty cycle. in all other cases, the adc should us e the clock divided by two internally. 28.3.3 adc sampling and conversion timing in order to support different loading and switching times, several different conversion timing registers (ctr) are present. there is one register per cha nnel type. inplatch and in pcmp configurations are limited when the system clock fr equency is greater than 20 mhz. when a conversion is started, the adc connects the in ternal sampling capacitor to the respective analog input pin, allowing the capac itance to charge up to the input voltage value. the time to load the capacitor is referred to as sampling time. after completion of the sampling phase, the evalua tion phase starts and all the bits corresponding to the resolution of the adc are estimated to provide the conversion result.
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 721 the conversion times are programmed via the bit fields of the ctr. bit fields inplatch, inpcmp, and inpsamp are used to define the total conversion duration (t conv ) and in particular the partition between sampling phase duration (t sample ) and total evaluation phase duration (t eval ). 28.3.3.1 adc_0 figure 28-4 represents the sampling and conversion sequence. figure 28-4. sampling and conversion timings the sampling phase duration is: where ndelay is equal to 0.5 if inpsamp is less than or equal to 06h, otherwise it is 1. inpsamp must be greater than or equal to 3 (hardware requirement). the total evaluation phase duration is: inpcmp must be greater than or equal to 1 and inplatch must be less than incmp (hardware requirements). the total conversion duration is (not including external multiplexing): the timings refer to the unit t ck , where f ck = (1/2 adc peripheral set clock). 0.5 cycles 2.5 cycles sampling phase successive approximation / evaluation phase 10 cycles latching phase: the capacitors field input switch is opened note: operating conditions ? inplatch = 0, inpsam p = 3, inpcmp = 1 and fadc clk = 20 mhz end of conversion t sample inpsamp ndelay ? ?? t ck ? = inpsamp 3 ? ? 10 inpcmp t ck ? ?? ? == inpcmp 1 ? ?? and inplatch inpcmp ? ?? ? ?? ++ =
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 722 freescale semiconductor 28.3.3.2 adc_1 figure 28-5 represents the sampling and conversion sequence. figure 28-5. sampling and conversion timings table 28-1. adc sampling and conver sion timing at 5 v / 3.3 v for adc_0 clock (mhz) t ck ( ? s) inpsample 1 1 where: inpsample ? 3 ndelay 2 2 where: inpsamp ? 6, n = 0.5; inpsamp > 6, n = 1 t sample 3 3 where: t sample = (inpsamp-n)t ck ; must be ? 500 ns t sample /t ck inpcmp t eval ( ? s) inplatch t conv ( ? s) t conv / t ck 6 0.167 4 0.5 0.583 3.500 1 1.667 0 2.333 14.000 7 0.143 4 0.5 0.500 3.500 1 1.429 0 2.000 14.000 8 0.125 5 0.5 0.563 4.500 1 1.250 0 1.875 15.000 16 0.063 9 1 0.500 8.000 1 0.625 0 1.188 19.000 32 0.031 17 1 0.500 16.000 2 0.625 1 1.156 37.000 table 28-2. max/min adc_clk frequency and related configuration settings at 5 v / 3.3 v for adc_0 inpcmp inplatch max f adc_clk min f adc_clk 00/01 0 20 + 4% 6 1?? 10 0 ? ? 132+4%6 11 0 ? ? 132+4%9 0.5 cycles 2.5 cycles sampling phase successive approximation / evaluation phase 10 cycles latching phase: the capacitors field input switch is opened note: operating conditions ? inplatch = 0, inpsam p = 3, inpcmp = 1 and fadc clk = 20 mhz end of conversion
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 723 the sampling phase duration is: where n delay is equal to 0.5 if inpsamp is less than or equal to 06h, otherwise it is 1. inpsamp must be greater than or equal to 8 (hardware requirement). the total evaluation phase duration is: where: the total conversion duration is (not including external multiplexing): the timings refer to the unit t ck , where f ck = (1/2 adc peripheral set clock). table 28-3. adc sampling and con version timing at 5 v for adc_1 clock (mhz) t ck ( ? s) inpsample 1 1 where: inpsample ? 8 ndelay 2 2 where: inpsamp ? 6, n = 0.5; inpsamp > 6, n = 1 t sample 3 3 where: t sample = (inpsamp-n)t ck ; must be ? 500 ns t sample /t ck inpcmp t eval ( ? s) inplatch t conv ( ? s) t conv / t ck 4 0.250 8 1 1.750 7.000 1 3.000 1 5.000 20.000 5 0.200 8 1 1.400 7.000 1 2.400 1 4.000 20.000 6 0.167 8 1 1.167 7.000 1 2.000 1 3.333 20.000 7 0.143 8 1 1.000 7.000 1 1.714 1 2.857 20.000 8 0.125 8 1 0.875 7.000 1 1.500 1 2.500 20.000 16 0.063 9 1 0.500 8.000 2 1.500 1 2.063 33.000 32 0.031 17 1 0.500 16.000 0 1.500 1 2.031 65.000 t sample inpsamp 1 ? ?? t ck ? = inpsamp 8 ? t eval 12 t biteval ? = t biteval inpcmp t ck ? =ifinpcmp1 ? ?? t biteval 4t ck ? =ifinpcmp0 = ?? t conv t sample t eval t ck ++ =
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 724 freescale semiconductor table 28-4. adc sampling and conversion timing at 3.3 v for adc_1 clock (mhz) t ck ( ? s) inpsample 1 ndelay 2 t sample 3 t sample /t ck inpcmp t eval ( ? s) inplatch t conv ( ? s) t conv / t ck 4 0.250 8 1 1.750 7.000 1 3.000 1 5.000 20.000 5 0.200 8 1 1.400 7.000 1 2.400 1 4.000 20.000 7 0.143 8 1 1.000 7.000 2 3.429 1 4.571 32.000 8 0.125 8 1 0.875 7.000 2 3.000 1 4.000 32.000 16 0.063 11 1 0.625 10.000 0 3.000 1 3.688 59.000 20 0.050 13 1 0.600 12.000 0 2.400 1 3.050 61.000 1 where: inpsample ? 8 2 where: inpsamp ? 6, n = 0.5; inpsamp > 6, n = 1 3 where: t sample = (inpsamp-n)t ck ; must be ? 600 ns table 28-5. max/min adc_clk frequency and related configuration settings at 5 v for adc_1 inpcmp inplatch max f adc_clk min f adc_clk 00 0 16 + 4% 13.33 1 32 + 4% 13.33 01 0/1 8 + 4% 3.33 10 0 8 + 4% 6.67 1 16 + 4% 6.67 11 0 16 + 4% 10 1 24 + 4% 10 table 28-6. max/min adc_clk frequency and related configuration settings at 3.3 v for adc_1 inpcmp inplatch max f adc_clk min f adc_clk 00 0 not allowed not allowed 1 20 + 4% 13.33 01 0/1 5 + 4% 3.33 10 0 not allowed not allowed 1 10 + 4% 6.67 11 0 10 + 4% 10 1 15 + 4% 10
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 725 28.3.4 adc ctu (cross triggering unit) 28.3.4.1 overview the adc cross triggering unit (ctu) is added to enhance the injected conversion capability of the adc. the ctu is triggered by multiple input events (emios and pit) and can be used to se lect the channels to be converted from the appropriate event configuration register. a si ngle channel is converted for each request. the ctu can be enabled by setting mcr[ctuen]. the ctu and the adc are synchronous with the peripheral set 3 clock in both cases. 28.3.4.2 ctu in trigger mode in ctu trigger mode, normal and injected conv ersions triggered by the cpu are still enabled. once the ctu event configuration register (ctu_evtcfgr x ) is configured and the corresponding trigger from the emios or pit is received, the conversion starts. the msr[ctustart] is set automatically at this point and it is also automa tically reset when the ctu triggered conversion is completed. if an injected conversion (programmed by the us er by setting the jstart bit) is ongoing and ctu conversion is triggere d, then the injected channel conversion ch ain is aborted and onl y the ctu triggered conversion proceeds. by aborting the injected conv ersion, the msr[jstart] is reset. that abort is signaled through the status bit msr[jabort]. if a normal conversion is ongoing a nd a ctu conversion is triggered, then any ongoi ng channel conversion is aborted and the ctu triggered conversion is proc essed. when it is finished, the normal conversion resumes from the channel at whic h the normal conversion was aborted. if another ctu conversion is triggered before the end of the current ctu triggered conversion, the new request is discarded. when a normal conversion is requested during ctu conversion (ctustart bit = 1), the normal conversion starts when ctu conversion is complete d (ctustart = 0). otherwise, when an injected conversion is requested during ctu conversion, the injected c onversion is discarded and the mcr[jstart] is immediately reset. 28.3.5 presampling 28.3.5.1 introduction presampling is used to precharge or discharge the adc internal capacitor before it starts sampling of the analog input coming from the input pins. this is us eful for resetting information regarding the last converted data or to have more accurate control of conversion speed. during presampling, the adc samples the internally generated voltage.
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 726 freescale semiconductor presampling can be enabled/disabled on a channel basis by setting the corresponding bits in the psr registers. after enabling the presampling for a channel, the normal sequence of operation will be presampling + sampling + conversion for that channe l. sampling of the channel can be bypassed by setting the preconv bit in the pscr. when sampli ng of a channel is bypassed, the sampled data of internal voltage in the presampling state is converted ( figure 28-6 , figure 28-7 ). figure 28-6. presampling sequence figure 28-7. presampling sequence with preconv = 1 28.3.5.2 presampling cha nnel enable signals it is possible to select between two internally gene rated voltages v0 and v1 de pending on the value of the pscr[preval] as shown in table 28-7 . three presampling value fields, one per channel type, in the pscr make it possible to select different presampling values for each type. 28.3.6 programmable analog watchdog 28.3.6.1 introduction the analog watchdogs are used for determining whether the result of a channel conversion lies within a given guarded area (as shown in figure 28-8 ) specified by upper and lower threshold values named thrh and thrl, respectively. table 28-7. presampling voltage selection based on preval x fields pscr[preval x ] presampling voltage 00 v0 = v ss_hv_adc0 or v ss_hv_adc1 01 v1 = v dd_hv_adc0 or v dd_hv_adc1 10 reserved 11 reserved presampling is enabled in the channel c and d. for channel b total conversion clock cycles = (s) + (c). for channel c and d total conversion clock cycles = (p) + (s) + (c). sample b convert b presample c convert c presample d sample d convert d sample c sample e sample b convert b presample c presample d convert d sample e convert e convert c presampling enabled in channel c and d but sampling is bypass ed in these channels by setting preconv = 1 in the pscr. for channel c and d total conversion clock cycles = (p) + (c).
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 727 figure 28-8. guarded area after the conversion of the selected channel, a comparison is perfor med between the converted value and the threshold values. if the converted value lies outside that guarded area then corresponding threshold violation interrupts are generated. the comp arison result is stored as wtisr[wdg x h] and wtisr[wdg x l] as explained in table 28-8 . depending on the mask bits wtimr[mskwdg x l] and wtimr[mskwdg x h], an interrupt is generated on threshold violation. each channel can be enabled independently from the cwenr registers and can select the watchdog threshold registers (thrhlr x ) to be used by programming the cw selr registers. the threshold registers selected by the cwselr[wsel_ch x ] provides the threshold values. for example, if channel number 15 is to be monito red with the threshold values in thrhlr1, then cwselr[wsel_ch15] is programmed to select th rhlr1 to provide the threshold values. the channel monitoring is enabled by setting the bit corresponding to channel 15 in the cwenr. if a converted value for a particular channel lies outside the range spec ified by threshold values, then the corresponding bit is set in the analog watchdog out of range register (aworr). a set of threshold registers (thrhlr x ) can be linked to several adc ch annels. the threshold values to be selected for a channel need be programmed only once in the cwselr x . note if the higher threshold for the anal og watchdog is programmed lower than the lower threshold and the converted value is less than the lower threshold, then the wdg x l interrupt for the low threshold violation is set, else if the converted value is greater than the lower threshold (consequently also greater than the higher thres hold) then the interrupt wdg x h for high threshold violation is set. thus, the us er should avoid that situation as it could lead to misinterpretati on of the watchdog interrupts. table 28-8. values of wdg x h and wdg x l fields wdg x hwdg x l converted data 1 0 converted data > thrh 0 1 converted data < thrl 0 0 thrl ? converted data ? thrh thrh thrl analog voltage upper threshold lower threshold guarded area
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 728 freescale semiconductor 28.3.7 dma functionality a dma request can be programmed after the convers ion of every channel by setting the respective masking bit in the dmar register s. the dmar masking registers mu st be programmed before starting any conversion. there is one dmar per channel type and each adc module has one dma request associated with it. the dma transfers can be enabled using the dmaen bit of dmae register. when the dclr bit of dmae register is set then the dma request is clea red on the reading of the register for which dma transfer has been enabled. 28.3.8 interrupts the adc generates the following two maskable interrupt signals: ? adc_eoc interrupt requests ? eoc (end of conversion) ? ech (end of chain) ? jeoc (end of injected conversion) ? jech (end of injected chain) ? eoctu (end of ctu conversion) ?wdg x l and wdg x h (watchdog threshold) interrupt requests interrupts are generated during the conversion process to signal events such as end of conversion as explained in register descript ion for ceocfr[0..2]. two register s named ceocfr[0..2] (channel pending registers) and imr (interr upt mask register) are provided in order to check and enable the interrupt request to int module. interrupts can be individually enab led on a channel by channel basis by programming the cimr (channel interrupt mask register). several ceocfr[0..2] are also provided in order to signal which of the channels? measurement has been completed. the analog watchdog interrupts are handled by two re gisters, wtisr (watchdog threshold interrupt status register) and wtimr (watchdog threshold interrupt mask register ), in order to check and enable the interrupt request to the in tc module. the watchdog interrupt source sets two pending bits wdg x h and wdg x l in the wtisr for each of the channels being monitored. the ceocfr[0..2] contains the interr upt pending request status. if the us er wants to clear a particular interrupt event status, then writing a 1 to the corresponding stat us bit clears the pendi ng interrupt flag (at this write operation all the ot her bits of the ceocfr[0..2] must be maintained at 0). 28.3.9 external decode signals delay the adc provides several external decode signals to select which external channel has to be converted. in order to take into account the control switchi ng time of the external an alog multiplexer, a decode
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 729 signals delay register (dsd r) is provided. the delay between the decoding signal selection and the actual start of conversion can be program med by writing the field dsd[0:11]. after having selected the channel to be converted, the ma[0:2] control lines are automatically reset. for instance, in the event of normal scan conversion on anp[0] followed by anx[0,7] (adc ch 71) all the ma[0:2] bits are set a nd subsequently reset. 28.3.10 power-down mode the analog part of the adc can be put in low power mode by setting the mcr[pwdn]. after releasing the reset signal the adc analog module is kept in power-down mode by default, so this state must be exited before starting any operat ion by resetting the appr opriate bit in the mcr. the power-down mode can be request ed at any time by setting the mcr[pwdn]. if a conversion is ongoing, the adc must complete the conversion before entering the pow er down mode. in fact, the adc enters power-down mode only afte r completing the ongoing conversion. otherwise, the ongoing operation should be aborted manually by resetting the nstart bit and using the abortchain bit. msr[adcstatus] bit is set only wh en adc enters power-down mode. after the power-down phase is completed the proc ess ongoing before the power-down phase must be restarted manually by setting the appropriate mcr[start] bit. resetting mcr[pwdn] bit and setting mcr[nstart] or mcr[jstart] bit during the same cycle is forbidden. if a ctu trigger pulse is received during power-down, it is discarded. if the ctu is enabled and the csr[ctustart] bi t is 1, then the mcr[pwdn] bit cannot be set. when ctu trigger mode is enabled, the application has to wait for the end of conversion (ctustart bit automatically reset). 28.3.11 auto-clock-off mode to reduce power consumption during the idle mode of operation (without going into power-down mode), an auto-clock-off feature can be enabled by setti ng the mcr[acko] bit. when enabled, the analog clock is automatically switched off when no operation is ongoing, that is, no conversi on is programmed by the user. note the auto-clock-off feature cannot operate when the digital interface runs at the same rate as the analog in terface. this means that when mcr.adcclksel = 1, the analog clock will not shut down in idle mode.
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 730 freescale semiconductor 28.4 register descriptions 28.4.1 introduction MPC5606BK has two adcs (10-bit adc_0 and 12-bit adc_1) and each has specific registers. table 28-9 lists the adc_0 registers with thei r address offsets and reset values. table 28-9. 10-bit adc_0 digital registers base address: 0xffe0_0000 location address offset register name 0x0000 main configuration register (mcr) on page 737 0x0004 main status register (msr) on page 739 0x0008?0x000f reserved ? 0x0010 interrupt status register (isr) on page 740 0x0014 channel pending register (ceocfr0) on page 741 0x0018 channel pending register (ceocfr1) on page 741 0x001c channel pending register (ceocfr2) on page 741 0x0020 interrupt mask register (imr) on page 743 0x0024 channel interrupt mask register (cimr0) on page 744 0x0028 channel interrupt mask register (cimr1) on page 744 0x002c channel interrupt mask register (cimr2) on page 744 0x0030 watchdog threshold interrupt status register (wtisr) on page 746 0x0034 watchdog threshold interrupt mask register (wtimr) on page 747 0x0038?0x003f reserved ? 0x0040 dma enable register (dmae) on page 748 0x0044 dma channel select register 0 () on page 749 0x0048 dma channel select register 1 (dmar1) on page 749 0x004c dma channel select register 2 (dmar2) on page 749 0x0050?0x005f reserved ? 0x0060 threshold register 0 (thrhlr0) on page 752 0x0064 threshold register 1 (thrhlr1) on page 752 0x0068 threshold register 2 (thrhlr2) on page 752 0x006c threshold register 3 (thrhlr3) on page 752 0x0070?0x007f reserved ? 0x0080 presampling control register (pscr) on page 753 0x0084 presampling register 0 (psr0) on page 753
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 731 0x0088 presampling register 1 (psr1) on page 753 0x008c presampling register 2 (psr2) on page 753 0x0090?0x0093 reserved ? 0x0094 conversion timing register 0 (ctr0) on page 756 0x0098 conversion timing register 1 (ctr1) on page 756 0x009c conversion timing register 2 (ctr2) on page 756 0x00a0?0x00a3 reserved ? 0x00a4 normal conversion mask register 0 (ncmr0) on page 757 0x00a8 normal conversion mask register 1 (ncmr1) on page 757 0x00ac normal conversion mask register 2 (ncmr2) on page 757 0x00b0?0x00b3 reserved ? 0x00b4 injected conversion mask register 0 (jcmr0) on page 760 0x00b8 injected conversion mask register 1 (jcmr1) on page 760 0x00bc injected conversion mask register 2 (jcmr2) on page 760 0x00c0?0x00c3 reserved ? 0x00c4 decode signals delay register (dsdr) on page 761 0x00c8 power-down exit delay register (pdedr) on page 762 0x00cc?0x00ff reserved ? 0x0100 channel 0 data register (cdr0) on page 763 0x0104 channel 1 data register (cdr1) on page 763 0x0108 channel 2 data register (cdr2) on page 763 0x010c channel 3 data register (cdr3) on page 763 0x0110 channel 4 data register (cdr4) on page 763 0x0114 channel 5 data register (cdr5) on page 763 0x0118 channel 6 data register (cdr6) on page 763 0x011c channel 7 data register (cdr7) on page 763 0x0120 channel 8 data register (cdr8) on page 763 0x0124 channel 9 data register (cdr9) on page 763 0x0128 channel 10 data register (cdr10) on page 763 0x012c channel 11 data register (cdr11) on page 763 0x0130 channel 12 data register (cdr12) on page 763 table 28-9. 10-bit adc_0 digital registers (continued) base address: 0xffe0_0000 location address offset register name
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 732 freescale semiconductor 0x0134 channel 13 data register (cdr13) on page 763 0x0138 channel 14 data register (cdr14) on page 763 0x013c channel 15 data register (cdr15) on page 763 0x0140?0x017f reserved ? 0x0180 channel 32 data register (cdr32) on page 763 0x0184 channel 33 data register (cdr33) on page 763 0x0188 channel 34 data register (cdr34) on page 763 0x018c channel 35 data register (cdr35) on page 763 0x0190 channel 36 data register (cdr36) on page 763 0x0194 channel 37 data register (cdr37) on page 763 0x0198 channel 38 data register (cdr38) on page 763 0x019c channel 39 data register (cdr39) on page 763 0x01a0 channel 40 data register (cdr40) on page 763 0x01a4 channel 41 data register (cdr41) on page 763 0x01a8 channel 42 data register (cdr42) on page 763 0x01ac channel 43 data register (cdr43) on page 763 0x01b0 channel 44 data register (cdr44) on page 763 0x01b4 channel 45 data register (cdr45) on page 763 0x01b8 channel 46 data register (cdr46) on page 763 0x01bc channel 47 data register (cdr47) on page 763 0x01c0 channel 48 data register (cdr48) on page 763 0x01c4 channel 49 data register (cdr49) on page 763 0x01c8 channel 50 data register (cdr50) on page 763 0x01cc channel 51 data register (cdr51) on page 763 0x01d0 channel 52 data register (cdr52) on page 763 0x01d4 channel 53 data register (cdr53) on page 763 0x01d8 channel 54 data register (cdr54) on page 763 0x01dc channel 55 data register (cdr55) on page 763 0x01e0 channel 56 data register (cdr56) on page 763 0x01e4 channel 57 data register (cdr57) on page 763 0x01e8 channel 58 data register (cdr58) on page 763 table 28-9. 10-bit adc_0 digital registers (continued) base address: 0xffe0_0000 location address offset register name
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 733 0x01ec channel 59 data register (cdr59) on page 763 0x01f0?0x01ff reserved ? 0x0200 channel 64 data register (cdr64) on page 763 0x0204 channel 65 data register (cdr65) on page 763 0x0208 channel 66 data register (cdr66) on page 763 0x020c channel 67 data register (cdr67) on page 763 0x0210 channel 68 data register (cdr68) on page 763 0x0214 channel 69 data register (cdr69) on page 763 0x0218 channel 70 data register (cdr70) on page 763 0x021c channel 71 data register (cdr71) on page 763 0x0220 channel 72 data register (cdr72) on page 763 0x0224 channel 73 data register (cdr73) on page 763 0x0228 channel 74 data register (cdr74) on page 763 0x022c channel 75 data register (cdr75) on page 763 0x0230 channel 76 data register (cdr76) on page 763 0x0234 channel 77 data register (cdr77) on page 763 0x0238 channel 78 data register (cdr78) on page 763 0x023c channel 79 data register (cdr79) on page 763 0x0240 channel 80 data register (cdr80) on page 763 0x0244 channel 81 data register (cdr81) on page 763 0x0248 channel 82 data register (cdr82) on page 763 0x024c channel 83 data register (cdr83) on page 763 0x0250 channel 84 data register (cdr84) on page 763 0x0254 channel 85 data register (cdr85) on page 763 0x0258 channel 86 data register (cdr86) on page 763 0x025c channel 87 data register (cdr87) on page 763 0x0260 channel 88 data register (cdr88) on page 763 0x0264 channel 89 data register (cdr89) on page 763 0x0268 channel 90 data register (cdr90) on page 763 0x026c channel 91 data register (cdr91) on page 763 0x0270 channel 92 data register (cdr92) on page 763 table 28-9. 10-bit adc_0 digital registers (continued) base address: 0xffe0_0000 location address offset register name
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 734 freescale semiconductor table 28-10 lists the adc_1 registers with thei r address offsets and reset values. 0x0274 channel 93 data register (cdr93) on page 763 0x0278 channel 94 data register (cdr94) on page 763 0x027c channel 95 data register (cdr95) on page 763 0x0280 threshold register 4 (thrhlr4) on page 763 0x0284 threshold register 5 (thrhlr5) on page 763 0x0288?0x02af reserved ? 0x02b0 channel watchdog selection register 0 (cwselr0) on page 765 0x02b4 channel watchdog selection register 1 (cwselr1) on page 765 0x02b8?0x02bf reserved ? 0x02c0 channel watchdog selection register 4 (cwselr4) on page 765 0x02c4 channel watchdog selection register 5 (cwselr5) on page 765 0x02c8 channel watchdog selection register 6 (cwselr6) on page 765 0x02cc channel watchdog selection register 7 (cwselr7) on page 765 0x02d0 channel watchdog selection register 8 (cwselr8) on page 765 0x02d4 channel watchdog selection register 9 (cwselr9) on page 765 0x02d8 channel watchdog selection register 10 (cwselr10) on page 765 0x02dc channel watchdog selection register 11 (cwselr11) on page 765 0x02e0 channel watchdog enable register 0 (cwenr0) on page 773 0x02e4 channel watchdog enable register 1 (cwenr1) on page 773 0x02e8 channel watchdog enable register 2 (cwenr2) on page 773 0x02ec?0x02ef reserved ? 0x02f0 analog watchdog out of range register 0 (aworr0) on page 775 0x02f4 analog watchdog out of range register 1 (aworr1) on page 775 0x02f8 analog watchdog out of range register 2 (aworr2) on page 775 0x2fc?0x02ff reserved ? table 28-9. 10-bit adc_0 digital registers (continued) base address: 0xffe0_0000 location address offset register name
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 735 table 28-10. 12-bit adc_1 digital registers base address: 0xffe0_4000 location address offset register name 0x0000 main configuration register (mcr) on page 737 0x0004 main status register (msr) on page 739 0x0008?0x000f reserved ? 0x0010 interrupt status register (isr) on page 740 0x0014 channel pending register (ceocfr0) on page 741 0x0018 channel pending register (ceocfr1) on page 741 0x001c reserved ? 0x0020 interrupt mask register (imr) on page 743 0x0024 channel interrupt mask register 0 (cimr0) on page 744 0x0028 channel interrupt mask register 1 (cimr1) on page 744 0x002c reserved ? 0x0030 watchdog threshold interrupt status register (wtisr) on page 746 0x0034 watchdog threshold interrupt mask register (wtimr) on page 747 0x0038?0x003f reserved ? 0x0040 dma enable register (dmae) on page 748 0x0044 dma channel select register 0 (dmar0) on page 748 0x0048 dma channel select register 1 (dmar1) on page 748 0x004c reserved ? 0x0060 threshold register 0 (thrhlr0) on page 752 0x0064 threshold register 1 (thrhlr1) on page 752 0x0068 threshold register 2 (thrhlr2) on page 752 0x006c?0x007f reserved ? 0x0080 presampling control register (pscr) on page 753 0x0084 presampling register 0 (psr0) on page 753 0x0088 presampling register 1 (psr1) on page 753 0x008c?0x0093 reserved ? 0x0094 conversion timing register 0 (ctr0) on page 756 0x0098 conversion timing register 1(ctr1) on page 756 0x009c?0x00a3 reserved ? 0x00a4 normal conversion mask register 0 (ncmr0) on page 757 0x00a8 normal conversion mask register 1 (ncmr1) on page 757
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 736 freescale semiconductor 0x00a8?0x00ac reserved ? 0x00b4 injected conversion mask register 0 (jcmr0) on page 760 0x00b8 injected conversion mask register 1 (jcmr1) 0x00bc?0x00c7 reserved ? 0x00c8 power-down exit delay register (pdedr) on page 762 0x00cc?0x00ff reserved ? 0x0100 channel 0 data register (cdr0) on page 763 0x0104 channel 1 data register (cdr1) on page 763 0x0108 channel 2 data register (cdr2) on page 763 0x010c channel 3 data register (cdr3) on page 763 0x0110 channel 4 data register (cdr4) on page 763 0x0114 channel 5 data register (cdr5) on page 763 0x0118 channel 6 data register (cdr6) on page 763 0x011c channel 7 data register (cdr7) on page 763 0x0120 channel 8 data register (cdr8) on page 763 0x0124 channel 9 data register (cdr9) on page 763 0x0128 channel 10 data register (cdr10) on page 763 0x012c channel 11 data register (cdr11) on page 763 0x0130 channel 12 data register (cdr12) on page 763 0x0134 channel 13 data register (cdr13) on page 763 0x0138 channel 14 data register (cdr14) on page 763 0x013c channel 15 data register (cdr15) on page 763 0x0140?0x017f reserved ? 0x0180 channel 32 data register (cdr32) on page 763 0x0184 channel 33 data register (cdr33) on page 763 0x0188 channel 34 data register (cdr34) on page 763 0x018c channel 35 data register (cdr35) on page 763 0x0190 channel 36 data register (cdr36) on page 763 0x0194 channel 37 data register (cdr37) on page 763 0x0198 channel 38 data register (cdr38) on page 763 0x019c channel 39 data register (cdr39) on page 763 table 28-10. 12-bit adc_1 digital registers (continued) base address: 0xffe0_4000 location address offset register name
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 737 28.4.2 control logic registers 28.4.2.1 main configuration register (mcr) the main configuration register (mcr) pr ovides configuration settings for the adc. 0x01a0?0x02af reserved ? 0x02b0 channel watchdog selection register 0 (cwselr0) on page 765 0x02b4 channel watchdog selection register 1 (cwselr1) on page 765 0x02b8?0x02bf reserved ? 0x02c0 channel watchdog selection register 4 (cwselr4) on page 765 0x02c4?0x02df reserved ? 0x02e0 channel watchdog enable register 0 (cwenr0) on page 773 0x02e4 channel watchdog enable register 1 (cwenr1) on page 773 0x02f0 analog watchdog out of range register 0 (aworr0) on page 775 0x02f4 analog watchdog out of range register 1 (aworr1) on page 775 0x02f8?0x02ff reserved ? address: base + 0x0000 access: user read/write 0123456789101112131415 r owren wlside mode 0000 nstart 0 jtrgen jedge jstart 00 ctuen 0 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 adclk sel abort chain abort acko 0000 pwdn w reset00000000 00000001 figure 28-9. main configuration register (mcr) table 28-10. 12-bit adc_1 digital registers (continued) base address: 0xffe0_4000 location address offset register name
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 738 freescale semiconductor table 28-11. mcr field descriptions field description owren overwrite enable this bit enables or disables the functionality to overwrite unread converted data. 0 prevents overwrite of unread conver ted data; new result is discarded 1 enables converted data to be overwritten by a new conversion wlside write left/right-aligned 0 the conversion data is written right-aligned. 1 data is left-aligned (from 15 to (15 ? resolution + 1)). the wlside bit affects all the cdr registers simultaneously. see figure 28-48 and figure 28-48 . mode one shot/scan 0 one shot mode?configures the normal conversion of one chain. 1 scan mode?configures continuous chain co nversion mode; when the programmed chain conversion is finished it restarts immediately. nstart normal start conversion setting this bit starts the chain or scan conversi on. resetting this bit during scan mode causes the current chain conversion to finish, then stops the operation. this bit stays high while the conversion is ongoing (or pending during injection mode). 0 causes the current chain conversion to finish and stops the operation 1 starts the chain or scan conversion jtrgen injection external trigger enable 0 external trigger disabled for channel injection 1 external trigger enabled for channel injection jedge injection trigger edge selection edge selection for external trigger, if jtrgen = 1. 0 selects falling edge for the external trigger 1 selects rising edge for the external trigger jstart injection start setting this bit will start the configured injected analog channels to be converted by software. resetting this bit has no effect, as the inje cted chain conversion cannot be interrupted. ctuen cross trigger unit conversion enable 0 ctu triggered conversion disabled 1 ctu triggered conversion enabled adclksel analog clock select this bit can only be written when adc in power-down mode 0 adc clock frequency is half peripheral set clock frequency 1 adc clock frequency is equal to peripheral set clock frequency abortchain abort chain when this bit is set, the ongoing chain conversion is aborted. this bit is reset by hardware as soon as a new conversion is requested. 0 conversion is not affected 1 aborts the ongoing chain conversion abort abort conversion when this bit is set, the ongoing conversion is aborted and a new conversion is invoked. this bit is reset by hardware as soon as a new conversion is invoked. if it is set during a scan chain, only the ongoing conversion is aborted and the next conversion is performed as planned. 0 conversion is not affected 1 aborts the ongoing conversion
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 739 28.4.2.2 main status register (msr) the main status register (msr) pr ovides status bits for the adc. acko auto-clock-off enable if set, this bit enables the auto clock off feature. 0 auto clock off disabled 1 auto clock off enabled pwdn power-down enable when this bit is set, the analog module is requested to enter power down mode. when adc status is pwdn, resetting this bit starts adc transition to idle mode. 0 adc is in normal mode 1 adc has been requested to power down address: base + 0x0004 access: user read-only 0123456789101112131415 r 0000000 nstart jabort 00 jstart 0 00 ctustart w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r chaddr 0 00 ack0 00 adcstatus w reset00000000 00000001 figure 28-10. main status register (msr) table 28-12. msr field descriptions field description nstart this status bit is used to signal that a normal conversion is ongoing. jabort this status bit is used to signal that an inje cted conversion has been aborted. this bit is reset when a new injected conversion starts. jstart this status bit is used to signal that an injected conversion is ongoing. ctustart this status bit is used to signal that a ctu conversion is ongoing. chaddr current conversion channel address this status field indicates current conversion channel address. acko auto-clock-off enable this status bit is used to signal if the auto-clock-off feature is on. table 28-11. mcr field descriptions (continued) field description
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 740 freescale semiconductor note msr[jstart] is automatically set when the injected conversion starts. at the same time mcr[jstart] is reset, allowing the software to program a new start of conversion. the jcmr registers do not change their values. 28.4.3 interrupt registers 28.4.3.1 interrupt status register (isr) the interrupt status register (isr) cont ains interrupt status bits for the adc. adcstatus the value of this par ameter depends on adc status: 000 idle ? the adc is powered up but idle. 001 power-down ? the adc is powered down. 010 wait state ? the adc is waiting for an external multiplexer, this only occurs when the dsdr register is non-zero. 011 reserved 100 sample ? the adc is sampling the analog signal. 101 reserved 110 conversion ? the adc is converting the sampled signal. 111 reserved address: base + 0x0010 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000 0 000 eo ctu jeoc jech eoc ech w w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-11. interrupt status register (isr) table 28-13. isr field descriptions field description eoctu end of ctu conversion interrupt flag when this bit is set, an eoctu interrupt has occurred. table 28-12. msr field descriptions (continued) field description
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 741 28.4.3.2 channel pending regi sters (ceocfr[0..2]) table 28-14 shows the available channels. jeoc end of injected channel conversion interrupt flag when this bit is set, a jeoc interrupt has occurred. jech end of injected chain conversion interrupt flag when this bit is set, a jech interrupt has occurred. eoc end of channel conversion interrupt flag when this bit is set, an eoc interrupt has occurred. ech end of chain conversion interrupt flag when this bit is set, an ech interrupt has occurred. table 28-14. ceocfr[0..2] register description adc register description adc_0 ceocfr0 end of conversion pending interrupt for channel 0 to 15 (precision channels) adc_0 ceocfr1 end of conversion pending interrup t for channel 32 to 59 (standard channels) adc_0 ceocfr2 end of conversion pending interrupt for channel 64 to 95 (external multiplexed channels) adc_1 ceocfr0 end of conversion pending interrupt for channel 0 to 15 (precision channels) adc_1 ceocfr1 end of conversion pending interrup t for channel 32 to 39 (standard channels) address: base + 0x0014 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ch15 eoc_ch14 eoc_ch13 eoc_ch12 eoc_ch11 eoc_ch10 eoc_ch9 eoc_ch8 eoc_ch7 eoc_ch6 eoc_ch5 eoc_ch4 eoc_ch3 eoc_ch2 eoc_ch1 eoc_ch0 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-12. channel pending register 0 (ceocfr0) table 28-13. isr field descriptions (continued) field description
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 742 freescale semiconductor address: base + 0x0018 access: user read/write 0123456789101112131415 r 0000 eoc_ch59 eoc_ch58 eoc_ch57 eoc_ch56 eoc_ch55 eoc_ch54 eoc_ch53 eoc_ch52 eoc_ch51 eoc_ch50 eoc_ch49 eoc_ch48 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ch47 eoc_ch46 eoc_ch43 eoc_ch44 eoc_ch43 eoc_ch42 eoc_ch41 eoc_ch40 eoc_ch39 eoc_ch38 eoc_ch37 eoc_ch36 eoc_ch35 eoc_ch34 eoc_ch33 eoc_ch32 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-13. channel pending register 1 (ceocfr1) ? adc_0 address: base + 0x0018 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 eoc_ch39 eoc_ch38 eoc_ch37 eoc_ch36 eoc_ch35 eoc_ch34 eoc_ch33 eoc_ch32 w w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-14. channel pending register 1 (ceocfr1) ? adc_1
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 743 note ceocfr2 is not implemented on adc_1. 28.4.3.3 interrupt mask register (imr) the interrupt mask register (imr) contains the interrupt enable bits for the adc. address: base + 0x001c access: user read/write 0123456789101112131415 r eoc_ch95 eoc_ch94 eoc_ch93 eoc_ch92 eoc_ch91 eoc_ch90 eoc_ch89 eoc_ch88 eoc_ch87 eoc_ch86 eoc_ch85 eoc_ch84 eoc_ch83 eoc_ch82 eoc_ch81 eoc_ch80 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eoc_ch79 eoc_ch78 eoc_ch77 eoc_ch76 eoc_ch75 eoc_ch74 eoc_ch73 eoc_ch72 eoc_ch71 eoc_ch70 eoc_ch69 eoc_ch68 eoc_ch67 eoc_ch66 eoc_ch65 eoc_ch64 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-15. channel pending register 2 (ceocfr2) table 28-15. ceocfr field descriptions field description eoc_chn when set, the measure of channel n is completed. address: base + 0x0020 access: user read/write 0123456789101112131415 r0000000 0 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 000 mske octu msk jeoc msk jech msk eoc msk ech w reset00000000 00000000 figure 28-16. interrupt mask register (imr)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 744 freescale semiconductor 28.4.3.4 channel interrupt mask register (cimr[0..2]) table 28-17 shows the available channels. table 28-16. interrupt mask register (imr) field descriptions field description mskeoctu mask for end of ctu conversion (eoctu) interrupt when set, the eoctu interrupt is enabled. mskjeoc mask for end of injected channel conversion (jeoc) interrupt when set, the jeoc interrupt is enabled. mskjech mask for end of injected chain conversion (jech) interrupt when set, the jech interrupt is enabled. mskeoc mask for end of channel conversion (eoc) interrupt when set, the eoc interrupt is enabled. mskech mask for end of chain conversion (ech) interrupt when set, the ech interrupt is enabled. adc register description adc_0 cimr0 enable bit for channel 0 to 15 (precision channels) adc_0 cimr1 enable bit for channel 32 to 59 (standard channels) adc_0 cimr2 enable bit for channel 64 to 95 (external multiplexed channels) adc_1 cimr0 enable bit for channel 0 to 15 (precision channels) adc_1 cimr1 enable bit for channel 32 to 39 (standard channels) table 28-17. cimr[0..2] register description address: base + 0x0024 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 15 cim 14 cim 13 cim 12 cim 11 cim 10 cim 9 cim 8 cim 7 cim 6 cim 5 cim 4 cim 3 cim 2 cim 1 cim 0 w reset00000000 00000000 figure 28-17. channel interrupt mask register 0 (cimr0)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 745 address: base + 0x0028 access: user read/write 0123456789101112131415 r0000 cim 59 cim 58 cim 57 cim 56 cim 55 cim 54 cim 53 cim 52 cim 51 cim 50 cim 49 cim 48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 47 cim 46 cim 43 cim 44 cim 43 cim 42 cim 41 cim 40 cim 39 cim 38 cim 37 cim 36 cim 35 cim 34 cim 33 cim 32 w reset00000000 00000000 figure 28-18. channel interrupt mask register 1 (cimr1) for adc_0 address: base + 0x0028 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 cim 39 cim 38 cim 37 cim 36 cim 35 cim 34 cim 33 cim 32 w reset00000000 00000000 figure 28-19. channel interrupt mask register 1 (cimr1) for adc_1 address: base + 0x002c access: user read/write 0123456789101112131415 r cim 95 cim 94 cim 93 cim 92 cim 91 cim 90 cim 89 cim 88 cim 87 cim 86 cim 85 cim 84 cim 83 cim 82 cim 81 cim 80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cim 79 cim 78 cim 77 cim 76 cim 75 cim 74 cim 73 cim 72 cim 71 cim 70 cim 69 cim 68 cim 67 cim 66 cim 65 cim 64 w reset00000000 00000000 figure 28-20. channel interrupt mask register 2 (cimr2)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 746 freescale semiconductor 28.4.3.5 watchdog threshold interr upt status register (wtisr) for adc_0 (10-bit) for adc_1 (12-bit) table 28-18. cimr field descriptions field description cim n interrupt enable when set (cim n = 1), interrupt for channel n is enabled. address: base + 0x0030 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 wdg 5h wdg 5l wdg 4h wdg 4l wdg 3h wdg 3l wdg 2h wdg 2l wdg 1h wdg 1l wdg 0h wdg 0l w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-21. adc_0 watchdog threshold interrupt status register (wtisr) table 28-19. adc_0 wtisr field descriptions field description wdg x h this corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold (for[ x =0..5). wdg x l this corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold (for[ x =0..5.)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 747 28.4.3.6 watchdog threshold inte rrupt mask register (wtimr) for adc_0 (10-bit): address: base + 0x0030 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000 wdg 2h wdg 2l wdg 1h wdg 1l wdg 0h wdg 0l w w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-22. adc_1 watchdog threshold interrupt status register (wtisr) table 28-20. adc_1 wtisr field descriptions field description wdg x h this corresponds to the interrupt generated on the converted value being higher than the programmed higher threshold (for [ x = 0..2]). wdg x l this corresponds to the interrupt generated on the converted value being lower than the programmed lower threshold (for [ x =0..2]). address: base + 0x0034 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000msk wdg 5h msk wdg 5l msk wdg 4h msk wdg 4l msk wdg 3h msk wdg 3l msk wdg 2h msk wdg 2l msk wdg 1h msk wdg 1l msk wdg 0h msk wdg 0l w reset00000000 00000000 figure 28-23. adc_0 watchdog threshold interrupt mask register (wtimr)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 748 freescale semiconductor for adc_1 (12-bit) 28.4.4 dma registers 28.4.4.1 dma enable register (dmae) the dma enable (dmae) register sets up the dma for use with the adc. table 28-21. adc_0 wtimr field descriptions field description 2 x + 1 mskwdg x h [ x = 0..5] this corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold. when set the interrupt is enabled. 2 x mskwdg x l [ x = 0..5]his corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower thres hold. when set the interrupt is enabled. address: base + 0x0034 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000msk wdg 2h msk wdg 2l msk wdg 1h msk wdg 1l msk wdg 0h msk wdg 0l w reset00000000 00000000 figure 28-24. adc_1 watchdog threshold interrupt mask register (wtimr) table 28-22. adc_1 wtimr field descriptions field description mskwdg x h this corresponds to the mask bit for the interrupt generated on the converted value being higher than the programmed higher threshold (for [ x = 0..2]). when set the interrupt is enabled. mskwdg x l this corresponds to the mask bit for the interrupt generated on the converted value being lower than the programmed lower threshold (for [ x = 0..2]). when set the interrupt is enabled.
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 749 28.4.4.2 dma channel select register (dmar[0..2]) table 28-24 shows the available channels. address: base + 0x0040 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 000000 dclr dmaen w reset00000000 00000000 figure 28-25. dma enable register (dmae) table 28-23. dmae field descriptions field description dclr dma clear sequence enable 0 dma request cleared by acknowledge from dma controller 1 dma request cleared on read of data registers dmaen dma global enable 0 dma feature disabled 1 dma feature enabled table 28-24. dmar[0..2] register description adc register description adc_0 dmar0 enable bits for channel 0 to 15 (precision channels) adc_0 dmar1 enable bits for channel 32 to 59 (standard channels) adc_0 dmar2 enable bits for channel 64 to 95 (external multiplexed channels) adc_1 dmar0 enable bits for channel 0 to 15 (precision channels) adc_1 dmar1 enable bit for channel 32 to 39 (standard channels)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 750 freescale semiconductor address: base + 0x0044 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dma 15 dma 14 dma 13 dma 12 dma 11 dma 10 dma 9 dma 8 dma 7 dma 6 dma 5 dma 4 dma 3 dma 2 dma 1 dma 0 w reset00000000 00000000 figure 28-26. dma channel select register 0 (dmar0) address: base + 0x0048 access: user read/write 0123456789101112131415 r0000 dma 59 dma 58 dma 57 dma 56 dma 55 dma 54 dma 53 dma 52 dma 51 dma 50 dma 49 dma 48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dma 47 dma 46 dma 43 dma 44 dma 43 dma 42 dma 41 dma 40 dma 39 dma 38 dma 37 dma 36 dma 35 dma 34 dma 33 dma 32 w reset00000000 00000000 figure 28-27. dma channel select register 1 (dmar1) for adc_0 address: base + 0x0048 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 dma 39 dma 38 dma 37 dma 36 dma 35 dma 34 dma 33 dma 32 w reset00000000 00000000 figure 28-28. dma channel select register 1 (dmar1) for adc_1
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 751 address: base + 0x004c access: user read/write 0123456789101112131415 r dma 95 dma 94 dma 93 dma 92 dma 91 dma 90 dma 89 dma 88 dma 87 dma 86 dma 85 dma 84 dma 83 dma 82 dma 81 dma 80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dma 79 dma 78 dma 77 dma 76 dma 75 dma 74 dma 73 dma 72 dma 71 dma 70 dma 69 dma 68 dma 67 dma 66 dma 65 dma 64 w reset00000000 00000000 figure 28-29. dma channel select register 2 (dmar2) table 28-25. dmarx field descriptions field description dma n dma enable when set (dma n = 1), channel n is enabled to transfer data in dma mode.
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 752 freescale semiconductor 28.4.5 threshold registers 28.4.5.1 threshold register (thrhlr) for adc_0 (10-bit): thrhlr[0..5] for adc_1 (12-bit): thrhlr[0..2] address: base + 0x0060 (thrhlr0) base + 0x0064 (thrhlr1) base + 0x0068 (thrhlr2) base + 0x006c (thrhlr3) base + 0x0280 (thrhlr4) base + 0x0284 (thrhlr5) access: user read/write 0123456789101112131415 r000000 thrh w reset00000011 11111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r000000 thrl w reset00000000 00000000 figure 28-30. adc_0 threshold register thrhlr[0..5] table 28-26. adc_0 thrhlr field descriptions field description thrh high threshold value for channel n . thrl low threshold value for channel n . address: base + 0x0060 (thrhlr0) base + 0x0064 (thrhlr1) base + 0x0068 (thrhlr2) access: user read/write 0123456789101112131415 r0000 thrh w reset00001111 11111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 thrl w reset00000000 00000000 figure 28-31. adc_1 threshold register thrhlr[0..2]
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 753 28.4.6 presampling registers 28.4.6.1 presampling control register (pscr) 28.4.6.2 presampling re gister (psr[0..2]) table 28-29 shows the available channels. table 28-27. adc_1 thrhlr field descriptions field description thrh high threshold value for channel n . thrl low threshold value for channel n . address: base + 0x0080 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 0 preval2 preval1 preval0 pre conv w reset00000000 00000000 figure 28-32. presampling control register (pscr) table 28-28. pscr field descriptions field description preval2 internal voltage selection for presampling selects analog input voltage for presampling from the available two internal voltages (external multiplexed channels). see table 28-7 . preval1 internal voltage selection for presampling selects analog input voltage for presampling from the available two internal voltages (standard channels). see ta b l e 2 8 - 7 . preval0 internal voltage selection for presampling selects analog input voltage for presampling from the available two internal voltages (precision channels). see ta b l e 2 8 - 7 . preconv convert presampled value if bit preconv is set, presampling is followed by the conversion. sampling will be bypassed and conversion of presampled data will be done.
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 754 freescale semiconductor table 28-29. psr[0..2] register description adc register description adc_0 psr0 enable bits of presampling for channel 0 to 15 (precision channels) adc_0 psr1 enable bits of presampling for channel 32 to 59 (standard channels) adc_0 psr2 enable bits of presampling for channel 64 to 95 (external multiplexed channels) adc_1 psr0 enable bits of presampling for channel 0 to 15 (precision channels) adc_1 psr1 enable bit for channel 32 to 39 (standard channels) address: base + 0x0084 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pres 15 pres 14 pres 13 pres 12 pres 11 pres 10 pres 9 pres 8 pres 7 pres 6 pres 5 pres 4 pres 3 pres 2 pres 1 pres 0 w reset00000000 00000000 figure 28-33. presampling register 0 (psr0) address: base + 0x0088 access: user read/write 0123456789101112131415 r0000 pres 59 pres 58 pres 57 pres 56 pres 55 pres 54 pres 53 pres 52 pres 51 pres 50 pres 49 pres 48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pres 47 pres 46 pres 43 pres 44 pres 43 pres 42 pres 41 pres 40 pres 39 pres 38 pres 37 pres 36 pres 35 pres 34 pres 33 pres 32 w reset00000000 00000000 figure 28-34. presam pling register 1 (psr1) for adc_0
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 755 address: base + 0x0088 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 pres 39 pres 38 pres 37 pres 36 pres 35 pres 34 pres 33 pres 32 w reset00000000 00000000 figure 28-35. presam pling register 1 (psr1) for adc_1 address: base + 0x008c access: user read/write 0123456789101112131415 r pres 95 pres 94 pres 93 pres 92 pres 91 pres 90 pres 89 pres 88 pres 87 pres 86 pres 85 pres 84 pres 83 pres 82 pres 81 pres 80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pres 79 pres 78 pres 77 pres 76 pres 75 pres 74 pres 73 pres 72 pres 71 pres 70 pres 69 pres 68 pres 67 pres 66 pres 65 pres 64 w reset00000000 00000000 figure 28-36. presampling register 2 (psr2) table 28-30. psr field descriptions field description pres n presampling enable when set (pres n = 1), presampling is enabled for channel n .
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 756 freescale semiconductor 28.4.7 conversion timing registers ctr[0..2] table 28-31 shows the available channels. table 28-31. ctr[0..2] register description adc register description adc_0 ctr0 associated to internal precision channels (from 0 to 15) adc_0 ctr1 associated to internal standard channels (from 32 to 59) adc_0 ctr2 associated to external multiplexed channels (from 64 to 95) adc_1 ctr0 associated to internal precision channels (from 0 to 15) adc_1 ctr1 associated to internal standard channel 32 to 39 address: base + 0x0094 (ctr0) base + 0x0098 (ctr1) base + 0x009c (ctr2) access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r inplatch 0 offshift 1 1 available only on ctr0 0 inpcmp 0 inpsamp w reset00000010 00000011 figure 28-37. conversion timing registers ctr[0..2] table 28-32. ctr field descriptions field description inplatch configuration bit for latching phase duration offshift configuration for o ffset shift characteristic 00 no shift (that is the transition between codes 000h and 001h) is reached when the a vin (analog input voltage) is equal to 1 lsb. 01 transition between code 000h and 001h is reached when the a vin is equal to1/2 lsb 10 transition between code 00h and 001h is reached when the a vin is equal to 0 11 not used note: available only on ctr0. inpcmp configuration bits for comparison phase duration inpsamp configuration bits fo r sampling phase duration
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 757 28.4.8 mask registers 28.4.8.1 introduction these registers are used to program which of the 96 input channels must be converted during normal and injected conversion. 28.4.8.2 normal conversion m ask registers (ncmr[0..2]) table 28-33 shows the available channels. table 28-33. ncmr[0..2] register description adc register description adc_0 ncmr0 enable bits of normal sampling for channel 0 to 15 (precision channels) adc_0 ncmr1 enable bits of normal sampling for channel 32 to 59 (standard channels) adc_0 ncmr2 enable bits of normal sampling for channel 64 to 95 (external multiplexed channels) adc_1 ncmr0 enable bits of normal sampling for channel 0 to 15 (precision channels) adc_1 ncmr1 enable bit of normal sampling channel 32 to 39 (standard channels) address: base + 0x00a4 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w reset00000000 00000000 figure 28-38. normal conversion mask register 0 (ncmr0)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 758 freescale semiconductor address: base + 0x00a8 access: user read/write 0123456789101112131415 r0000 ch59 ch58 ch57 ch56 ch55 ch54 ch53 ch52 ch51 ch50 ch49 ch48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch47 ch46 ch45 ch44 ch43 ch42 ch41 ch40 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset00000000 00000000 figure 28-39. normal conversion mask register 1 (ncmr1) for adc_0 address: base + 0x00a8 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset00000000 00000000 figure 28-40. normal conversion mask register 1 (ncmr1) for adc_1 address: base + 0x00ac access: user read/write 0123456789101112131415 r ch95 ch94 ch93 ch92 ch91 ch90 ch89 ch88 ch87 ch86 ch85 ch84 ch83 ch82 ch81 ch80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch79 ch78 ch77 ch76 ch75 ch74 ch73 ch72 ch71 ch70 ch69 ch68 ch67 ch66 ch65 ch64 w reset00000000 00000000 figure 28-41. normal conversion mask register 2 (ncmr2)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 759 note the implicit channel convers ion priority in the case in which all channels are selected is the following: adc n _p[0: x ], adc n _s[0: y ], adc n _x[0: z ]. the channels always start with 0, the lowest index. table 28-34. ncmr field descriptions field description ch n sampling enable when set, sampling is enabled for channel n .
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 760 freescale semiconductor 28.4.8.3 injected conversion mask registers (jcmr[0..2]) table 28-35 shows the available channels. table 28-35. jcmr[0..2] register description adc register description adc_0 jcmr0 enable bits of injected sampling for channel 0 to 15 (precision channels) adc_0 jcmr1 enable bits of injected sampling for channel 32 to 59 (standard channels) adc_0 jcmr2 enable bits of injected sampling for channel 64 to 95 (external multiplexed channels) adc_1 jcmr0 enable bits of injected sampling for channel 0 to 15 (precision channels) adc_1 jcmr1 enable bit of injected sampling for channel 32 to 39 (standard channels) address: base + 0x00b4 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch15 ch14 ch13 ch12 ch11 ch10 ch9 ch8 ch7 ch6 ch5 ch4 ch3 ch2 ch1 ch0 w reset00000000 00000000 figure 28-42. injected conversion mask register 0 (jcmr0) address: base + 0x00b8 access: user read/write 0123456789101112131415 r0000 ch59 ch58 ch57 ch56 ch55 ch54 ch53 ch52 ch51 ch50 ch49 ch48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch47 ch46 ch45 ch44 ch43 ch42 ch41 ch40 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset00000000 00000000 figure 28-43. injected conversion mask register 1 (jcmr1) for adc_0
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 761 28.4.9 delay registers 28.4.9.1 decode signals delay register (dsdr) the decode signals delay register (dsdr) is implemented only on adc_0. address: base + 0x00b8 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 ch39 ch38 ch37 ch36 ch35 ch34 ch33 ch32 w reset00000000 00000000 figure 28-44. injected conversion mask register 1 (jcmr1) for adc_1 address: base + 0x00bc access: user read/write 0123456789101112131415 r ch95 ch94 ch93 ch92 ch91 ch90 ch89 ch88 ch87 ch86 ch85 ch84 ch83 ch82 ch81 ch80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ch79 ch78 ch77 ch76 ch75 ch74 ch73 ch72 ch71 ch70 ch69 ch68 ch67 ch66 ch65 ch64 w reset00000000 00000000 figure 28-45. injected conversion mask register 2 (jcmr2) table 28-36. jcmr field descriptions field description ch n sampling enable when set, sampling is enabled for channel n .
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 762 freescale semiconductor 28.4.9.2 power-down exit delay register (pdedr) address: base + 0x00c4 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000 dsd w reset00000000 00000000 figure 28-46. decode signals delay register (dsdr) table 28-37. dsdr field descriptions field description dsd delay between the external decode signals and the start of the sampling phase it is used to take into account the se ttling time of the external multiplexer. the decode signal delay is calculated as: dsd 1/frequency of adc clock. note: when adc clock = peripheral clock/2 the dsd has to be incremented by 2 to see an additional adc clock cycle delay on the decode signal. for example: dsd = 0; 0 adc clock cycle delay dsd = 2; 1 adc clock cycle delay dsd = 4; 2 adc clock cycles delay address: base + 0x00c8 access: user read/write 0123456789101112131415 r0000000 0 0000 0 000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000 0 pded w reset00000000 00000000 figure 28-47. power-down exit delay register (pdedr)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 763 28.4.10 data registers 28.4.10.1 introduction adc conversion results are stored in data re gisters. there is one register per channel. 28.4.10.2 channel data register (cdr[0..95]) table 28-39 shows the available channels. each data register also gives information rega rding the corresponding result as described below. for adc_0 10-bit: table 28-38. pdedr field descriptions field description pded delay between the power-down bit reset and the start of conversion. the delay is to allow time for the adc power supply to settle before commencing conversions. the power down delay is calculated as: pded 1/frequency of adc clock. adc registers description adc_0 cdr0[0..15] enable bits of injected sampling for channel 0 to 15 (precision channels) adc_0 cdr0[32..59] enable bits of injected samp ling for channel 32 to 59 (standard channels) adc_0 cdr0[64..95] enable bits of injected sampling fo r channel 64 to 95 (external multiplexed channels) adc_1 cdr1[0..15] enable bits of injected sampling for channel 0 to 15 (precision channels) adc_1 cdr1[32..59] enable bits of injected samp ling for channel 32 to 39 (standard channels) table 28-39. cdr[0..95] register description
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 764 freescale semiconductor for adc_1 12-bit: address: see ta b l e 2 8 - 9 access: user read-only 0123456789101112131415 r 0000000 0 0000 va lid over w result w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000 cdata[0:9] (mcr[wlside] = 0) w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cdata[0:9] (mcr[wlside] = 1) 000000 w reset00000000 00000000 figure 28-48. channel data register (cdr[0..95]) address: see table 28-10 access: user read-only 0123456789101112131415 r 0000000 0 0000 va lid over w result [0:1] w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000 cdata[0:11] (mcr[wlside] = 0) w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cdata[0:11] (mcr[wlside] = 1) 0000 w reset00000000 00000000 figure 28-49. channel data register (cdr[0..95])
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 765 28.4.11 watchdog register 28.4.11.1 channel watchdog select register (cwselr[0..11]) in channel watchdog sel ect register (cwselr[0..11]) the field wsel_ch n [3:0] = selects the threshold register that provides the values to be used for upper and lower bounds for channel n . table 28-41 shows the available channels. table 28-40. cdr field descriptions field description valid used to notify when the data is valid (a new value has been written). it is automatically cleared when data is read. overw overwrite data this bit signals that the previous converted dat a has been overwritten by a new conversion. this functionality depends on the value of mcr[owren]: ? when owren = 0, then overw is frozen to 0 and cdat a field is protected aga inst being overwritten until being read. ? when owren = 1, then overw flags the cdata field overwrite status. 0 converted data has not been overwritten 1 previous converted data has been overwritten before having been read result this bit reflects the mode of conversion for the corresponding channel. 00 data is a result of normal conversion mode 01 data is a result of injected conversion mode 10 data is a result of ctu conversion mode 11 reserved cdata channel 0-95 converted data. depending on the va lue of the mcr[wlside] bit, the position of this field can be changed as shown in figure 28-48 and figure 28-48 . table 28-41. cwselr[0..11] register description adc register description adc_0 cwselr[0..1] channel watchdog select register for channel 0 to 15 (precision channels) adc_0 cwselr[2..3] not implemented adc_0 cwselr[4..7] channel watchdog select regist er for channel 32 to 59 (standard channels) adc_0 cwselr[8..11] channel watchdog select register for channel 64 to 95 (external multiplexed channels) adc_1 cwselr[0..1] channel watchdog select register for channel 0 to 15 (precision channels) adc_1 cwselr[2..3] not implemented adc_1 cwselr[4] channel watchdog select register for channel 32 to 39 (standard channels) adc_1 cwselr[5..11] not implemented
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 766 freescale semiconductor offset: 0x02b0 access: user read/write 0123456789101112131415 r0 wsel_ch7 0 wsel_ch6 0 wsel_ch5 0 wsel_ch4 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch3 0 wsel_ch2 0 wsel_ch1 0 wsel_ch0 w reset00000000 00000000 figure 28-50. channel watchdog select register 0 (cwselr0) ? adc_0 table 28-42. cwselr field descriptions ? adc_0 field description wsel_ch n channel watchdog select for channel n 000 thrhlr0 register is selected 001 thrhlr1 register is selected 010 thrhlr2 register is selected 011 thrhlr3 register is selected 100 thrhlr4 register is selected 101 thrhlr5 register is selected 110 reserved 111 reserved offset: 0x02b4 access: user read/write 0123456789101112131415 r0 wsel_ch15 0 wsel_ch14 0 wsel_ch13 0 wsel_ch12 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch11 0 wsel_ch10 0 wsel_ch9 0 wsel_ch8 w reset00000000 00000000 figure 28-51. channel watchdog select register 1 (cwselr1) ? adc_0
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 767 table 28-43. cwselr1 field descriptions ? adc_0 field description wsel_ch n see table 28-42 . offset: 0x02c0 access: user read/write 0123456789101112131415 r0 wsel_ch39 0 wsel_ch38 0 wsel_ch37 0 wsel_ch36 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch35 0 wsel_ch34 0 wsel_ch33 0 wsel_ch32 w reset00000000 00000000 figure 28-52. channel watchdog select register 4 (cwselr4) ? adc_0 table 28-44. cwselr4 field descriptions ? adc_0 field description wsel_ch n see table 28-42 . offset: 0x02c4 access: user read/write 0123456789101112131415 r0 wsel_ch47 0 wsel_ch46 0 wsel_ch45 0 wsel_ch44 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch43 0 wsel_ch42 0 wsel_ch41 0 wsel_ch40 w reset00000000 00000000 figure 28-53. channel watchdog select register 5 (cwselr5) ? adc_0
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 768 freescale semiconductor table 28-45. cwselr5 field descriptions ? adc_0 field description wsel_ch n see table 28-42 . offset: 0x02c8 access: user read/write 0123456789101112131415 r0 wsel_ch55 0 wsel_ch54 0 wsel_ch53 0 wsel_ch52 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch51 0 wsel_ch50 0 wsel_ch49 0 wsel_ch48 w reset00000000 00000000 figure 28-54. channel watchdog select register 6 (cwselr6) ? adc_0 table 28-46. cwselr6 field descriptions ? adc_0 field description wsel_ch n see table 28-42 . offset: 0x02cc access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch59 0 wsel_ch58 0 wsel_ch57 0 wsel_ch56 w reset00000000 00000000 figure 28-55. channel watchdog select register 7 (cwselr7) ? adc_0
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 769 table 28-47. cwselr7 field descriptions ? adc_0 field description wsel_ch n see table 28-42 . offset: 0x02d0 access: user read/write 0123456789101112131415 r0 wsel_ch71 0 wsel_ch70 0 wsel_ch69 0 wsel_ch68 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch67 0 wsel_ch66 0 wsel_ch65 0 wsel_ch64 w reset00000000 00000000 figure 28-56. channel watchdog select register 8 (cwselr8) ? adc_0 table 28-48. cwselr8 field descriptions ? adc_0 field description wsel_ch n see table 28-42 . offset: 0x02d4 access: user read/write 0123456789101112131415 r0 wsel_ch79 0 wsel_ch78 0 wsel_ch77 0 wsel_ch76 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch75 0 wsel_ch74 0 wsel_ch73 0 wsel_ch72 w reset00000000 00000000 figure 28-57. channel watchdog select register 9 (cwselr9) ? adc_0
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 770 freescale semiconductor table 28-49. cwselr9 field descriptions ? adc_0 field description wsel_ch n see table 28-42 . offset: 0x02d8 access: user read/write 0123456789101112131415 r0 wsel_ch87 0 wsel_ch86 0 wsel_ch85 0 wsel_ch84 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch83 0 wsel_ch82 0 wsel_ch81 0 wsel_ch80 w reset00000000 00000000 figure 28-58. channel watchdog select register 10 (cwselr10) ? adc_0 table 28-50. cwselr10 field descriptions ? adc_0 field description wsel_ch n see table 28-42 . offset: 0x02dc access: user read/write 0123456789101112131415 r0 wsel_ch95 0 wsel_ch94 0 wsel_ch93 0 wsel_ch92 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 wsel_ch91 0 wsel_ch90 0 wsel_ch89 0 wsel_ch88 w reset00000000 00000000 figure 28-59. channel watchdog select register 11 (cwselr11) ? adc_0
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 771 table 28-51. cwselr11 field descriptions ? adc_0 field description wsel_ch n see table 28-42 . offset: 0x02b0 access: user read/write 0123456789101112131415 r0 0 wsel_ch7 00 wsel_ch6 00 wsel_ch5 00 wsel_ch4 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 wsel_ch3 00 wsel_ch2 00 wsel_ch1 00 wsel_ch0 w reset00000000 00000000 figure 28-60. channel watchdog select register 0 (cwselr0) ? adc_1 table 28-52. cwselr0 field descriptions ? adc_1 field description wsel_ch n channel watchdog select for channel n 00 thrhlr0 register is selected 01 thrhlr1 register is selected 10 thrhlr2 register is selected 11 reserved offset: 0x02b4 access: user read/write 0123456789101112131415 r0 0 wsel_ch15 00 wsel_ch14 00 wsel_ch13 00 wsel_ch12 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 wsel_ch11 00 wsel_ch10 00 wsel_ch9 00 wsel_ch8 w reset00000000 00000000 figure 28-61. channel watchdog select register 1 (cwselr1) ? adc_1
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 772 freescale semiconductor table 28-53. cwselr1 field descriptions ? adc_1 field description wsel_ch n see table 28-52 . offset: 0x02c0 access: user read/write 0123456789101112131415 r0 0 wsel_ch39 00 wsel_ch38 00 wsel_ch37 00 wsel_ch36 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 wsel_ch35 00 wsel_ch34 00 wsel_ch33 00 wsel_ch32 w reset00000000 00000000 figure 28-62. channel watchdog select register 4 (cwselr4) ? adc_1 table 28-54. cwselr4 field descriptions ? adc_1 field description wsel_ch n see table 28-52 . offset: 0x02c4 access: user read/write 0123456789101112131415 r0 0 wsel_ch47 00 wsel_ch46 00 wsel_ch45 00 wsel_ch44 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0 0 wsel_ch43 00 wsel_ch42 00 wsel_ch41 00 wsel_ch40 w reset00000000 00000000 figure 28-63. channel watchdog select register 5 (cwselr5) ? adc_1
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 773 28.4.11.2 channel watchdog enable register (cwenr x , x = [0..2]) table 28-56 shows the available channels. table 28-55. cwselr5 field descriptions ? adc_1 field description wsel_ch n see table 28-52 . adc register description adc_0 cwenr0 watchdog enable bits for channel 0 to 15 (precision channels) adc_0 cwenr1 watchdog enable bits for channel 32 to 59 (standard channels) adc_0 cwenr2 watchdog enable bits for channel 64 to 95 (external multiplexed channels) adc_1 cwenr0 watchdog enable bits for channel 0 to 15 (precision channels) adc_1 cwenr1 watchdog enable bits for channel 32 to 39 (standard channels) table 28-56. cwenr[0..2] register description address: base + 0x02e0 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cwen 15 cwen 14 cwen 13 cwen 12 cwen 11 cwen 10 cwen 9 cwen 8 cwen 7 cwen 6 cwen 5 cwen 4 cwen 3 cwen 2 cwen 1 cwen 0 w reset00000000 00000000 figure 28-64. channel watchdog enable register 0 (cwenr0)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 774 freescale semiconductor address: base + 0x02e4 access: user read/write 0123456789101112131415 r0000 cwen 59 cwen 58 cwen 57 cwen 56 cwen 55 cwen 54 cwen 53 cwen 52 cwen 51 cwen 50 cwen 49 cwen 48 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cwen 47 cwen 46 cwen 43 cwen 44 cwen 43 cwen 42 cwen 41 cwen 40 cwen 39 cwen 38 cwen 37 cwen 36 cwen 35 cwen 34 cwen 33 cwen 32 w reset00000000 00000000 figure 28-65. channel watchdog enable register 1 (cwenr1) address: base + 0x02e4 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r00000000 cwen 39 cwen 38 cwen 37 cwen 36 cwen 35 cwen 34 cwen 33 cwen 32 w reset00000000 00000000 figure 28-66. channel watchdog enable register 1 (cwenr1) ? adc_1 address: base + 0x02e08 access: user read/write 0123456789101112131415 r cwen 95 cwen 94 cwen 93 cwen 92 cwen 91 cwen 90 cwen 89 cwen 88 cwen 87 cwen 86 cwen 85 cwen 84 cwen 83 cwen 82 cwen 81 cwen 80 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cwen 79 cwen 78 cwen 77 cwen 76 cwen 75 cwen 74 cwen 73 cwen 72 cwen 71 cwen 70 cwen 69 cwen 68 cwen 67 cwen 66 cwen 65 cwen 64 w reset00000000 00000000 figure 28-67. channel watchdog enable register 2 (cwenr2)
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 775 28.4.11.3 analog watchdog out of range register (aworr x , x = [0..2]) table 28-57. cwenrx field descriptions field description cwen n channel watchdog enable when set (cwen n = 1), watchdog feature is enabled for channel n . address: base + 0x02f0 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r awor_ch15 awor_ch14 awor_ch13 awor_ch12 awor_ch11 awor_ch10 awor_ch9 awor_ch8 awor_ch7 awor_ch6 awor_ch5 awor_ch4 awor_ch3 awor_ch2 awor_ch1 awor_ch0 w reset00000000 00000000 figure 28-68. analog watchdog out of range register 0 (aworr0) address: base + 0x02f4 access: user read/write 0123456789101112131415 r 0000 awor_ch59 awor_ch58 awor_ch57 awor_ch56 awor_ch55 awor_ch54 awor_ch53 awor_ch52 awor_ch51 awor_ch50 awor_ch49 awor_ch48 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r awor_ch47 awor_ch46 awor_ch43 awor_ch44 awor_ch43 awor_ch42 awor_ch41 awor_ch40 awor_ch39 awor_ch38 awor_ch37 awor_ch36 awor_ch35 awor_ch34 awor_ch33 awor_ch32 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-69. analog watchdog out of range register 1 (aworr1) ? adc_0
chapter 28 analog-to-digital converter (adc) MPC5606BK microcontroller reference manual, rev. 2 776 freescale semiconductor address: base + 0x02f4 access: user read/write 0123456789101112131415 r00000000 00000000 w reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 00000000 awor_ch39 awor_ch38 awor_ch37 awor_ch36 awor_ch35 awor_ch34 awor_ch33 awor_ch32 w w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-70. analog watchdog out of range register 1 (aworr1) ? adc_1 address: base + 0x02f8 access: user read/write 0123456789101112131415 r awor_ch95 awor_ch94 awor_ch93 awor_ch92 awor_ch91 awor_ch90 awor_ch89 awor_ch88 awor_ch87 awor_ch86 awor_ch85 awor_ch84 awor_ch83 awor_ch82 awor_ch81 awor_ch80 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r awor_ch79 awor_ch78 awor_ch77 awor_ch76 awor_ch75 awor_ch74 awor_ch73 awor_ch72 awor_ch71 awor_ch70 awor_ch69 awor_ch68 awor_ch67 awor_ch66 awor_ch65 awor_ch64 w w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c reset00000000 00000000 figure 28-71. analog watchdog out of range register 2 (aworr2) table 28-58. aworr x field descriptions field description aworr_ch n when set, indicates channel n converted data is out of range
chapter 29 cross triggering unit (ctu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 779 chapter 29 cross triggering unit (ctu) 29.1 introduction the cross triggering unit (ctu) allows synchroni zing an adc conversion with a timer event from emios (every mode that can genera te a dma request can trigger ctu) or pit. to select which adc channel is converted on a particular timer event, the ctu provides the adc with a 7-bit channel number. this channel number can be configured for each timer channel event by the application. 29.2 main features ? single cycle delayed trigger output. the trigger output is a combinat ion of 64 (generic value) input flags/events connected to different timers in the system. ? one event configuration register dedicated to each timer event to define the corresponding adc channel ? acknowledgment signal to emio s/pit for clearing the flag ? synchronization with adc to avoid collision 29.3 block diagram the ctu block diagram is shown in figure 29-1 . figure 29-1. cross triggering unit block diagram 29.4 memory map and register descriptions the ctu registers are listed in table 29-1 . every register can have 32-bit access. the base address of the ctu is 0xffe6_4000. event gen event gen event gen flag_ack next_cmd channel value select tr i g 0 tr i g 1 tr i g 6 3 channel value event arbitration & masking event configuration register 0 event configuration register 1 event configuration register 63 . . . . . . . . . .
chapter 29 cross triggering unit (ctu) MPC5606BK microcontroller reference manual, rev. 2 780 freescale semiconductor 29.4.1 event configuration regist ers (ctu_evtcfgr x) (x = 0...63) these registers contain the adc channel number to be converted when the timer event occurs. the clr_flag is used to clear the respect ive timer event flag by software (t his applies only to the pit as the emios flags are automatically cleared by the ctu). table 29-1. ctu memory map base address: 0xffe6_4000 address offset register location 0x000?0x02f reserved 0x030?0x12c event configuration r egisters 0..63 (ctu_evtcfgr0..63) on page 780 offsets: 0x030?0x12c access: read/write 0123456789101112131415 r0000000000000000 w reset0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tm clr_flag 1 1 this bit implementation is generic based and impl emented only for inputs ma pped to pit event flags. 00000 adc_sel 0 channel_value w reset0000000000000000 figure 29-2. event configuration registers (ctu_evtcfgrx) (x = 0...63) table 29-2. ctu_evtcfgrx field descriptions field description tm trigger mask 0: trigger masked 1: trigger enabled clr_flag to provide flag_ack through software 1: flag_ack is forced to 1 for the particular event 0: flag_ack is dependent on flag servicing adc_sel this bit selects the adc number. 0: 10-bit adc0 is selected 1: 12-bit adc1 is selected channel_ value these bits provide the adc channel number to be converted. valid values are 0b0 to 0b1011111 (decimal 95).
chapter 29 cross triggering unit (ctu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 781 the clr_flag bit has to be used cautiously as sett ing this bit may result in a loss of events. the event input can be masked by writing 0 to bit tm of the ctu_evtcfgr re gister. writing 1 to bit tm enables the ctu triggering and automaticall y disables the dma connection for the corresponding emios channel. note the ctu tracks issued conversion reque sts to the adc. when the adc is being triggered by the ctu and there is a need to shut down the adc, the adc must be allowed to complete conversions before being shut down. this ensures that the ctu is notified of completion; if the adc is shut down while performing a ctu-triggered conve rsion, the ctu is not notified and will not be able to tri gger further conversions until the device is reset. 29.5 functional description this peripheral is used to synchr onize adc conversions with timer events (from emios or pit). when a timer event occurs, the ctu triggers an adc c onversion providing the adc channel number to be converted. in case concurrent events occur the priori ty is managed according to the index of the timer event. the trigger output is a single cycle pulse us ed to trigger adc conversion of the channel number provided by the ctu. each trigger input from the ctu is connected to the event trigger signal of an emios channel. the assignment between emios outputs and ctu trigger inputs is defined in table 29-3 . table 29-3. trigger source ctu trigger no. module source 0 emios 0 channel_0 1 emios 0 channel_1 2 emios 0 channel_2 3 emios 0 channel_3 4 emios 0 channel_4 5 emios 0 channel_5 6 emios 0 channel_6 7 emios 0 channel_7 8 emios 0 channel_8 9 emios 0 channel_9 10 emios 0 channel_10 11 emios 0 channel_11 12 emios 0 channel_12 13 emios 0 channel_13 14 emios 0 channel_14
chapter 29 cross triggering unit (ctu) MPC5606BK microcontroller reference manual, rev. 2 782 freescale semiconductor 15 emios 0 channel_15 16 emios 0 channel_16 17 emios 0 channel_17 18 emios 0 channel_18 19 emios 0 channel_19 20 emios 0 channel_20 21 emios 0 channel_21 22 emios 0 channel_22 23 pit pit_3 24 emios 0 channel_24 25 emios 0 channel_25 26 emios 0 channel_26 27 emios 0 channel_27 28 emios 0 channel_28 29 emios 0 channel_29 30 emios 0 channel_30 31 emios 0 channel_31 32 emios 1 channel_0 33 emios 1 channel_1 34 emios 1 channel_2 35 emios 1 channel_3 36 emios 1 channel_4 37 emios 1 channel_5 38 emios 1 channel_6 39 emios 1 channel_7 40 emios 1 channel_8 41 emios 1 channel_9 42 emios 1 channel_10 43 emios 1 channel_11 44 emios 1 channel_12 45 emios 1 channel_13 46 emios 1 channel_14 47 emios 1 channel_15 table 29-3. trigger source (continued) ctu trigger no. module source
chapter 29 cross triggering unit (ctu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 783 each event has a dedicated confi guration register (ctu_evtcfgr). these registers store a channel number that is used to communicate which channel needs to be converted. in case several events are pending for adc request, the priority is managed according to the timer event index. the lowest index has the highest priority. once an event has been serviced (conversion requested to adc) the emios flag is cleared by th e ctu and next prio r event is handled. the acknowledgment signal can be forced to 1 by setting the clr_flag bit of the ctu_evtcfgr register. these bits are implemente d for only those input flags to whic h pit flags are c onnected. providing these bits offers the option of clearing pit flags by software. 29.5.1 channel value the channel value stored in an event configuration register is demultiple xed to 7 bits and then provided to the adc. the mapping of the channel number value to the corresponding adc channel is provided in table 29-3 . 48 emios 1 channel_16 49 emios 1 channel_17 50 emios 1 channel_18 51 emios 1 channel_19 52 emios 1 channel_20 53 emios 1 channel_21 54 emios 1 channel_22 55 pit pit_7 56 emios 1 channel_24 57 emios 1 channel_25 58 emios 1 channel_26 59 emios 1 channel_27 60 emios 1 channel_28 61 emios 1 channel_29 62 emios 1 channel_30 63 emios 1 channel_31 table 29-3. trigger source (continued) ctu trigger no. module source
chapter 29 cross triggering unit (ctu) MPC5606BK microcontroller reference manual, rev. 2 784 freescale semiconductor table 29-4. ctu-to-adc channel assignment 10-bit adc 12-bit adc 10-bit adc_0 signal name 10-bit adc_0 channel # channel # in ctu_evtcfgrx 12-bit adc_1 signal name 12-bit adc_1 channel # channel # in ctu_evtcfgrx adc0_p[0] ch0 0 adc1_p[0] ch0 0 adc0_p[1] ch1 1 adc1_p[1] ch1 1 adc0_p[2] ch2 2 adc1_p[2] ch2 2 adc0_p[3] ch3 3 adc1_p[3] ch3 3 adc0_p[4] ch4 4 adc1_p[4] ch4 4 adc0_p[5] ch5 5 adc1_p[5] ch5 5 adc0_p[6] ch6 6 adc1_p[6] ch6 6 adc0_p[7] ch7 7 adc1_p[7] ch7 7 adc0_p[8] ch8 8 adc1_p[8] ch8 8 adc0_p[9] ch9 9 adc1_p[9] ch9 9 adc0_p[10] ch10 10 adc1_p[10] ch10 10 adc0_p[11] ch11 11 adc1_p[11] ch11 11 adc0_p[12] ch12 12 adc1_p[12] ch12 12 adc0_p[13] ch13 13 adc1_p[13] ch13 13 adc0_p[14] ch14 14 adc1_p[14] ch14 14 adc0_p[15] ch15 15 adc1_p[15] ch15 15 adc0_s[0] ch32 32 adc1_s[0] ch32 32 adc0_s[1] ch33 33 adc1_s[1] ch33 33 adc0_s[2] ch34 34 adc1_s[2] ch34 34 adc0_s[3] ch35 35 adc1_s[3] ch35 35 adc0_s[4] ch36 36 adc1_s[4] ch36 36 adc0_s[5] ch37 37 adc1_s[5] ch37 37 adc0_s[6] ch38 38 adc1_s[6] ch38 38 adc0_s[7] ch39 39 adc1_s[7] ch39 39 adc0_s[8] ch40 40 adc0_s[9] ch41 41 adc0_s[10] ch42 42 adc0_s[11] ch43 43 adc0_s[12] ch44 44 adc0_s[13] ch45 45
chapter 29 cross triggering unit (ctu) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 785 ctu channel mapping should be taken into consid eration when programming an event configuration register. for example, if the channel value of any event configuration regi ster is programmed to 16, it will actually correspond to adc channel 32 and conversion will occur for this channel. adc0_s[14] ch46 46 adc0_s[15] ch47 47 adc0_s[16] ch48 48 adc0_s[17] ch49 49 adc0_s[18] ch50 50 adc0_s[19] ch51 51 adc0_s[20] ch52 52 adc0_s[21] ch53 53 adc0_s[22] ch54 54 adc0_s[23] ch55 55 adc0_s[24] ch56 56 adc0_s[25] ch57 57 adc0_s[26] ch58 58 adc0_s[27] ch59 59 adc0_x[0] ch64 : ch71 64:71 adc0_x[1] ch72 : ch79 72:79 adc0_x[2] ch80 : ch87 80:87 adc0_x[3] ch88 : ch95 88:95 table 29-4. ctu-to-adc channel assignment (continued) 10-bit adc 12-bit adc 10-bit adc_0 signal name 10-bit adc_0 channel # channel # in ctu_evtcfgrx 12-bit adc_1 signal name 12-bit adc_1 channel # channel # in ctu_evtcfgrx
chapter 29 cross triggering unit (ctu) MPC5606BK microcontroller reference manual, rev. 2 786 freescale semiconductor this page is intent ionally left blank.
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 787 ??? memory ???
MPC5606BK microcontroller reference manual, rev. 2 788 freescale semiconductor this page is intent ionally left blank.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 789 chapter 30 flash memory 30.1 introduction the flash memory comprises a platform flash memory controller (pflash) interface and the following flash memory arrays: ? two arrays of 512 kb for code (cflash) ? one array of 64 kb for data (dflash) the flash memory architecture of this device is illustrated in figure 30-1 . figure 30-1. flash memory architecture the primary function of the flash memory module is to serve as electrically programmable and erasable nonvolatile memory. nonvolatile memory may be used for instruction and/or data storage. the module is a nonvolatile solid-state silicon memory device consisting of: crossbar switch bank1 (dflash) 32 data (for eeprom array 0 512 kb array 1 1x128 page buffer 4x128 page buffer pflash controller emulation) cflash_pfcr0[b0_p0_bfe] cflash_mcr ... ... ... cflash_umisr4 cflash_pfcr1[b1_p0_bfe] dflash_mcr ... ... ... dflash_umisr4 flash memory flash memory 128 64 kb 512 kb array 2 flash memory bank0 (cflash) 512 kb array 0 flash memory 128 512 kb array 1 flash memory 128
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 790 freescale semiconductor ? blocks (also called sectors) of single transistor storage elements ? an electrical means for selectively adding (pro gramming) and removing (erasing) charge from these elements ? a means of selectively se nsing (reading) the charge stored in these elements the flash memory module is ar ranged as two functional units: ? the flash memory core ? the memory interface the flash memory core is composed of arrayed nonvolatile storage elements , sense amplifiers, row decoders, column decoders, and char ge pumps. the arrayed storage elemen ts in the flash memory core are subdivided into physically se parate units referred to as blocks (or sectors). the memory interface contai ns the registers and logic that control the operation of the flash memory core. the memory interface is also the interface between the flas h memory module and a pl atform flash memory controller. it contains the ecc logic and redundancy logic. a platform flash memory controller connects the flash memory module to a system bus, and contains all system level customiz ation required for th e device application. 30.2 main features 30.3 block diagram the flash memory module contains one matrix modul e, composed of a single bank (bank 0) normally used for code storage. rww operations are not possible. table 30-1. flash memory features feature cflash dflash high read parallelism (128 bits) yes error correction code (sec-ded) to enhance data retention yes double word program (64 bits) yes sector erase ye s single bank?read-while-write (rww) no erase suspend ye s program suspend no software programmable program/erase protection to avoid unwanted writings ye s censored mode against piracy yes shadow sector available yes no one-time programmable (otp) area in test flash block yes boot sectors yes no
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 791 modify operations are managed by an embedded fl ash memory program/erase controller (fpec). commands to the fpec are given through a user registers interface. the read data bus is 128 bits wide , while the flash memory registers are on a separate bus 32 bits wide addressed in the user memory map. the high voltages needed for program/erase operations are generated internally. figure 30-2. cflash and dflash module structures 30.4 functional description 30.4.1 module structure the flash memory module is addre ssable by double word (64 bits) for program, and page (128 bits) for read. reads to the flash memory al ways return 128 bits, although read page buffering may be done in the platform flash memory controller. each read of the flash memory module retrieves a page, or four consecutive words (128 bits) of information. the address for each word retrieved within a page differ s from the other addresses in the page only by address bits (3:2). the flash memory module supports fault tolerance through error correction code (ecc) or error detection, or both. the ecc implemented within the fl ash memory module will co rrect single bit failures and detect double bit failures. cflash structure 64 kb: + 16 kb testflash hv generator flash memory controller flash memory matrix register program/erase registers interface flash memory interface bank 1 dflash structure 4 16 kb hv generator flash memory controller flash memory matrix register program/erase registers interface interface 512 kb: + 16 kb testflash module 0 + 16 kb shadow 32 kb 216 kb 232 kb 3 128 kb 512 kb: module 1 4 x 128 kb
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 792 freescale semiconductor the flash memory module uses an embedded hardware algorithm implemented in the memory interface to program and erase the flash memory core. the embedded hardware algorithm includes control l ogic that works with software block enables and software lock mechanisms to guard against accidental program/erase. the hardware algorithm performs th e steps necessary to ensure that the storage elemen ts are programmed and erased with sufficient margin to guarantee data integr ity and reliability. in the flash memory module, logi c levels are defined as follows: ? a programmed bit reads as logic level 0 (or low). ? an erased bit reads as logic level 1 (or high). program and erase of the flash memory module requi res multiple system clock cycles to complete. the erase sequence may be suspended. the program and erase sequences may be aborted. 30.4.2 flash memory module sectorization 30.4.2.1 cflash module sectorization the cflash module supports 1 mb of user memory, pl us 16 kb of test memory (a portion of which is one-time programmable by the user). an extra 16 kb sector is availa ble as shadow spac e usable for user option bits and censorship settings. the module is composed of a single bank (b ank 0): read-while-write is not supported. bank 0 of the module is divided in 14 sectors including a reserved sector , named testflash, in which some one-time programmable (otp) user data are stored, as well as a shadow sector in which user erasable configuration values can be stored. the matrix module sectorization is shown in table 30-2 . table 30-2. cflash module sectorization cflash sector address range sector size address space address space locking register bank sector module cflash_lml cflash_hbl 0 0 0 0x00000000?0x00007fff 32 kb low llk0 0 1 0 0x00008000?0x0000bfff 16 kb low llk1 0 2 0 0x0000c000?0x0000ffff 16 kb low llk2 0 3 0 0x00010000?0x00017fff 32 kb low llk3 0 4 0 0x00018000?0x0001ffff 32 kb low llk4 0 5 0 0x00020000?0x0003ffff 128 kb low llk5 0 6 0 0x00040000?0x0005ffff 128 kb mid mlk0 0 7 0 0x00060000?0x0007ffff 128 kb mid mlk1
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 793 the division into blocks of the flash memory module is also used to implement independent erase/program protection. a software mechanism is provided to independently lock/unlock each block in low and mid address space against program and erase. 30.4.2.2 dflash module sectorization the dflash module supports 64 kb of user memory, plus 16 kb of test memory (a portion of which is one-time programmable by the user). the module is composed of a single bank (b ank 0): read-while-write is not supported. bank 0 of the 80 kb module is divided in four sector s. bank 0 also contains a reserved sector named testflash in which some one-time programmable user data are stored. the sectorization of the 80 kb matrix module is shown in table 30-3 . the flash memory module is divided into blocks also to implement i ndependent erase/program protection. a software mechanism is provided to independently lock/unlock each bl ock in low and mid address space against program and erase. 30.4.3 testflash block a testflash block is availa ble in both the cflash and dflash modul es. the testflash block exists outside the normal address space and is programmed and read independently of the other blocks. the independent 0 8 1 0x00080000?0x0009ffff 128 kb high hlk0 0 9 1 0x000a0000?0x000bffff 128 kb high hlk1 0 10 1 0x000c0000?0x000dffff 128 kb high hlk2 0 11 1 0x000e0000?0x000fffff 128 kb high hlk3 0 shadow 0 0x00200000?0x00203fff 16 kb shadow tslk 0 test 0 0x00400000?0x00403fff 16 kb test tslk table 30-3. dflash module sectorization bank sector addresses size (kb) address space dflash_lml field for locking the address space 0 0 0x00800000?0x00803fff 16 low llk0 1 0x00804000?0x00807fff llk1 2 0x00808000?0x0080bfff llk2 3 0x0080c000?0x0080ffff llk3 test 0x00c00000?0x00c03fff test tslk table 30-2. cflash module sectorization (continued) cflash sector address range sector size address space address space locking register bank sector module cflash_lml cflash_hbl
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 794 freescale semiconductor testflash block is included to also support systems that requi re nonvolatile memory for security or to store system initialization information, or both. a section of the testflash is reserved to stor e the nonvolatile information related to redundancy, configuration, and protection. the ecc is also applied to testflash. the structure of the testflas h sector is detailed in table 30-4 and table 30-5 . erase of the testflash bl ock is always locked. programming of the testflash block has similar restrictions as the array in terms of how ecc is calculated. only one programming ope ration is allowed pe r 64-bit ecc segment. table 30-4. cflash testflash structure name description addresses size ? user otp area 0x400000?0x401fff 8192 bytes ? reserved 0x402000?0x403cff 7424 bytes ? user otp area 0x403d00?0x403de7 232 bytes cflash_nvlml cflash nonvolatile low/mid address space block locking register 0x403de8?0x403def 8 bytes cflash_nvhbl cflash nonvolatile high address space block locking register 0x403df0?0x403df7 8 bytes cflash_nvsll cflash nonvolatile secondary low/mid address space block locking register 0x403df8?0x403dff 8 bytes ? user otp area 0x403e00?0x403eff 256 bytes ? reserved 0x403f00?0x403fff 256 bytes table 30-5. dflash testflash structure name description addresses size ? user otp area 0xc00000?0xc01fff 8192 bytes ? reserved 0xc02000?0xc03cff 7424 bytes ? user otp area 0xc03d00?0xc03de7 232 bytes dflash_nvlml dflash nonvolatile low/mid address space block locking register 0xc03de8?0xc03def 8 bytes ? reserved 0xc03df0?0xc03df7 8 bytes dflash_nvsll dflash nonvolatile secondary low/mid address space block locking register 0xc03df8?0xc03dff 8 bytes ? user otp area 0xc03e00?0xc03eff 256 bytes ? reserved 0xc03f00?0xc03fff 256 bytes
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 795 the first 8 kb of testflash block ma y be used for user defined functions (possibly to stor e serial numbers, other configuration words or factory process codes). locations of the te stflash other than the first 8 kb of otp area cannot be program med by the user application. 30.4.4 shadow sector the shadow sector is only present in the cflash module. user mode program and erase of the shadow sector are enabled onl y when cflash_mcr[peas] is high. the shadow sector may be locked /unlocked against program or eras e by using the cflash_lml[tslk] and cflash_sll[stslk] fields. programming of the shadow s ector has similar restrictions as the ar ray in terms of how ecc is calculated. only one programming operatio n is allowed per 64-bit ecc segment between erases. erase of the shadow sector is done similarly to a sector erase. the shadow sector contains specified da ta that are needed for user features. the user area of shadow sector ma y be used for user defined functions (possibly to stor e boot code, other configuration words or factory process codes). the structure of the shadow sector is detailed in table 30-6 . 30.4.5 user mode operation in user mode, the flash memory module may be read and written (register writes and interlock writes), programmed, or erased. the default state of the flash memory module is read. the main, shadow and test address space can be read only in the read state. table 30-6. shadow sector structure name description addresses size (bytes) ? user area 0x200000?0x203dcf 15824 ? reserved 0x203dd0?0x203dd7 8 nvpwd0? 1 nonvolatile private censorship password 0?1 registers 0x203dd8?0x203ddf 8 nvscc0?1 nonvolatile system censorship control 0?1 registers 0x203de0?0x203de7 8 ? reserved 0x203de8?0x203dff 24 nvpfapr nonvolatile platform flash memory access protection register 0x203e00?0x203e07 8 ? reserved 0x203e08?0x203e17 16 nvusro nonvolatile user options register 0x203e18?0x203e1f 8 ? reserved 0x203e20?0x203fff 480
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 796 freescale semiconductor the majority of cflash and dflash memory-mapped registers can be read even when the cflash or dflash is in power-down or low-power mode. the exceptions are as follows: ?cflash ? ut0[mre, mrv, ais, dsi0:7] ?ut1 ?ut2 ?dflash ? ut0[mre, mrv, ais, dsi0:7] ?ut1 ?ut2 the flash memory module enters the read state on reset. the module is in the read stat e under two sets of conditions: ? the read state is active when the module is enabled (user mode read). ? the read state is active when the ers and esus fields in the corresponding mcr (cflash_mcr or dflash_mcr) are 1 and the pgm field is 0 (erase suspend). flash memory core reads return 128 bits (1 page = 2 double words). register reads return 32 bits (1 word). flash memory core reads are done through the platform flash memory controller. register reads to unmapped register address space will return all 0s. register writes to unmapped register address space will have no effect. attempted array reads to invalid locations will result in indeterminate data. i nvalid locations occur when blocks that do not exist in non 2 n array sizes are addressed. attempted interlock writes to inva lid locations will result in an in terlock occurring, but attempts to program these blocks will not occur since they are for ced to be locked. erase will occur to selected and unlocked blocks even if the interloc k write is to an invalid location. simultaneous read cycle on the flash matrix and read/write cycles on th e registers are possible . on the contrary, registers read/w rite accesses simultaneous to a flash matrix interlock write are forbidden. 30.4.6 reset a reset is the highest priority operation for the flas h memory module and terminates all other operations. the flash memory module uses reset to initialize register and status bits to their default reset values. if the flash memory module is executi ng a program or erase operation (p gm = 1 or ers = 1 in cflash_mcr or dflash_mcr) and a reset is i ssued, the operation will be suddenl y terminated and the module will disable the high voltage logic without damage to the high voltage circui ts. reset terminates all operations and forces the flash memory module into user mode ready to receive accesses. reset and power-off must not be used as a systematic way to terminate a program or erase operation.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 797 after reset is negated, read register access may be done , although it should be noted that registers that require updating from shadow inform ation, or other inputs, may not re ad updated values until the done field (in cflash_mcr or dflash_mcr) transitions. the done field may be polled to determine if the flash memory module has transitione d out of reset. notice that the registers cannot be written until the done field is high. 30.4.7 power-down mode all flash memory dc current sources can be turned off in power-down mode, so that all power dissipation is due only to leakage in this mode. flash memory power-down mode can be selected at me_ _mc. reads from or writes to the module are not possible in power-down mode. when enabled the flash memory module returns to its pre-disabl e state in all cases unle ss in the process of executing an erase high voltage ope ration at the time of disable. if the flash memory module is disabled during an erase operation, mcr[esus] bit is programmed to 1. the user may resume the erase operation at the time the module is enabled by programming mcr[esus] = 0. mcr[ehv] must be hi gh to resume the erase operation. if the flash memory module is disabled during a pr ogram operation, the operation will in any case be completed and the power-down mode will be entered only after the programming ends. the user should realize that, if th e flash memory module is put in power-down mode and the interrupt vectors remain mapped in th e flash memory address space, the flash memory module will greatly increase the interrupt response time by adding several wait-states. it is forbidden to enter in low power mode when the power-down mode is active. 30.4.8 low power mode the low power mode turns off most of the dc curr ent sources within the fl ash memory module. flash memory low power mode can be selected at me_ _mc. the module (flash memory core and registers) is not accessible for read or writ e once it enters low power mode. wake-up time from low power mode is faster than wake-up time from power-down mode. when exiting from low power mode the flash memory module returns to its pre-sleep state in all cases unless it is executing an erase high voltage ope ration at the time low power mode is entered. if the flash memory module ente rs low power mode during an erase operation, mcr[esus] is programmed to 1. the user may resu me the erase operation at the time the module exits low power mode by programming mcr[esus] = 0. mc r[ehv] must be high to resume the erase operation. if the flash memory module enters low power mode during a program operation, the operation will be in any case completed and the low power mode wi ll be entered only after the programming end. it is forbidden to enter power-down m ode when the low power mode is active.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 798 freescale semiconductor 30.5 register description the cflash and dflash modules have respective sets of memory mapped registers. the cflash register mapping is shown in table 30-7 . the dflash register mapping is shown in table 30-8 . table 30-7. cflash registers address offset register location 0x0000 cflash module configur ation register (cflash_mcr) on page 799 0x0004 cflash low/mid address space block locking register (cflash_lml) on page 805 0x0008 cflash high address space block locking register (cflash_hbl) on page 809 0x000c cflash secondary low/mid address space block locking register (cflash_sll) on page 812 0x0010 cflash low/mid address space block select register (cflash_lms) on page 818 0x0014 cflash high address sp ace block select register (cflash_hbs) on page 819 0x0018 cflash address register (cflash_adr) on page 820 0x0028?0x0038 reserved 0x003c cflash user test 0 register (cflash_ut0) on page 821 0x0040 cflash user test 1 register (cflash_ut1) on page 823 0x0044 cflash user test 2 register (cflash_ut2) on page 823 0x0048 cflash user multiple input signature register 0 (cflash_umisr0) on page 824 0x004c cflash user multiple input signature register 1 (cflash_umisr1) on page 825 0x0050 cflash user multiple input signature register 2 (cflash_umisr2) on page 826 0x0054 cflash user multiple input signature register 3 (cflash_umisr3) on page 827 0x0058 cflash user multiple input signature register 4 (cflash_umisr4) on page 828 table 30-8. dflash registers address offset register name location 0x0000 dflash module configur ation register (dflash_mcr) on page 834 0x0004 dflash low/mid address space block locking register (dflash_lml) on page 839 0x0008 reserved ?
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 799 in the following some nonvolatile registers are desc ribed. please notice that such entities are not flip-flops, but locations of testflash or shadow sectors with a special meaning. during the flash memory initialization phase, the fpe c reads these nonv olatile registers and updates the corresponding volatile regist ers. when the fpec detects ecc double errors in these special locations, it behaves in the following way: ? in case of a failing system locations (confi gurations, device options , redundancy, embedded firmware), the initialization phase is in terrupted and a fatal error is flagged. ? in case of failing user locations (protections, censorship, platform flash memory controller, ...), the volatile registers are filled with all 1s and the flash memory initialization ends setting low the peg bit of the corresponding mcr (c flash_mcr or dflash_mcr). 30.5.1 cflash register description 30.5.1.1 cflash module config uration register (cflash_mcr) the cflash module configura tion register is used to enable and m onitor all modify operations of the flash memory module. 0x000c dflash secondary low/mid address space block locking register (dflash_sll) on page 843 0x0010 dflash low/mid address space block select register (dflash_lms) on page 847 0x0014 reserved ? 0x0018 dflash address register (dflash_adr) on page 847 0x001c?0x003b reserved ? 0x003c dflash user test 0 register (dflash_ut0) on page 848 0x0040 dflash user test 1 register (dflash_ut1) on page 851 0x0044 dflash user test 2 register (dflash_ut2) on page 851 0x0048 dflash user multiple input signature register 0 (dflash_umisr0) on page 852 0x004c dflash user multiple input signature register 1 (dflash_umisr1) on page 853 0x0050 dflash user multiple input signature register 2 (dflash_umisr2) on page 854 0x0054 dflash user multiple input signature register 3 (dflash_umisr3) on page 855 0x0058 dflash user multiple input signature register 4 (dflash_umisr4) on page 856 table 30-8. dflash registers (continued) address offset register name location
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 800 freescale semiconductor offset: 0x0000 access: read/write 0123456789101112131415 r edc0000 size 0 las 000mas w w1c reset 0000001100100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eer rwe 0 0 peas done peg 0 0 0 0 pgm psus ers esus ehv w w1c w1c reset 0000011000000000 figure 30-3. cflash module configuration register (cflash_mcr) table 30-9. cflash_mcr field descriptions field description edc ecc data correction edc provides information on previous reads. if an ecc single error detection and correction occurred, the edc bit is set to 1. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. in the event of an ecc double error detection, this bit will not be set. if edc is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of edc) were not corrected through ecc. 0 reads are occurring normally. 1 an ecc single error occurred and was corrected during a previous read. size array space size the value of size field is dependent upon th e size of the flash memory module. see table 30-10 . las low address space the value of the las field corresponds to the configuration of the low address space. see table 30-11 . mas mid address space the value of the mas field corresponds to the configuration of the mid address space. see table 30-12 . eer ecc event error eer provides information on previous reads. if an ecc double error detection occurred, the eer bit is set to 1. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. in the event of an ecc single error detection and correction, this bit will not be set. if eer is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of eer) were correct. 0 reads are occurring normally. 1 an ecc double error occurred during a previous read.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 801 rwe read-while-write event error rwe provides information on previous reads when a modify operation is on going. if a rww error occurs, the rwe bit is set to 1. read-while-write error means that a read access to the flash memory matrix has occurred while the fpec was performing a program or erase operation or an array integrity check. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. if rwe is not set, or remains 0, this indicates that all previous rww reads (from the last reset, or clearing of rwe) were correct. 0 reads are occurring normally. 1 a rww error occurred during a previous read. peas program/erase access space peas indicates which space is valid for program and erase operations: main array space or shadow/test space. peas = 0 indicates that the main address space is active for all flash memory module program and erase operations. peas = 1 indicates that th e test or shadow address space is active for program and erase. the value in peas is captured and held with the first interlock write done for modify operations. the value of peas is retained betw een sampling events (that is, subsequent first interlock writes). 0 shadow/test address space is disabled for program/erase and main address space enabled. 1 shadow/test address space is enabled for program/erase and main address space disabled. done modify operation done done indicates if the flash memory mo dule is performing a high voltage operation. done is set to 1 on termination of the flash memory module reset. done is cleared to 0 just after a 0-to-1 tr ansition of ehv, which initiates a high voltage operation, or after resuming a suspended operation. done is set to 1 at the end of program and erase high voltage sequences. done is set to 1 (within t pabt or t eabt , equal to p/e abort latency) after a 1-to-0 transition of ehv, which aborts a high voltage program/erase operation. done is set to 1 (within t esus , time equals to erase suspend latency) after a 0-to-1 transition of esus, which suspends an erase operation. 0 flash memory is executing a high voltage operation. 1 flash memory is not executing a high voltage operation. table 30-9. cflash_mcr field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 802 freescale semiconductor peg program/erase good the peg bit indicates the completion status of the last flash memory program or erase sequence for which high voltage operations we re initiated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/erase high voltage operation will cause peg to be cleared to 0, indicating the sequence failed. peg is set to 1 when the fl ash memory module is reset, unless a flash memory initialization error ha s been detected. the value of peg is valid only when pgm=1 and/or ers=1 and after done transitions from 0-to-1 due to an abort or the completion of a program/erase operation. peg is valid unti l pgm/ers makes a 1-to-0 transition or ehv makes a 0-to-1 transition. the value in peg is not valid after a 0-to-1 transition of done caused by esus being set to logic 1. if program or erase are attempted on blocks that are locked, the response will be pe g=1, indicating that the operation was successful, and the content of the block were properly protected from the program or erase operation. if a program operation tries to program at 1 bits that are at 0, the program operation is correctly executed on the new bits to be programmed at 0, but peg is cleared, indicating that the requested operation has failed. in array integrity check or margin read, peg is set to 1 when the operation is completed, regardless the occu rrence of any error. the presence of errors can be detected only comparing checksum value stored in umirs0-1. aborting an array integrity check or a margin read operation will cause peg to be cleared to 0, indicating the sequence failed. 0 program or erase operation failed or program, erase, array integrity check, or margin mode aborted. 1 program or erase operation successful or array integrity check or margin mode completed. pgm program pgm is used to set up the flash memory module for a program operation. a 0-to-1 transition of pgm initiates a program sequence. a 1-to-0 transition of pgm ends the program sequence. pgm can be set only under user mode read (ers is low and ut0[aie] is low). pgm can be cleared by the user onl y when ehv is low and done is high. pgm is cleared on reset. 0 flash memory is not executing a program sequence. 1 flash memory is executing a program sequence. psus program suspend write this bit has no effect, but the written data can be read back. ers erase ers is used to set up the flash memory module for an erase operation. a 0-to-1 transition of ers initiates an erase sequence. a 1-to-0 transition of ers ends the erase sequence. ers can be set only under user mode r ead (pgm is low and ut0[aie] is low). ers can be cleared by the user only when esus and ehv are low and done is high. ers is cleared on reset. 0 flash memory is not executing an erase sequence. 1 flash memory is executing an erase sequence. table 30-9. cflash_mcr field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 803 esus erase suspend esus is used to indicate that the flash memory module is in erase suspend or in the process of entering a suspend state. the flash memory module is in erase suspend when esus = 1 and done = 1. esus can be set high only when ers and ehv are high and pgm is low. a 0-to-1 transition of esus starts the sequen ce that sets done and places the flash memory in erase suspend. the flash memory module enters suspend within t esus of this transition. esus can be cleared only when done and ehv are high and pgm is low. a 1-to-0 transition of esus with ehv = 1 starts the sequence that clears done and returns the module to erase. the flash memory module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0 erase sequence is not suspended. 1 erase sequence is suspended. ehv enable high voltage the ehv bit enables the flash memory module for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock write to start a program/erase sequence. ehv may be set under one of the following conditions: ? erase (ers = 1, esus = 0, ut0[aie] = 0) ? program (ers = 0, esus = 0, pgm = 1, ut0[aie] = 0) in normal operation, a 1-to-0 transition of eh v with done high and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1-to -0 transition of ehv with done low and the eventual suspend bit low. an abort causes the value of peg to be cleared, indicating a failing program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. a su spended operation cannot be aborted. aborting a high voltage operation will leave the flash memory module addresses in an indeterminate data state. this may be recovere d by executing an erase on the affected blocks. ehv may be written during suspend. ehv must be high to exit suspend. ehv may not be written after esus is set and before done transitions high. ehv may not be cleared after esus is cleared and before done transitions low. 0 flash memory is not enabled to perform an high voltage operation. 1 flash memory is enabled to perform an high voltage operation. table 30-10. array space size size array space size 000 128 kb 001 256 kb 010 512 kb 011 1024 kb 100 1536 kb 101 reserved (2048 kb) table 30-9. cflash_mcr field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 804 freescale semiconductor a number of cflash_mcr bits ar e protected against write when another b it, or set of bits, is in a specific state. these write lo cks are covered on a bit by bit basis in th e preceding description, but those locks do not consider the effects of trying to wr ite two or more bits simultaneously. the flash memory module does not allo w the user to write bi ts simultaneously, whic h would put the device into an illegal state. this is implemented through a priority mechan ism among the bits. the bit changing priorities are detailed in table 30-13 . if the user attempts to write two or more cflash_m cr bits simultaneously then only the bit with the lowest priority level is written. 110 64 kb 111 reserved table 30-11. low address space configuration las low address space sectorization 000 reserved 001 reserved 010 32 kb + 2 16 kb + 2 32 kb + 128 kb 011 reserved 100 reserved 101 reserved 110 4 16 kb 111 reserved table 30-12. mid address space configuration mas mid address space sectorization 0 2 128 kb or 0 kb 1 reserved table 30-13. cflash_mcr bits set/clear priority levels priority level cflash_mcr bits 1ers 2pgm 3ehv 4 esus table 30-10. array space size (continued) size array space size
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 805 if stall/abort-while-write is enable d and an erase operation is starte d on one sector while fetching code from another, then the fo llowing sequence is executed: 1. cpu is stalled when flash is unavailable. 2. peg flag set (stall case) or reset (abort case). 3. interrupt triggered if enabled. if stall/abort-while-write is use d, then application software should ignore the setting of the rwe flag. the rwe flag should be cleared after each hv operation. if stall/abort-while-write is not used the a pplication softwa re should handle rwe error. see section 30.8.10, read-while-write functionality . 30.5.1.2 cflash low/mid address space block locking register (cflash_lml) the cflash low/mid address space block locking regi ster provides a means to protect blocks from being modified. these bits, along with bits in the cflash_sll regist er, determine if th e block is locked from program or erase. an or of cflash_lml a nd cflash_sll determines the final lock status. offset: 0x0004 access: read/write 0123456789101112131415 r lme0000000000 tslk 00 mlk w reset defined by cflash_nvlml at cflash test se ctor address 0x403de8. this location is user otp (one-time programmable). the cflash_nvlml re gister influences only the r/w bits of the cflash_lml register. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000 llk w reset defined by cflash_nvlml at cflash test se ctor address 0x403de8. this location is user otp (one-time programmable). the cflash_nvlml re gister influences only the r/w bits of the cflash_lml register. figure 30-4. cflash low/mid address space block locking register (cflash_lml)
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 806 freescale semiconductor table 30-14. cflash_lml field descriptions field description lme low/mid address space block enable this bit is used to enable the lock regist ers (tslk, mlk1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the lme bit will be set to re flect the status of enabled, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the cflash_lml register. 0 low address locks are disabled: tslk, mlk1-0 and llk15-0 cannot be written. 1 low address locks are enabled: tslk, mlk1-0 and llk15-0 can be written. tslk test/shadow address space block lock this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies t hat the test/shadow sector is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow sector is available to receive program and erase pulses. the tslk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0 test/shadow address space block is unlocked and can be modified (also if cflash_sll[stslk] = 0). 1 test/shadow address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 807 30.5.1.2.1 cflash nonvolatile low/mid address space block locking register (cflash_nvlml) the cflash_lml register has a related cflash nonvolatile low/mid addres s space block locking register located in testflash that contains the default reset valu e for cflash_lml. during the reset phase of the flash memory module, the cflash_nvlml register conten t is read and loaded into the cflash_lml. mlk mid address space block lock this field is used to lock the blocks of mid address space from program and erase. mlk is related to sectors b0f7-6, respectively. a value of 1 in a bit of the mlk field signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the mlk field signifies that the corresponding block is available to receive program and erase pulses. the mlk field is not writable after an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the mlk field is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the mlk field. the mlk field may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the mlk field (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the mlk field will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. mlk is not writable unless lme is high. 0 mid address space block is unlocked and can be modified (also if cflash_sll[smlk] = 0). 1 mid address space block is locked and cannot be modified. llk low address space block lock this field is used to lock the blocks of low address space from program and erase. llk[5:0] are related to sectors b0f5-0, respecti vely. llk[15:6] are not used for this memory cut. a value of 1 in a bit of the llk field signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk field signifies that the corresponding block is available to receive program and erase pulses. the llk field is not writable after an interl ock write is completed until cflash_mcr[done] is set at the completion of the requested operati on. likewise, the llk field is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the llk field. the llk field may be written as a register. reset will cause the field to go back to its testflash block value. the default value of the llk field (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the llk field will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. bits llk[15:6] are read-only and locked at 1. llk is not writable unless lme is high. 0 low address space block is unlocked and can be modified (also if cflash_sll[slk] = 0). 1 low address space block is locked and cannot be modified. table 30-14. cflash_lml field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 808 freescale semiconductor the cflash_nvlml register is a 64- bit register, of which the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. offset: 0x403de8 access: read/write 0123456789101112131415 r lme1111111111 tslk 11 mlk w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 1111111111 llk w reset1111111111111111 figure 30-5. cflash nonvolatile low/mid address space block locking register (cflash_nvlml) table 30-15. cflash_nvlml field descriptions field description lme low/mid address space block enable this bit is used to enable the lock regist ers (tslk, mlk1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the lme bit will be set to re flect the status of enabled, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the cflash_lml register. 0 low address locks are disabled: tslk, mlk1-0 and llk15-0 cannot be written. 1 low address locks are enabled: tslk, mlk1-0 and llk15-0 can be written. tslk test/shadow address space block lock this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies t hat the test/shadow sector is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow sector is available to receive program and erase pulses. the tslk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0 test/shadow address space block is unlocked and can be modified (also if cflash_sll[stslk] = 0). 1 test/shadow address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 809 30.5.1.3 cflash high address space bl ock locking regist er (cflash_hbl) the cflash_hbl register provides a means to protect blocks from being modified. mlk mid address space block lock these bits are used to lock the blocks of mid address space from program and erase. mlk[1:0] are related to sectors b0f7-6, respectively. a value of 1 in a bit of the mlk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the mlk register sign ifies that the corresponding block is available to receive program and erase pulses. the mlk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the mlk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the mlk registers. the mlk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the mlk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the mlk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. mlk is not writable unless lme is high. 0 mid address space block is unlocked and can be modified (also if cflash_sll[smlk] = 0). 1 mid address space block is locked and cannot be modified. llk low address space block lock these bits are used to lock the blocks of low address space from program and erase. llk[5:0] are related to sectors b0f5-0, respecti vely. llk[15:6] are not used for this memory cut. a value of 1 in a bit of the llk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk register signi fies that the corresponding block is available to receive program and erase pulses. the llk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the llk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the llk registers. the llk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the llk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the llk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. bits llk[15:6] are read-only and locked at 1. llk is not writable unless lme is high. 0 low address space block is unlocked and can be modified (also if cflash_sll[slk] = 0). 1 low address space block is locked and cannot be modified. table 30-15. cflash_nvlml field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 810 freescale semiconductor offset: 0x0008 access: read/write 0123456789101112131415 r hbe000000000000000 w reset defined by cflash_nvhbl 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 hlk w reset defined by cflash_nvhbl figure 30-6. cflash nonvolatile high address space block locking register (cflash_hbl) table 30-16. cflash_hbl field descriptions field description hbe high address space block enable this bit is used to enable the lock registers (hlk5-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the hbe bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for hbe the password 0xb2b22222 must be written to the hbl register. 0 high address locks are disabled: hlk5-0 cannot be written. 1 high address locks are enabled: hlk5-0 can be written. hlk high address space block lock these bits are used to lock the blocks of high address space from program and erase. hlk11-8 are not used for this memory cut. a value of 1 in a bit of the hlk register signi fies that the corresponding block is locked for program and erase. a value of 0 in a bit of the hlk register signif ies that the corresponding block is available to receive program and erase pulses. the hlk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the hlk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the hlk registers. the hlk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the hlk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the hlk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. in the 544 kb flash module bits hlk11-8 are read-only and locked at 1. hlk is not writable unless hbe is high. 0 high address space block is unlocked and can be modified. 1 high address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 811 30.5.1.3.1 cflash nonvolatile high addr ess space block locking register (cflash_nvhbl) the cflash_hbl register has a re lated nonvolatile high a ddress space block lock ing register located in testflash that contains the de fault reset value for cflash_hbl. du ring the reset phase of the flash module, the cflash_nvhbl register content is read and loaded into the cflash_hbl. the cflash_nvhbl register is a 64- bit register, of which the 32 most significant bits 63:32 are ?don?t care? and eventually used to manage ecc codes. offset: 0x403df0 access: read/write 0123456789101112131415 r hbe000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 hlk w reset 000000000000 xxxx figure 30-7. cflash nonvolatile high address space block locking register (cflash_nvhbl)
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 812 freescale semiconductor 30.5.1.4 cflash secondary low/mid addr ess space block lo cking register (cflash_sll) the cflash secondary low/mid addr ess space block locking register provides an altern ative means to protect blocks from being modified. these bits , along with bits in the cf lash_lml register, determine if the block is locked from program or erase. an or of cflash_lml and cflash_sll determines the final lock status. table 30-17. cflash_nvhbl field descriptions field description hbe high address space block enable this bit is used to enable the lock registers (hlk5-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the hbe bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for hbe the password 0xb2b22222 must be written to the hbl register. 0 high address locks are disabled: hlk5-0 cannot be written. 1 high address locks are enabled: hlk5-0 can be written. hlk high address space block lock these bits are used to lock the blocks of high address space from program and erase. hlk11-8 are not used for this memory cut. a value of 1 in a bit of the hlk register signi fies that the corresponding block is locked for program and erase. a value of 0 in a bit of the hlk register signif ies that the corresponding block is available to receive program and erase pulses. the hlk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the hlk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the hlk registers. the hlk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the hlk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the hlk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. in the 544 kb flash module bits hlk11-8 are read-only and locked at 1. hlk is not writable unless hbe is high. 0 high address space block is unlocked and can be modified. 1 high address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 813 offset: 0x000c access: read/write 0123456789101112131415 r sle0000000000 stslk 00 smk w reset defined by cflash_nvsll at cflash test sector address 0x403df8. this location is user otp (one-time programmable). the cflash_nvsll register influences only the r/w bits of th e cflash_sll register. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000 slk w reset defined by cflash_nvsll at cflash test sector address 0x403df8. this location is user otp (one-time programmable). the cflash_nvsll register influences only the r/w bits of the cflash_sll register. figure 30-8. cflash secondary low/mid address space block locking register (cflash_sll) table 30-18. cflash_s ll field descriptions field description sle secondary low/mid address space block enable this bit is used to enable the lock register s (stslk, smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the cflash_sll register. 0 secondary low/mid address locks are disabl ed: stslk, smk1-0 and slk15-0 cannot be written. 1 secondary low/mid address locks are enabled: stslk, smk1-0 and slk15-0 can be written. stslk secondary test/shadow address space block lock this bit is used as an alternate means to lo ck the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk register signifies that the test/shadow sector is locked for program and erase. a value of 0 in the stslk register signifies that the test/shadow sector is available to receive program and erase pulses. the stslk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0 test/shadow address space block is unlocked and can be modified (also if cflash_lml[tslk] = 0). 1 test/shadow address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 814 freescale semiconductor smk secondary mid address space block lock these bits are used as an alternate means to lock the blocks of mid address space from program and erase. smk[1:0] are related to se ctors b0f7-6, respectively. a value of 1 in a bit of the smk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the smk register signif ies that the corresponding block is available to receive program and erase pulses. the smk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the smk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the smk registers. the smk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the smk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the smk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. smk is not writable unless sle is high. 0 mid address space block is unlocked and can be modified (also if cflash_lml[mlk] =0). 1 mid address space block is locked and cannot be modified. slk secondary low address space block lock these bits are used as an al ternate means to lock the blocks of low address space from program and erase. slk[5:0] are related to sectors b0f5-0, respec tively. slk[15:6] are not used for this memory cut. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the slk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the slk registers. the slk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. bits slk[15:6] are read-only and locked at 1. slk is not writable unless sle is high. 0 low address space block is unlocked and can be modified (also if cflash_lml[llk] = 0). 1 low address space block is locked and cannot be modified. table 30-18. cflash_sll field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 815 30.5.1.4.1 cflash nonvolatile secondary low/mid address sp ace block locking register (cflash_nvsll) the cflash_sll register has a related nonvolatile secondary low/ mid address space block locking register located in testflash that contains the default reset value for sll. during the reset phase of the flash memory module, the cflash_n vsll register content is read and loaded into the cflash_sll. the cflash_nvsll register is a 64- bit register, of which the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. offset: 0x403df8 access: read/write 0123456789101112131415 r sle1111111111 stslk 11 smk w reset 1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 1111111111 slk w reset 1111111111111111 figure 30-9. cflash nonvolatile secondary low/mid address space block locking register (cflash_nvsll)
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 816 freescale semiconductor table 30-19. cflash_nvsll field descriptions field description sle secondary low/mid address space block enable this bit is used to enable the lock register s (stslk, smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the cflash_sll register. 0 secondary low/mid address locks are disabl ed: stslk, smk1-0 and slk15-0 cannot be written. 1 secondary low/mid address locks are enabled: stslk, smk1-0 and slk15-0 can be written. stslk secondary test/shadow address space block lock this bit is used as an alternate means to lo ck the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk register signifies that the test/shadow sector is locked for program and erase. a value of 0 in the stslk register signifies that the test/shadow sector is available to receive program and erase pulses. the stslk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0 test/shadow address space block is unlocked and can be modified (also if cflash_lml[tslk] = 0). 1 test/shadow address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 817 smk secondary mid address space block lock these bits are used as an alternate means to lock the blocks of mid address space from program and erase. smk[1:0] are related to se ctors b0f7-6, respectively. a value of 1 in a bit of the smk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the smk register signif ies that the corresponding block is available to receive program and erase pulses. the smk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the smk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the smk registers. the smk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the smk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the smk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. smk is not writable unless sle is high. 0 mid address space block is unlocked and can be modified (also if cflash_lml[mlk] = 0). 1 mid address space block is locked and cannot be modified. slk secondary low address space block lock these bits are used as an al ternate means to lock the blocks of low address space from program and erase. slk[5:0] are related to sectors b0f5-0, respec tively. slk[15:6] are not used for this memory cut. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until cflash_mcr[done] is set at the completion of the requested operation. likewise, the slk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the slk registers. the slk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. bits slk[15:6] are read-only and locked at 1. slk is not writable unless sle is high. 0 low address space block is unlocked and can be modified (also if cflash_lml[llk] = 0). 1 low address space block is locked and cannot be modified. table 30-19. cflash_nvsll field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 818 freescale semiconductor 30.5.1.5 cflash low/mid address space block select register (cflash_lms) the cflash_lms register provides a means to select blocks to be operated on during erase. offset: 0x00010 access: read/write 0123456789101112131415 r 00000000000000 msl w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0000000000 lsl w reset 0000000000000000 figure 30-10. cflash low/mid address space block select register (cflash_lms) table 30-20. cflash_lms field descriptions field description msl mid address space block select a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected for erase. the reset value for the select register is 0, or not selected. msl[1:0] are related to sectors b0f7-6, respectively. the blocks must be selected (or deselected) befo re doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to configuration or total memory size), the corresponding msl bits will default to not selected, and will not be writable. the reset value will always be 0, and register writes will have no effect. 0 mid address space block is not selected for erase. 1 mid address space block is selected for erase. lsl low address space block select a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected for erase. the reset value for the select register is 0, or not selected. lsl[5:0] are related to sectors b0f5-0, respecti vely. lsl[15:6] are not used for this memory cut. the blocks must be selected (or deselected) befo re doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to configuration or total memory size), the corresponding lsl bits will default to not selected, and will not be writable. the reset value will always be 0, and register writes will have no effect. bits lsl[15:6] are read-only and locked at 0. 0 low address space block is not selected for erase. 1 low address space block is selected for erase.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 819 30.5.1.6 cflash high address space bl ock select register (cflash_hbs) the cflash_hbs register provides a means to select blocks to be operated on during erase. offset: 0x00014 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 hsl w reset 0000000000000000 figure 30-11. cflash high address space block select register (cflash_hbs) table 30-21. cflash_hbs field descriptions field description hsl high address space block select a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected for erase. the reset value for the select register is 0, or not selected. hsl11-8 are not used for this memory cut. the blocks must be selected (or deselected) befo re doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to configuration or total memory size), the corresponding hsl bits will default to not sele cted, and will not be writable. the reset value will always be 0, and register writes will have no effect. in the 544 kb flash module, bits hsl11-8 are read-only and locked at 0. 0 high address space block is not selected for erase. 1 high address space block is selected for erase.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 820 freescale semiconductor 30.5.1.7 cflash address register (cflash_adr) the cflash_adr provides the first failing address in the event module failures (ecc or fpec) occur or the first address at which an ecc single error correction occurs. offset: 0x00018 access: read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r 0 0 0 0 0 0 0 0 0 ad22 ad21 ad20 ad19 ad18 ad17 ad16 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 0 0 0 w reset 1100000000000000 figure 30-12. cflash address register (cflash_adr) table 30-22. cflash_adr field descriptions field description ad address 22-3 (read only) the address register provides the first failing address in the event of ecc error (cflash_mcr[eer] = 1) or the first failing address in the event of rww error (cflash_mcr[rwe] = 1), or the address of a fa ilure that may have occurred in a fpec operation (cflash_mcr[peg] = 0). the address r egister also provides the first address at which an ecc single error co rrection occurs (cflash_mcr[edc] = 1). the ecc double error detection takes the highes t priority, followed by the fpec error and the ecc single error correction. when accessed cflash_adr will provide the address related to the first event occurred with the highe st priority. the priorities between these four possible events is summarized in table 30-23 . this address is always a double word address that selects 64 bits. in case of a simultaneous ecc double error detection on both double words of the same page, bit ad3 will output 0. the same is valid for a simultaneous ecc single error correction on both double words of the same page. table 30-23. cflash_adr content: priority list priority level error flag cflash_adr content 1 cflash_mcr[eer] = 1 address of first ecc double error 2 cflash_mcr[rwe] = 1 add ress of first rww error 3 cflash_mcr[peg] = 0 address of first fpec error 4 cflash_mcr[edc] = 1 address of first ecc single error correction
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 821 30.5.1.8 cflash user test 0 register (cflash_ut0) the user test registers provide the us er with the ability to test features on the fl ash memory module. the user test 0 register allows to control the way in which the fl ash memory content check is done. bits mre, mrv, ais, eie, and dsi[7:0] of the user test 0 register are not accessible whenever cflash_mcr[done] or ut0[aid] ar e low: reading returns indeterm inate data while writing has no effect. offset: 0x0003c access: read/write 0123456789101112131415 r ute0000000 dsi w w1c reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000 x mre mrv eie ais aie aid w reset 0000000000000001 figure 30-13. cflash user test 0 register (cflash_ut0) table 30-24. cflash_ut0 field descriptions field description ute user test enable this status bit gives indication when user test is enabled. all bits in cflash_ut0-2 and cflash_umisr0-4 are locked when this bit is 0. the method to set this bit is to provide a pas sword, and if the password matches, the ute bit is set to reflect the status of enabled, and is enabled until it is cleared by a register write. for ute the password 0xf9f99999 must be written to the cflash_ut0 register. dsi data syndrome input these bits represent the input of syndrome bits of ecc logic used in the ecc logic check. bits dsi[7:0] correspond to the 8 syndrome bits on a double word. these bits are not accessible whenever cf lash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 the syndrome bit is forced at 0. 1 the syndrome bit is forced at 1. x reserved this bit can be written and its value can be re ad back, but there is no function associated. this bit is not accessible whenever cfl ash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 822 freescale semiconductor mre margin read enable mre enables margin reads to be done. this bit, combined with mrv, enables regular user mode reads. to be replaced by margin reads inside the array integrity check sequences. margin reads are only active during array integrity checks; normal user reads are not affected by mre. this bit is not accessible whenever cflash_mcr [done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 margin reads are not enabled 1 margin reads are enabled. mrv margin read value if mre is high, mrv selects the margin level that is being checked. margin can be checked to an erased level (mrv = 1) or to a programmed level (mrv = 0). this bit is not accessible whenever cfl ash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 zeros (programmed) margin reads are requested (if mre = 1). 1 ones (erased) margin reads are requested (if mre = 1). eie ecc data input enable eie enables the ecc logic check operation to be done. this bit is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 ecc logic check is not enabled. 1 ecc logic check is enabled. ais array integrity sequence ais determines the address sequence to be used during array integr ity checks or margin read. the default sequence (ais=0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths. this sequence is proprietary. the alternative sequence (ais=1) is just logica lly sequential. it should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence. the usage of proprietary sequence is forbidden in margin read. this bit is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 array integrity sequence is proprietary sequence. 1 array integrity or margin read sequence is sequential. aie array integrity enable aie set to 1 starts the array integrity check done on all selected and unlocked blocks. the pattern is selected by ais, and the mi sr (cflash_umisr0-4) can be checked after the operation is complete, to determi ne if a correct signature is obtained. aie can be set only if cflash _mcr[ers], cflash _mcr[pgm], and cflash_mcr[ehv] are all low. 0 array integrity checks, margin read, and ecc logic checks are not enabled. 1 array integrity checks, margin read, and ecc logic checks are enabled. aid array integrity done aid will be cleared upon an array integrity check being enabled (to signify the operation is on-going). once completed, aid will be set to indicate that the array integrity check is complete. at this time the misr (cflash_umisr0-4) can be checked. 0 array integrity check is on-going. 1 array integrity check is done. table 30-24. cflash_ut0 field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 823 30.5.1.9 cflash user test 1 register (cflash_ut1) the cflash_ut1 register allows to enable the ch ecks on the ecc logic related to the 32 lsb of the double word. the user test 1 register is not accessible whenever cflash_m cr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 30.5.1.10 cflash user test 2 register (cflash_ut2) the cflash_ut2 register allows to enable the ch ecks on the ecc logic related to the 32 msb of the double word. the user test 2 register is not accessible whenever cflash_m cr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. offset: 0x00040 access: read/write 0123456789101112131415 r dai[31:16] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai[15:0] w reset 0000000000000000 figure 30-14. cflash user test 1 register (cflash_ut1) table 30-25. cflash_ut1 field descriptions field description dai[31:0] data array input, bits 31?0 these bits represent the input of even word of ecc logic used in the ecc logi c check. bits dai[31:00] correspond to the 32 array bits repres enting word 0 within the double word. 0 the array bit is forced at 0. 1 the array bit is forced at 1.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 824 freescale semiconductor 30.5.1.11 cflash user multiple input signature register 0 (cflash_umisr0) the cflash_umisr0 register provides a m ean to evaluate the array integrity. the user multiple input signature re gister 0 represents the bits 31:0 of the whole 144 bits word (2 double words including ecc). the cflash_umisr0 register is not acces sible whenever cflash_mcr[done] or cflash_ut0[aid] are low: read ing returns indeterminate data while writing has no effect. offset: 0x00044 access: read/write 0123456789101112131415 r dai[63:48] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai[47:32] w reset 0000000000000000 figure 30-15. cflash user test 2 register (cflash_ut2) table 30-26. cflash_ut2 field descriptions field description dai[63:32] data array input, bits 63?32 these bits represent the input of odd word of ecc logic used in the ecc logic check. bits dai[63:32] correspond to the 32 array bits representing word 1 within the double word. 0 the array bit is forced at 0. 1 the array bit is forced at 1.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 825 30.5.1.12 cflash user multiple input signature register 1 (cflash_umisr1) the cflash_umisr1 provides a means to evaluate the array integrity. the cflash_umisr1 represents th e bits 63:32 of the w hole 144 bits word (2 double words including ecc). the cflash_umisr1 is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. offset: 0x00048 access: read/write 0123456789101112131415 r ms0[31:16] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms0[15:0] w reset 0000000000000000 figure 30-16. cflash user multiple input signature register 0 (cflash_umisr0) table 30-27. cflash_umisr0 field descriptions field description ms0[31:0] multiple input signature, bits 31?0 these bits represent the misr value obtained accumulating the bits 31:0 of all the pages read from the flash memory. the ms can be seeded to any value by writing the cflash_umisr0 register.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 826 freescale semiconductor 30.5.1.13 cflash user multiple input signature register 2 (cflash_umisr2) the cflash_umisr2 provides a means to evaluate the array integrity. the cflash_umisr2 represents th e bits 95:64 of the w hole 144 bits word (2 double words including ecc). the cflash_umisr2 is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. offset: 0x0004c access: read/write 0123456789101112131415 r ms0[63:48] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms0[47:32] w reset 0000000000000000 figure 30-17. cflash user multiple input signature register 1 (cflash_umisr1) table 30-28. cflash_umisr1 field descriptions field description ms0[63:32] multiple input signature, bits 63?32 these bits represent the misr value obtained accumulating the bits 63:32 of all the pages read from the flash memory. the ms can be seeded to any value by writing the cflash_umisr1.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 827 30.5.1.14 cflash user multiple input signature register 3 (cflash_umisr3) the cflash_umisr3 provides a mean to evaluate the array integrity. the cflash_umisr3 represents the bits 127:96 of the whole 144 bits word (2 double words including ecc). the cflash_umisr3 is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. offset: 0x00050 access: read/write 0123456789101112131415 r ms0[95:80] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms0[79:64] w reset 0000000000000000 figure 30-18. cflash user multiple input signature register 2 (cflash_umisr2) table 30-29. cflash_umisr2 field descriptions field description ms0[95:64] multiple input signature, bits 95?64 these bits represent the misr value obtained accumulating the bits 95:64 of all the pages read from the flash memory. the ms can be seeded to any value by writing the cflash_umisr2.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 828 freescale semiconductor 30.5.1.15 cflash user multiple input signature register 4 (cflash_umisr4) the cflash_umisr4 provides a mean to evaluate the array integrity. the cflash_umisr4 represents the ecc bits of the whole 144 bits word (2 double words including ecc): bits 8:15 are ecc bits for the odd double word, and bits 24:31 are the ecc bits for the even double word; bits 4:5 and 20:21 of misr are respectively the double and single ecc er ror detection for odd and even double word. the cflash_umisr4 is not accessible whenever cflash_mcr[done] or cflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. offset: 0x00054 access: read/write 0123456789101112131415 r ms[127:112] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[111:96] w reset 0000000000000000 figure 30-19. cflash user multiple input signature register 3 (cflash_umisr3) table 30-30. cflash_umisr3 field descriptions field description ms[127:96] multiple input signature, bits127?96 these bits represent the misr value obtained accumulating the bits 127:96 of all the pages read from the flash memory. the ms can be seeded to any value by writing the cflash_umisr3.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 829 30.5.1.16 cflash nonvolatile private cens orship password 0 register (nvpwd0) the nonvolatile private censorship password 0 register contains the 32 lsb of the password used to validate the censorship informati on contained in nvscc0?1 registers. offset: 0x00058 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r ms[159:144] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[143:128] w reset 0000000000000000 figure 30-20. cflash user multiple input signature register 4 (cflash_umisr4) table 30-31. cflash_umisr4 field descriptions field description ms[159:128] multiple input signature, bits 159?128 these bits represent the misr value obtained accumulating: ? the 8 ecc bits for the even double word (on ms[135:128]); ? the single ecc error detection for even double word (on ms138); ? the double ecc error detection for even double word (on ms139); ? the 8 ecc bits for the odd double word (on ms[151:144]); ? the single ecc error detection for odd double word (on ms154); ? the double ecc error detection for odd double word (on ms155). the ms can be seeded to any value by writing the cflash_umisr4 register.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 830 freescale semiconductor 30.5.1.17 cflash nonvolatile private cens orship password 1 register (nvpwd1) the nonvolatile private censorship password 1 register contains the 32 msb of the password used to validate the censorship informati on contained in nvscc0?1 registers. offset: 0x203dd8 access: read/write 0123456789101112131415 r pwd[31:16] w reset 1111111011101101 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwd[15:0] w reset 1111101011001110 figure 30-21. cflash nonvolatile private censorship password 0 register (nvpwd0) table 30-32. nvpwd0 field descriptions field description pwd[31:0] password, bits 31?0 these bits represent the 32 lsb of the private censorship password. offset: 0x203ddc access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r pwd[63:48] w reset 1100101011111110 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r pwd[47:32] w reset 1011111011101111 figure 30-22. cflash nonvolatile private censorship password 1 register (nvpwd1)
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 831 note in a secured device, starting with a se rial boot, it is possible to read the content of the four flash locations where the rchw can be stored. for example if the rchw is stored at address 0x00000000, the reads at address 0x00000000, 0x00000004, 0x00000008, and 0x0000000c will return a correct value. any other fl ash address cannot be accessed. 30.5.1.18 cflash nonvolatil e system censorship control 0 register (nvscc0) the nvscc0 register stores the 32 lsb of th e censorship control word of the device. the nvscc0 is a nonvolatile re gister located in the shad ow sector: it is read dur ing the reset phase of the flash memory module and the protection m echanisms are activated consequently. the parts are delivered uncensored to the user. table 30-33. nvpwd1 field descriptions field description pwd[63:32] password, bits 63?32 these bits represent the 32 msb of the private censorship password. offset: 0x203de0 access: read/write 0123456789101112131415 r sc[15:0] w reset 0101010110101010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cw[15:0] w reset 0101010110101010 figure 30-23. cflash nonvolatile system censorship control 0 register (nvscc0)
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 832 freescale semiconductor 30.5.1.19 cflash nonvolatil e system censorship control 1 register (nvscc1) the nvscc1 register stores the 32 msb of th e censorship control word of the device. the nvscc1 is a nonvolatile re gister located in the shad ow sector: it is read dur ing the reset phase of the flash memory module and the protection m echanisms are activated consequently. the parts are delivered uncensored to the user. table 30-34. nvscc0 field descriptions field description sc[15:0] serial censorship control word, bits 15-0 these bits represent the 16 lsb of the serial censorship control word (sccw). if sc15-0 = 0x55aa and nvscc1 = nvscc0 the public access is disabled. if sc15-0 ? 0x55aa or nvscc1 ? nvscc0 the public access is enabled. cw[15:0] censorship control word, bits 15-0 these bits represent the 16 lsb of the censorship control word (ccw). if cw15-0 = 0x55aa and nvscc1 = nvscc0 the censored mode is disabled. if cw15-0 ? 0x55aa or nvscc1 ? nvscc0 the censored mode is enabled. offset: 0x203de4 access: read/write 0123456789101112131415 r sc[31:16] w reset 0101010110101010 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r cw[31:16] w reset 0101010110101010 figure 30-24. cflash nonvolatile system censorship control 1 register (nvscc1) table 30-35. nvscc1 field descriptions field description sc[31:16] serial censorship control word, bits 31-16 these bits represent the 16 msb of the serial censor ship control word (sccw). if sc15-0 = 0x55aa and nvscc1 = nvscc0 the public access is disabled. if sc15-0 ? 0x55aa or nvscc1 ? nvscc0 the public access is enabled. cw[31:16] censorship control word, bits 31-16 these bits represent the 16 msb of the censorship control word (ccw). if cw15-0 = 0x55aa and nvscc1 = nvscc0 the censored mode is disabled. if cw15-0 ? 0x55aa or nvscc1 ? nvscc0 the censored mode is enabled.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 833 30.5.1.20 cflash nonvolatile us er options register (nvusro) the nonvolatile user options regist er contains configuration inform ation for the user application. the nvusro register is a 64-bit register, of which th e 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. offset: 0x203e18 access: read/write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r watchdog_en oscillator_margin pa d 3 v 5 v 1111111111111 w reset 1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 1111111111111111 w reset 1111111111111111 figure 30-25. cflash nonvolatile user options register (nvusro) table 30-36. nvusro field descriptions field description watchdog_en watchdog enable 0 disable after reset 1 enable after reset default manufacturing value before flash memory initialization is 1 oscillator_ margin oscillator margin 0 low consumption configuration (4 mhz/8 mhz) 1 high margin configuration (4 mhz/16 mhz) default manufacturing value before flash memory initialization is 1 pa d 3 v 5 v pa d 3 v 5 v 0 high voltage supply is 5.0 v 1 high voltage supply is 3.3 v default manufacturing value before flash memory initialization is 1 (3.3 v), which should ensure correct minimum slope for boundary scan.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 834 freescale semiconductor 30.5.2 dflash register description 30.5.2.1 dflash module config uration register (dflash_mcr) the module configuration register is used to enable and monitor al l modify operations of the flash memory module. address offset: 0x0000 access: read/write 0123456789101112131415 r edc0000 size 0 las 000mas w w1c reset 0000011001100000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r eer rwe 0 0 peas done peg0000 pgm psus ers esus ehv w w1c w1c reset 0000011000000000 figure 30-26. dflash module conf iguration register (dflash_mcr) table 30-37. dflash_mcr field descriptions field description edc ecc data correction edc provides information on previous reads. if an ecc single error detection and correction occurred, the edc bit is set to 1. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. in the event of an ecc double error detection, this bit will not be set. if edc is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of edc) were not corrected through ecc. the function of this bit is device depend ent and it can be configured to be disabled. 0 reads are occurring normally. 1 an ecc single error occurred and was corrected during a previous read. size array space size the value of size field is dependent upon th e size of the flash memory module. see table 30-38 . las low address space the value of the las field corresponds to the configuration of the low address space. see table 30-39 . mas mid address space the value of the mas field corresponds to the configuration of the mid address space. see table 30-40 .
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 835 eer ecc event error eer provides information on previous reads. if an ecc double error detection occurred, the eer bit is set to 1. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. in the event of an ecc single error detection and correction, this bit will not be set. if eer is not set, or remains 0, this indicates that all previous reads (from the last reset, or clearing of eer) were correct. 0 reads are occurring normally. 1 an ecc double error occurred during a previous read. rwe read-while-write event error rwe provides information on previous reads when a modify operation is on going. if a rww error occurs, the rwe bit will be set to 1. read-while-write error means that a read access to the flash memory matrix has occurred while the fpec was performing a program or erase operation or an array integrity check. this bit must then be cleared, or a reset must occur before this bit will return to a 0 state. this bit may not be set to 1 by the user. if rwe is not set, or remains 0, this indicates that all previous rww reads (from the last reset, or clearing of rwe) were correct. 0 reads are occurring normally. 1 a rww error occurred during a previous read. peas program/erase access space peas indicates which space is valid for program and erase operations: main array space or shadow/test space. peas = 0 indicates that the main address space is active for all flash memory module program and erase operations. peas = 1 indicates that th e test or shadow address space is active for program and erase. the value in peas is captured and held with the first interlock write done for modify operations. the value of peas is retained betw een sampling events (that is, subsequent first interlock writes). 0 shadow/test address space is disabled for program/erase and main address space enabled. 1 shadow/test address space is enabled for program/erase and main address space disabled. done modify operation done done indicates if the flash memory mo dule is performing a high voltage operation. done is set to 1 on termination of the flash memory module reset. done is cleared to 0 just after a 0-to-1 tr ansition of ehv, which initiates a high voltage operation, or after resuming a suspended operation. done is set to 1 at the end of program and erase high voltage sequences. done is set to 1 (within t pabt or t eabt , equal to p/e abort latency) after a 1-to-0 transition of ehv, which aborts a high voltage program/erase operation. done is set to 1 (within t esus , time equals to erase suspend latency) after a 0-to-1 transition of esus, which suspends an erase operation. 0 flash memory is executing a high voltage operation. 1 flash memory is not executing a high voltage operation. table 30-37. dflash_mcr field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 836 freescale semiconductor peg program/erase good the peg bit indicates the completion status of the last flash memory program or erase sequence for which high voltage operations we re initiated. the value of peg is updated automatically during the program and erase high voltage operations. aborting a program/erase high voltage operation will cause peg to be cleared to 0, indicating the sequence failed. peg is set to 1 when the flash memory module is reset, unless a flash memory initialization error has been detected. the value of peg is valid only when pgm = 1 and/or ers = 1 and after done transitions from 0-to-1 due to an abort or the completion of a program/erase operat ion. peg is valid until pgm/ers makes a 1-to-0 transition or ehv makes a 0-to-1 transition. the value in peg is not valid after a 0-to-1 transition of done caused by esus being set to logic 1. if program or erase are attempted on blocks that are locked, the response will be peg = 1, indicating that the operation was successful, and the content of the block were properly protected from the program or erase operation. if a program operation tries to program at 1 bi ts that are at 0, the program operation is correctly executed on the new bits to be programm ed at 0, but peg is cleared, indicating that the requested operation has failed. in array integrity check or margin read, peg is set to 1 when the operation is completed, regardless the occurrence of any error. the presence of errors can be detected only comparing checksum value stored in umirs0-1. aborting an array integrity check or a margin read operation will cause peg to be cleared to 0, indicating the sequence failed. 0 program or erase operation failed; or program, erase, array integrity check, or margin mode aborted. 1 program or erase operation successful, or array integrity check or margin mode completed. pgm program pgm is used to set up the flash memory module for a program operation. a 0-to-1 transition of pgm initiates a program sequence. a 1-to-0 transition of pgm ends the program sequence. pgm can be set only under user mode read (e rs is low and dflash_ut0[aie] is low). pgm can be cleared by the user onl y when ehv is low and done is high. pgm is cleared on reset. 0 flash memory is not executing a program sequence. 1 flash memory is executing a program sequence. psus program suspend a write to this bit has no effect, but the written data can be read back. ers erase ers is used to set up the flash memory module for an erase operation. a 0-to-1 transition of ers initiates an erase sequence. a 1-to-0 transition of ers ends the erase sequence. ers can be set only under user mode read (p gm is low and dflash_ut0[aie] is low). ers can be cleared by the user only when esus and ehv are low and done is high. ers is cleared on reset. 0 flash memory is not executing an erase sequence. 1 flash memory is executing an erase sequence. table 30-37. dflash_mcr field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 837 esus erase suspend esus is used to indicate that the flash memory module is in erase suspend or in the process of entering a suspend state. the flash memory module is in erase suspend when esus = 1 and done = 1. esus can be set high only when ers and ehv are high and pgm is low. a 0-to-1 transition of esus starts the sequen ce that sets done and places the flash memory in erase suspend. the flash memory module enters suspend within t esus of this transition. esus can be cleared only when done and ehv are high and pgm is low. a 1-to-0 transition of esus with ehv = 1 starts the sequence that clears done and returns the module to erase. the flash memory module cannot exit erase suspend and clear done while ehv is low. esus is cleared on reset. 0 erase sequence is not suspended. 1 erase sequence is suspended. ehv enable high voltage the ehv bit enables the flash memory module for a high voltage program/erase operation. ehv is cleared on reset. ehv must be set after an interlock write to start a program/erase sequence. ehv may be set under one of the following conditions: ? erase (ers = 1, esus = 0, dflash_ut0[aie] = 0) ? program (ers = 0, esus = 0, pgm = 1, dflash_ut0[aie] = 0) in normal operation, a 1-to-0 transition of eh v with done high and esus low terminates the current program/erase high voltage operation. when an operation is aborted, there is a 1-to -0 transition of ehv with done low and the eventual suspend bit low. an abort causes the value of peg to be cleared, indicating a failing program/erase; address locations being operated on by the aborted operation contain indeterminate data after an abort. a su spended operation cannot be aborted. aborting a high voltage operation will leave the flash memory module addresses in an indeterminate data state. this may be recovere d by executing an erase on the affected blocks. ehv may be written during suspend. ehv must be high to exit suspend. ehv may not be written after esus is set and before done transitions high. ehv may not be cleared after esus is cleared and before done transitions low. 0 flash memory is not enabled to perform an high voltage operation. 1 flash memory is enabled to perform an high voltage operation. table 30-38. array space size size array space size 000 128 kb 001 256 kb 010 512 kb 011 reserved (1024 kb) 100 reserved (1536 kb) 101 reserved (2048 kb) table 30-37. dflash_mcr field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 838 freescale semiconductor a number of dflash_mcr bits are protected against write wh en another bit, or set of bits, is in a specific state. these write lo cks are covered on a bit by bit basis in th e preceding description, but those locks do not consider the effects of trying to wr ite two or more bits simultaneously. the flash memory module does not allo w the user to write bi ts simultaneously, whic h would put the device into an illegal state. this is implemented through a priority mechan ism among the bits. the bit changing priorities are detailed in the table 30-41 . if the user attempts to write two or more dflash_m cr bits simultaneously then only the bit with the lowest priority level is written. 110 64 kb 111 reserved table 30-39. low address space configuration las low address space sectorization 000 reserved 001 reserved 010 32 kb + 2 16 kb + 2 32 kb + 128 kb 011 reserved 100 reserved 101 reserved 110 4 16 kb 111 reserved table 30-40. mid address space configuration mas mid address space sectorization 0 2 128kb 1 reserved table 30-41. dflash_mcr bits set/clear priority levels priority level dflash_mcr bits 1ers 2pgm 3ehv 4 esus table 30-38. array space size (continued) size array space size
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 839 if stall/abort-while-write is enable d and an erase operation is starte d on one sector while fetching code from another then the foll owing sequence is executed: ? cpu is stalled when flash is unavailable ? peg flag set (stall cas e) or reset (abort case) ? interrupt triggered if enabled if stall/abort-while-write is used, then software s hould ignore the setting of th e rwe flag. the rwe flag should be cleared after each hv operation. if stall/abort-while-write is not used the a pplication softwa re should handle rwe error. see section 30.8.10, read-while-write functionality . 30.5.2.2 dflash low/mid address space block locking register (dflash_lml) the dflash low/mid address space block locking regi ster provides a means to protect blocks from being modified. these bits, along with bits in the df lash_sll register, determine if the block is locked from program or erase. an or of dflash_lml and dflash_sll determine the final lock status. offset: 0x0004 access: read/write 0123456789101112131415 r lme0000000000 tslk 0000 w reset defined by dflash_nvlml at dflash test se ctor address 0xc03de8. this location is user otp (one-time programmable). the dflash_nvlml re gister influences only the r/w bits of the dflash_lml register. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 llk w reset defined by dflash_nvlml at dflash test se ctor address 0xc03de8. this location is user otp (one-time programmable). the dflash_nvlml re gister influences only the r/w bits of the dflash_lml register. figure 30-27. dflash low/mid address sp ace block locking register (dflash_lml)
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 840 freescale semiconductor table 30-42. dflash_lml field descriptions field description lme low/mid address space block enable this bit is used to enable the lock regist ers (tslk, mlk1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the lme bit will be set to re flect the status of enabled, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the dflash_lml register. 0 low address locks are disabled: tslk, mlk1-0 and llk15-0 cannot be written. 1 low address locks are enabled: tslk, mlk1-0 and llk15-0 can be written. tslk test/shadow address space block lock this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies t hat the test/shadow sector is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow sector is available to receive program and erase pulses. the tslk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0 test/shadow address space block is unlocked and can be modified (also if dflash_sll[stslk] = 0). 1 test/shadow address space block is locked and cannot be modified. llk low address space block lock this field is used to lock the blocks of low address space from program and erase. llk[3:0] are related to sectors b1f3-0, respecti vely. llk[15:4] are not used for this memory cut. a value of 1 in a bit of the llk field signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk field signifies that the corresponding block is available to receive program and erase pulses. the llk field is not writable after an interl ock write is completed until dflash_mcr[done] is set at the completion of the requested operati on. likewise, the llk field is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the llk field. the llk field may be written as a register. reset will cause the field to go back to its testflash block value. the default value of the llk field (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the llk field will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. in the 64 kb flash memory module bits llk[15:4] are read-only and locked at 1. llk is not writable unless lme is high. 0 low address space block is unlocked and can be modified (also if dflash_sll[slk] = 0). 1 low address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 841 30.5.2.2.1 dflash nonvolatile low/mid address space block locking register (dflash_nvlml) the dflash_lml register has a related nonvolatile low/mid address space block locking register located in testflash that contains the default reset value for dflash _lml. during the reset phase of the flash memory module, the dflash_nvlml regist er content is read and loaded into the dflash_lml. the dflash_nvlml register is a 64- bit register, of which the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. offset: 0xc03de8 access: read/write 0123456789101112131415 r lme1111111111 tslk 1111 w reset1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 111111111111 llk w reset1111111111111111 figure 30-28. dflash nonvolatile low/mid address space block locking register (dflash_nvlml)
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 842 freescale semiconductor table 30-43. dflash_nvlml field descriptions field description lme low/mid address space block enable this bit is used to enable the lock registers (tslk, mlk1-0 and llk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the lme bit will be set to re flect the status of enabled, and is enabled until a reset operation occurs. for lme the password 0xa1a11111 must be written to the dflash_lml register. 0 low address locks are disabled: tslk, mlk1-0, and llk15-0 cannot be written. 1 low address locks are enabled: tslk, mlk1-0, and llk15-0 can be written. tslk test/shadow address space block lock this bit is used to lock the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the tslk register signifies t hat the test/shadow sector is locked for program and erase. a value of 0 in the tslk register signifies that the test/shadow sector is available to receive program and erase pulses. the tslk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the tslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the tslk register. the tslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the tslk bit (assuming erased fuses) would be locked. tslk is not writable unless lme is high. 0 test/shadow address space block is unlocked and can be modified (also if dflash_sll[stslk]= 0). 1 test/shadow address space block is locked and cannot be modified. llk low address space block lock these bits are used to lock the blocks of low address space from program and erase. llk[3:0] are related to sectors b1f3-0, respecti vely. llk[15:4] are not used for this memory cut. a value of 1 in a bit of the llk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the llk register signi fies that the corresponding block is available to receive program and erase pulses. the llk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the llk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the llk registers. the llk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the llk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the llk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. in the 64 kb flash memory module bits llk[15:4] are read-only and locked at 1. llk is not writable unless lme is high. 0 low address space block is unlocked and can be modified (also if dflash_sll[slk] = 0). 1 low address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 843 30.5.2.3 dflash secondary low/mid addr ess space block lo cking register (dflash_sll) the dflash secondary low/mid addr ess space block locking register provides an alternative means to protect blocks from being modified. these bits, along with bits in the dflash_lml re gister, determine if the block is locked from program or erase. an or of dflash_lml and dflash_sll determines the final lock status. offset: 0x000c access: read/write 0123456789101112131415 r sle0000000000 stslk 0000 w reset defined by dflash_nvsll at dflash test sect or address 0xc03df8. this location is user otp (one-time programmable). the dflash_nvsll register influences only the r/w bits of the dflash_sll register. 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 slk w reset defined by dflash_nvsll at dflash test sect or address 0xc03df8. this location is user otp (one-time programmable). the dflash_nvsll register influences only the r/w bits of the dflash_sll register. figure 30-29. dflash secondary low/mid address space block locking register (dflash_sll)
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 844 freescale semiconductor table 30-44. dflash_s ll field descriptions field description sle secondary low/mid address space block enable this bit is used to enable the lock register s (stslk, smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the dflash_sll register. 0 secondary low/mid address locks are disabled: stslk, smk1-0, and slk15-0 cannot be written. 1 secondary low/mid address locks are enabled: stslk, smk1-0, and slk15-0 can be written. stslk secondary test/shadow address space block lock this bit is used as an alternate means to lo ck the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk register signifies that the test/shadow sector is locked for program and erase. a value of 0 in the stslk register signifies that the test/shadow sector is available to receive program and erase pulses. the stslk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0 test/shadow address space block is unlocked and can be modified (also if dflash_lml[tslk] = 0). 1 test/shadow address space block is locked and cannot be modified. slk secondary low address space block lock these bits are used as an al ternate means to lock the blocks of low address space from program and erase. slk[3:0] are related to sectors b1f3-0, respec tively. slk[15:4] are not used for this memory cut. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the slk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the slk registers. the slk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. in the 64 kb flash memory module bits slk[15:4] are read-only and locked at 1. slk is not writable unless sle is high. 0 low address space block is unlocked and can be modified (also if dflash_lml[llk] = 0). 1 low address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 845 30.5.2.3.1 dflash nonvolatile secondary low/mid address sp ace block locking register (dflash_nvsll) the dflash_sll register has a re lated nonvolatile seconda ry low/mid address space block locking register located in testflash that contains the default reset value fo r dflash_sll. during the reset phase of the flash memory module, the dflash_nvsll re gister content is read and loaded into the dflash_sll. the dflash_nvsll register is a 64- bit register, of which the 32 mo st significant bits 63:32 are ?don?t care? and are used to manage ecc codes. offset: 0xc03df8 access: read/write 0123456789101112131415 r sle1111111111 stslk 1111 w reset 1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 111111111111 slk w reset 1111111111111111 figure 30-30. dflash nonvolatile secondary lo w/mid address space block locking register (dflash_nvsll)
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 846 freescale semiconductor table 30-45. dflash_nvsll field descriptions field description sle secondary low/mid address space block enable this bit is used to enable the lock register s (stslk, smk1-0 and slk15-0) to be set or cleared by registers writes. this bit is a status bit only. the method to se t this bit is to write a password, and if the password matches, the sle bit will be set to reflect the status of enabled, and is enabled until a reset operation occurs. for sle the password 0xc3c33333 must be written to the dflash_sll register. 0 secondary low/mid address locks are disabled: stslk, smk1-0, and slk15-0 cannot be written. 1 secondary low/mid address locks are enabled: stslk, smk1-0, and slk15-0 can be written. stslk secondary test/shadow address space block lock this bit is used as an alternate means to lo ck the block of test and shadow address space from program and erase (erase is any case forbidden for test block). a value of 1 in the stslk register signifies that the test/shadow sector is locked for program and erase. a value of 0 in the stslk register signifies that the test/shadow sector is available to receive program and erase pulses. the stslk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the stslk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash block is loaded into the stslk register. the stslk bit may be written as a register. reset will cause the bit to go back to its testflash block value. the default value of the stslk bit (assuming erased fuses) would be locked. stslk is not writable unless sle is high. 0 test/shadow address space block is unlocked and can be modified (also if dflash_lml[tslk] = 0). 1 test/shadow address space block is locked and cannot be modified. slk secondary low address space block lock these bits are used as an al ternate means to lock the blocks of low address space from program and erase. slk[3:0] are related to sectors b1f3-0, respec tively. slk[15:4] are not used for this memory cut. a value of 1 in a bit of the slk register signifies that the corresponding block is locked for program and erase. a value of 0 in a bit of the slk register signifies that the corresponding block is available to receive program and erase pulses. the slk register is not writable once an interlock write is completed until dflash_mcr[done] is set at the completion of the requested operation. likewise, the slk register is not writable if a high voltage operation is suspended. upon reset, information from the testflash bloc k is loaded into the slk registers. the slk bits may be written as a register. reset will cause the bits to go back to their testflash block value. the default value of the slk bits (assuming erased fuses) would be locked. in the event that blocks are not present (due to configuration or total memory size), the slk bits will default to locked, and will not be writable. the reset value will always be 1 (independent of the testflash block), and re gister writes will have no effect. in the 64 kb flash memory module bits slk[15:4] are read-only and locked at 1. slk is not writable unless sle is high. 0 low address space block is unlocked and can be modified (also if dflash_lml[llk] = 0). 1 low address space block is locked and cannot be modified.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 847 30.5.2.4 dflash low/mid address space block select register (dflash_lms) the dflash_lms register provides a means to select blocks to be operated on during erase. 30.5.2.5 dflash address register (dflash_adr) the dflash_adr provides the first failing address in the event modul e failures (ecc, rww or fpec) occur or the first addre ss at which an ecc single error correction occurs. offset: 0x00010 access: read/write 0123456789101112131415 r 0000000000000000 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000000 lsl w reset 0000000000000000 figure 30-31. dflash low/mid address space block select register (dflash_lms) table 30-46. dflash_lms field descriptions field description lsl low address space block select a value of 1 in the select register signifies that the block is selected for erase. a value of 0 in the select register signifies that the block is not selected for erase. the reset value for the select register is 0, or not selected. lsl[3:0] are related to sectors b1f3-0, respectively. lsl[15:4] are not used for this memory cut. the blocks must be selected (or deselected) befor e doing an erase interlock write as part of the erase sequence. the select register is not writable once an interlock write is completed or if a high voltage operation is suspended. in the event that blocks are not present (due to configuration or total memory size), the corresponding lsl bits will default to not selected, and will not be writable. the reset value will always be 0, and register writes will have no effect. in the 80 kb flash memory module bits lsl[15:4] are read-on ly and locked at 0. 0 low address space block is not selected for erase. 1 low address space block is selected for erase.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 848 freescale semiconductor 30.5.2.6 dflash user test 0 register (dflash_ut0) the user test registers provide the user with the ability to test features on the flash memory module. address offset: 0x00018 access: read 0123456789101112131415 r 000000000ad22ad21ad20ad19ad18ad17ad16 w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 0 0 0 w reset 0000000000000000 figure 30-32. dflash address register (dflash_adr) table 30-47. dflash_adr field descriptions field description ad[22:3] address 22-3 the address register provides the first failing address in the event of ecc error (dflash_mcr[eer] set) or the first failing address in the event of rww error (dflash_mcr[rwe] set), or the address of a failur e that may have occurred in a fpec operation (dflash_mcr[peg] cleared). the address register also provides the first address at which an ecc single error correction occurs (dflash_mcr[edc] se t), if the device is configured to show this feature. the ecc double error detection takes the highest priority, followed by the rww error, the fpec error and the ecc single error correction. when accessed dflash_adr will provide the address related to the first event occurred with the highest priority. the priorities between these four possible events is summarized in the table 30-48 . this address is always a double word address that selects 64 bits. in case of a simultaneous ecc double error detecti on on both double words of the same page, bit ad3 will output 0. the same is valid for a simultan eous ecc single error correction on both double words of the same page. in user mode, the address register is read only. table 30-48. dflash_adr content: priority list priority level error flag dflash_adr content 1 dflash_mcr[eer] = 1 address of first ecc double error 2 dflash_mcr[rwe] = 1 add ress of first rww error 3 dflash_mcr[peg] = 0 address of first fpec error 4 dflash_mcr[edc] = 1 address of first ecc single error correction
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 849 the user test 0 register allows to control the wa y in which the flash memory content check is done. bits mre, mrv, ais, eie, and dsi[7:0] of the user test 0 register are not accessible whenever dflash_mcr[done] or dflash_u t0[aid] are low: reading returns indeterminate data while writing has no effect. offset: 0x0003c access: read/write 0123456789101112131415 r ute0000000 dsi w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 000000000 x mre mrv eie ais aie aid w reset 0000000000000001 figure 30-33. dflash user test 0 register (dflash_ut0) table 30-49. dflash_ut0 field descriptions field description ute user test enable this status bit gives indication when user test is enabled. all bits in dflash_ut0-2 and dflash_umisr0-4 are locked when this bit is 0. this bit is not writable to a 1, bu t may be cleared. the reset value is 0. the method to set this bit is to provide a password, and if the password matches, the ute bit is set to reflect the status of enabled, and is enabl ed until it is cleared by a register write. for ute the password 0xf9f99999 must be written to the dflash_ut0 register. dsi data syndrome input these bits represent the input of syndrome bits of ecc logic used in the ecc logic check. bits dsi[7:0] correspond to the 8 syndrome bits on a double word. these bits are not accessible whenever dflash_m cr[done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 the syndrome bit is forced at 0. 1 the syndrome bit is forced at 1. x reserved this bit can be written and its value can be read back, but there is no function associated. this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 850 freescale semiconductor mre margin read enable mre enables margin reads to be done. this bit, combined with mrv, enables regular user mode reads to be replaced by margin reads. margin reads are only active during array integrit y checks; normal user reads are not affected by mre. this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 margin reads are not enabled. all reads are user mode reads. 1 margin reads are enabled. mrv margin read value if mre is high, mrv selects the margin level that is being checked. margin can be checked to an erased level (mrv = 1) or to a programmed level (mrv = 0). this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 zeros (programmed) margin reads are requested (if mre = 1). 1 ones (erased) margin reads are requested (if mre = 1). eie ecc data input enable eie enables the ecc logic check operation to be done. this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 ecc logic check is not enabled. 1 ecc logic check is enabled. ais array integrity sequence ais determines the address sequence to be used during array integrity checks or margin read. the default sequence (ais = 0) is meant to replicate sequences normal user code follows, and thoroughly checks the read propagation paths. this sequence is proprietary. the alternative sequence (ais = 1) is just logically sequential. proprietary sequence is forbidden in margin read. it should be noted that the time to run a sequential sequence is significantly shorter than the time to run the proprietary sequence. this bit is not accessible whenever dflash_mcr [done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. 0 array integrity sequence is proprietary sequence. 1 array integrity or margin read sequence is sequential. aie array integrity enable aie set to 1 starts the array integrity check done on all selected and unlocked blocks. the pattern is selected by ais, and the misr (d flash_umisr0-4) can be checked after the operation is complete, to determine if a correct signature is obtained. aie can be set only if dflash_mcr[ers], df lash_mcr[pgm], and dflash_mcr[ehv] are all low. 0 array integrity checks are not enabled. 1 array integrity checks are enabled. aid array integrity done aid will be cleared upon an array integrity check being enabled (to signify the operation is on-going). once completed, aid will be set to indicate that the array integrity c heck is complete. at this time the misr (dflash_umisr0-4) can be checked. 0 array integrity check is on-going. 1 array integrity check is done. table 30-49. dflash_ut0 field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 851 30.5.2.7 dflash user test 1 register (dflash_ut1) the dflash_ut1 register allows to enable the ch ecks on the ecc logic related to the 32 lsb of the double word. the user test 1 register is not accessible whenever dflash_mcr[ done] or dflash _ut0[aid] are low: reading returns indeterminate data while writing has no effect. 30.5.2.8 dflash user test 2 register (dflash_ut2) the dflash_ut2 register allows to enable the ch ecks on the ecc logic related to the 32 msb of the double word. the user test 2 register is not accessible whenever dflash_mcr[ done] or dflash _ut0[aid] are low: reading returns indeterminate data while writing has no effect. address offset: 0x00040 access: read/write 0123456789101112131415 r dai[31:16] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai[15:0] w reset 0000000000000000 figure 30-34. dflash user test 1 register (dflash_ut1) table 30-50. dflash_ut1 field descriptions field description dai[31:16] data array input, bits 31-0 these bits represent the input of even word of ecc lo gic used in the ecc logic check. bits dai[31:00] correspond to the 32 array bits representing word 0 within the double word. 0 the array bit is forced at 0. 1 the array bit is forced at 1.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 852 freescale semiconductor 30.5.2.9 dflash user multiple input si gnature register 0 (dflash_umisr0) the dflash_umisr0 provides a means to evaluate the array integrity. the dflash_umisr0 represents th e bits 31:0 of the whole 144 bits word (2 double words including ecc). the dflash_umisr0 is not accessible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. offset: 0x00044 reset value: 0x0000_0000 0123456789101112131415 r dai[63:48] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r dai[47:32] w reset 0000000000000000 figure 30-35. dflash user test 2 register (dflash_ut2) table 30-51. dflash_ut2 field descriptions field description dai[63:32] data array input, bits 63-32 these bits represent the input of odd word of ecc logic used in the ecc logi c check. bits dai[63:32] correspond to the 32 array bits representing word 1 within the double word. 0 the array bit is forced at 0. 1 the array bit is forced at 1.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 853 30.5.2.10 dflash user multiple input signature register 1 (dflash_umisr1) the dflash_umisr1 provides a mean to evaluate the array integrity. the dflash_umisr1 represents th e bits 63:32 of the w hole 144 bits word (2 double words including ecc). the dflash_umisr1 is not accessible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. address offset: 0x00048 reset value: 0x0000_0000 0123456789101112131415 r ms[31:16] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[15:0] w reset 0000000000000000 figure 30-36. dflash user multiple input signature register 0 (dflash_umisr0) table 30-52. dflash_umisr0 field descriptions field description ms[31:0] multiple input signature, bits 31?0 these bits represent t he misr value obtained accumulating the bits 31:0 of all the pages read from the flash memory. the ms can be seeded to any value by writing the dflash_umisr0 register.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 854 freescale semiconductor 30.5.2.11 dflash user multiple input signature register 2 (dflash_umisr2) the dflash_umisr2 provides a mean to evaluate the array integrity. the dflash_umisr2 represents th e bits 95:64 of the w hole 144 bits word (2 double words including ecc). the dflash_umisr2 is not accessible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. address offset: 0x0004c reset value: 0x0000_0000 0123456789101112131415 r ms[63:48] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[47:32] w reset 0000000000000000 figure 30-37. dflash user multiple input signature register 1 (dflash_umisr1) table 30-53. dflash_umisr1 field descriptions field description ms[63:32] multiple input signature, bits 63-32 these bits represent the misr value obtained accumu lating the bits 63:32 of all the pages read from the flash memory. the ms can be seeded to any value by writing the dflash_umisr1.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 855 30.5.2.12 dflash user multiple input signature register 3 (dflash_umisr3) the dflash_umisr3 provides a mean to evaluate the array integrity. the dflash_umisr3 represents th e bits 127:96 of the whole 144 bits word (2 double words including ecc). the dflash_umisr3 is not accessible whenever dflash_mcr[done] or dflash_ut0[aid] are low: reading returns indeterminate data while writing has no effect. address offset: 0x00050 reset value: 0x0000_0000 0123456789101112131415 r ms[95:80] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[79:64] w reset 0000000000000000 figure 30-38. dflash user multiple input signature register 2 (dflash_umisr2) table 30-54. dflash_umisr2 field descriptions field description ms[95:64] multiple input signature, bits 95-64 these bits represent the misr value obtained accumulating the bi ts 95:64 of all the pages read from the flash memory. the ms can be seeded to any val ue by writing the dflash_umisr2.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 856 freescale semiconductor 30.5.2.13 dflash user multiple input signature register 4 (dflash_umisr4) the multiple input signature register provide s a mean to evaluate the array integrity. the user multiple input signature re gister 4 represents the ecc bits of the whole 144 bits word (2 double words including ecc): bits 23-168:15 are ecc bits for the odd double word, and bits 7-024:31 are the ecc bits for the even double word ; bits 27-264:5 and 11-1020:21 of mi sr are respectively the double and single ecc error detection for odd and even double word. the dflash_umisr4 register is not acces sible whenever dflash_mcr[done] or dflash_ut0[aid] are low: read ing returns indeterminate data while writing has no effect. address offset: 0x00054 access: read/write 0123456789101112131415 r ms[127:112] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[111:96] w reset 0000000000000000 figure 30-39. dflash user multiple input signature register 3 (dflash_umisr3) table 30-55. dflash_umisr3 field descriptions field description ms[127:96] multiple input signature, bits 127096 these bits represent the misr value obtained accumu lating the bits 127:96 of all the pages read from the flash memory. the ms can be seeded to any value by writing the dflash_umisr3.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 857 30.6 programming considerations in the following sections, register names can refer to the cflash or df lash versions of those registers. thus, for example, the term mc r can refer to the cflash_mcr or dflash_mcr, based on context. 30.6.1 modify operation all modify operations of the flash memory module are managed th rough the flash memory user registers interface. all the sectors of the flas h memory module belong to th e same partition (bank), therefore when a modify operation is active on some sectors no read access is pos sible on any other sector (read-while-write is not supported). during a flash memory modify operati on any attempt to read any flash me mory location will output invalid data and bit mcr[rwe] will be automatically set. this means th at the flash memory module is not fetchable when a modify operation is active and these commands must be executed from another memory (internal sram or another flash memory module). address offset: 0x00058 reset value: 0x0000_0000 0123456789101112131415 r ms[159:144] w reset 0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r ms[143:128] w reset 0000000000000000 figure 30-40. dflash user multiple input signature register 4 (dflash_umisr4) table 30-56. dflash_umisr4 field descriptions field description ms[159:128] multiple input signature, bits 159-128 these bits represent the misr value obtained accumulating: ? the 8 ecc bits for the even double word (on ms[135:128]); ? the single ecc error detection for even double word (on ms138); ? the double ecc error detection for even double word (on ms139); ? the 8 ecc bits for the odd double word (on ms[151:144]); ? the single ecc error detection for odd double word (on ms154); ? the double ecc error detection for odd double word (on ms155). the ms can be seeded to any value by writing the dflash_umisr4 register.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 858 freescale semiconductor if during a modify operatio n a reset occurs, the operation is suddenly terminated and the macrocell is reset to read mode. the data integrity of the flash me mory section where the modify operation has been terminated is not guaranteed: th e interrupted flash memory modify operation must be repeated. in general each modify operation is st arted through a sequence of three steps: 1. the first instruction is used to select the desired operation by set ting its corresponding selection bit in mcr (pgm or ers) or ut0 (mre or eie). 2. the second step is the definiti on of the operands: the address and the data for programming or the sectors for erase or margin read. 3. the third instruction is used to start the mo dify operation, by setting mcr[ehv] or ut0[aie]. once selected, but not yet started, one operation can be canceled by rese tting the operation selection bit. a summary of the available flash memo ry modify operations is shown in table 30-57 . once the mcr[ehv] bit (or ut0[aie]) is set, a ll the operands can no more be modified until the mcr[done] bit (or ut0[aid]) is high. in general each modify operation is co mpleted through a sequence of four steps: 1. wait for operation completion: wait for th e mcr[done] bit (or ut0[aid]) to go high. 2. check operation result: check the mcr[peg] bi t (or compare umisr0-4 with expected value). 3. switch off fpec by resetting th e mcr[ehv] bit (or ut0[aie]). 4. deselect current operation by clearing the m cr[pgm] / mcr[ers] fields (or ut0[mre] /ut0[eie]). if the device embeds more than one flash memory module and a modify operatio n is on-going on one of them, then it is forbidden to start any other modify operation on the other flash memory modules. in the following all the possible modify operations are described and some examples of the sequences needed to activate them are presented. 30.6.2 double word program a flash memory program sequence operates on a ny double word within the flash memory core. as many as two words within the double word may be altered in a single program operation. table 30-57. flash memory modify operations operation select bit operands start bit double word program mcr[pgm] address and data by interlock writes mcr[ehv] sector erase mcr[ers] lms mcr[ehv] array integrity check none lms ut0[aie] margin read ut0[mre] ut 0[mrv] + lms ut0[aie] ecc logic check ut0[eie] ut0[dsi], ut1, ut2 ut0[aie]
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 859 ecc is handled on a 64-bit boundary. thus, if only one word in any given 64-bit ecc segment is programmed, the adjoining word (in that segment) should not be pr ogrammed since ec c calculation has already completed for that 64-bit segment. attempts to program the adjoining word will probably result in an operation failure. it is reco mmended that all programming operations be of 64 bits. the programming operation should completely fill selected ecc segments within the double word. programming changes the value stored in an array b it from logic 1 to logic 0 only. programming cannot change a stored logic 0 to a logic 1. addresses in locked/disabled blocks cannot be programmed. the user may program the values in any or all of two words of a double word with a single program sequence. double word-bound words have addresses that differ only in address bit 2. the program operation consists of the following sequence of events: 1. change the value in the mcr[pgm] bit from 0 to 1. 2. ensure the block that contains the address to be programmed is unlocked. a) write the first address to be programmed with the program data. b) the flash memory modul e latches address bits (22:3) at this time. c) the flash memory module latches data written as well. d) this write is referred to as a program data in terlock write. an interlock write may be as large as 64 bits, and as small as 32 bits (depending on the cpu bus). 3. if more than 1 word is to be programmed, write the a dditional address in the double word with data to be programmed. this is referr ed to as a program data write. the flash memory module ignor es address bits (22:3) for program data writes. the eventual unwritten data word default to 0xffffffff. 4. write a logic 1 to the mcr[ehv] bit to start the internal program sequence or skip to step 9 to terminate. 5. wait until the mcr[done] bit goes high. 6. confirm that the mcr[peg] bit is 1. 7. write a logic 0 to the mcr[ehv] bit. 8. if more addresses are to be programmed, return to step 2. 9. write a logic 0 to the mcr[pgm] bi t to terminate the program operation. program may be initiated with the 0-to-1 transition of the mcr[ pgm] bit or by clea ring the mcr[ehv] bit at the end of a previous program. the first write after a progr am is initiated determines the page address to be programmed. this first write is referred to as an interlock write. the interlock wr ite determines if the shadow , test or norma l array space will be programmed by ca using the mcr[peas] field to be set/cleared. an interlock write must be performed before se tting mcr[ehv]. the user may terminate a program sequence by clearing mcr[pgm] prior to setting mcr[ehv].
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 860 freescale semiconductor after the interlock write, additiona l writes only affect the data to be programmed at the word location determined by address bit 2. unwritten locations defaul t to a data value of 0xf fffffff. if multiple writes are done to the same location the data fo r the last write is used in programming. while mcr[done] is low and mcr[ehv] is high, the user may clear ehv, resulting in a program abort. a program abort forces the module to step 8 of the program sequence. an aborted program will result in mcr[peg] bei ng set low, indicating a fa iled operation. mcr[done] must be checked to know when the aborting command has completed. the data space being operated on befo re the abort will cont ain indeterminate data. this may be recovered by repeating the same program instruction or executing an erase of the affected blocks. example 30-1. double word program of data 0x55aa55aa at address 0x00aaa8 and data 0xaa55aa55 at address 0x00aaac mcr = 0x00000010; /* set pgm in mcr: select operation */ (0x00aaa8) = 0x55aa55aa; /* latch address and 32 lsb data */ (0x00aaac) = 0xaa55aa55; /* latch 32 msb data */ mcr = 0x00000011; /* set ehv in mcr: operation start */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); status = mcr & 0x00000200; /* check peg flag */ mcr = 0x00000010; /* reset ehv in mcr: operation end */ mcr = 0x00000000; /* reset pgm in mcr: deselect operation */ 30.6.3 sector erase erase changes the value stored in all bits of the selected block(s) to logic 1. an erase sequence operates on any combination of blocks (sectors) in the low, mid or high address space, or the shadow sector (if available) . the test block cannot be erased. the erase sequence is fully automated within the flas h memory. the user only need s to select the blocks to be erased and initiate the erase sequence. locked/disabled blocks cannot be erased. if multiple blocks are selected fo r erase during an erase sequence, no specific operation order must be assumed. the erase operation consists of the following sequence of events: 1. change the value in the mcr[ers] bit from 0 to 1. 2. select the block(s) to be erased by writing 1s to the appropriate bit(s) in the lms register. if the shadow sector is to be erased, th is step may be skipped, and lms is ignored. note that lock and select are i ndependent. if a block is selected and locked, no erase will occur. 3. write to any address in flash memory. this is referred to as an erase interlock write. 4. write a logic 1 to the mcr[ehv] bit to start th e internal erase sequence or skip to step 9 to terminate. 5. wait until the mcr[done] bit goes high.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 861 6. confirm mcr[peg] = 1. 7. write a logic 0 to the mcr[ehv] bit. 8. if more blocks are to be erased, return to step 2. 9. write a logic 0 to the mcr[ers] bi t to terminate the erase operation. after setting mcr[ers], one write, referred to as an interlock write, must be performed before mcr[ehv] can be set to 1. data words written during erase sequence interlock writes are ignored. the user may terminate the erase seque nce by clearing ers before setting ehv. an erase operation may be aborte d by clearing mcr[ehv] assuming mcr[done] is low, mcr[ehv] is high, and mcr[esus] is low. an erase abort forces the module to step 8 of the erase sequence. an aborted erase will result in mcr[peg] being set low, indicating a failed operation. mcr[done] must be checked to know when the aborting command has completed. the block(s) being operated on before the abort cont ain indeterminate data. th is may be recovered by executing an erase on the affected blocks. the user may not abort an erase sequence while in erase suspend. example 30-2. erase of sectors b0f1 and b0f2 mcr = 0x00000004; /* set ers in mcr: select operation */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors to erase */ (0x000000) = 0xffffffff; /* latch a flash memory address with any data */ mcr = 0x00000005; /* set ehv in mcr: operation start */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); status = mcr & 0x00000200; /* check peg flag */ mcr = 0x00000004; /* reset ehv in mcr: operation end */ mcr = 0x00000000; /* reset ers in mcr: deselect operation */ 30.6.3.1 erase suspend/resume the erase sequence may be suspended to allo w read access to the flash memory core. it is not possible to program or to erase during an erase suspend. during erase suspend, all reads to blocks targ eted for erase return indeterminate data. an erase suspend can be initiated by changing the va lue of the mcr[esus] bit from 0 to 1. mcr[esus] can be set to 1 at any time when mcr[ers] and mcr[ehv] are high and mcr[pgm] is low. a 0-to-1 transition of mcr[esus] causes th e module to start the sequence th at places it in erase suspend. the user must wait until mcr[done] = 1 before the module is suspended and further actions are attempted. mcr[done] will go high no more than t esus after mcr[esus] is set to 1.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 862 freescale semiconductor once suspended, the array may be r ead. flash memory core reads whil e mcr[esus] = 1 from the block(s) being erased return indeterminate data. example 30-3. sector erase suspend mcr = 0x00000007; /* set esus in mcr: erase suspend */ do /* loop to wait for done=1 */ { tmp = mcr; /* read mcr */ } while ( !(tmp & 0x00000400) ); notice that there is no need to clear mcr[ehv] an d mcr[ers] in order to perform reads during erase suspend. the erase sequence is resumed by wr iting a logic 0 to mcr[esus]. mcr[ehv] must be set to 1 before mcr[es us] can be cleared to resume the operation. the module continues the erase sequen ce from one of a set of predefined points. th is may extend the time required for the erase operation. example 30-4. sector erase resume mcr = 0x00000005; /* reset esus in mcr: erase resume */ 30.6.3.2 user test mode the user can perform specific tests to check flash memory module integrity by putting the flash memory module in user test mode. three kinds of test can be performed: ? array integrity self check ? margin read ? ecc logic check the user test mode is equivalent to a modify opera tion: read accesses attempted by the user during user test mode generates a read-whi le-write error (mcr[rwe] set). it is not allowed to perform user test operations on the test and shadow sectors. 30.6.3.2.1 array integrity self check array integrity is checked using a predefined addr ess sequence (proprietary), and this operation is executed on selected and unlocked bloc ks. once the operation is completed, the results of the reads can be checked by reading the misr value (stored in umisr0 ?4), to determine if an incorrect read, or ecc detection was noted. the internal misr calculator is a 32-bit register. the 128-bit data, the 16 ecc data, and the single and double ecc errors of the two double words are therefore captured by the misr through five di fferent read accesses at the same location. the whole check is done through five comple te scans of the memory address space: 1. the first pass will scan only bits 31:0 of each page.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 863 2. the second pass will scan only bits 63:32 of each page. 3. the third pass will scan only bits 95:64 of each page. 4. the fourth pass will scan only bits 127:96 of each page. 5. the fifth pass will scan only the ecc bits (8 + 8) and the single and double ecc errors (2 + 2) of both double words of each page. the 128-bit data and the 16 ecc data are sampled be fore the eventual ecc correction, while the single and double error flags are samp led after the ecc evaluation. only data from existing and unlocke d locations are captured by the misr. the misr can be seeded to any value by writing the umisr0?4 registers. the array integrity self check consists of the following sequence of events: 1. set ut0[ute] by writing the related password in ut0. 2. select the block(s) to be checked by writing 1s to the appropriate bit(s) in the lms register. note that lock and select are independent. if a block is select ed and locked, no array integrity check will occur. 3. set eventually ut0[ais] bit for a sequential addressing only. 4. write a logic 1 to the ut0[aie] bi t to start the array integrity check. 5. wait until the ut0[aid] bit goes high. 6. compare umisr0-4 content with the expected result. 7. write a logic 0 to the ut0[aie] bit. 8. if more blocks are to be checked, return to step 2. it is recommended to leave ut0[ais] at 0 and use th e proprietary address sequence that checks the read path more fully, although this seque nce takes more time. during the exec ution of the array integrity check operation it is forbidden to modify the content of block select (lms) and lock (lml, sll) registers, otherwise the misr value can vary in an unpredictable way. while ut 0[aid] is low and ut0[aie] is high, the user may clear aie, resulti ng in a array integrity check abort. ut0[aid] must be checked to know wh en the aborting command has completed. example 30-5. array integrity check of sectors b0f1 and b0f2 ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors */ ut0 = 0x80000002; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content*/ data1 = umisr1; /* read umisr1 content*/ data2 = umisr2; /* read umisr2 content*/ data3 = umisr3; /* read umisr3 content*/ data4 = umisr4; /* read umisr4 content*/ ut0 = 0x00000000; /* reset ute and aie in ut0: operation end */
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 864 freescale semiconductor 30.6.3.2.2 margin read margin read procedure (either margin 0 or margin 1), can be run on unlocked blocks in order to unbalance the sense amplifiers, respect to standard read conditi ons, so that all the read accesses reduce the margin vs. 0 (ut0[mrv] = 0) or vs. 1 (ut0[mrv] = 1). lo cked sectors are ignored by misr calculation and ecc flagging. the results of the margin reads can be checked comparing chec ksum value in umisr0?4. since margin reads are done at voltages that differ th an the normal read voltage, lifetime expectancy of the flash memory macrocell is imp acted by the execution of margin read s. doing margin reads repetitively results in degradation of the flash memory array, and shorten expected lifetime experienced at normal read levels. for these reasons the margin read usage is allo wed only in factory, while it is forbidden to use it inside the user application. in any case the charge losses detected through the marg in read cannot be considered failures of the device and no failure analysis will be opened on them. the margin read se tup operation consists of the following sequence of events: 1. set ut0[ute] by writing the related password in ut0. 2. select the block(s) to be checked by writing 1s to the appropriate bit(s) in the lms register. note that lock and select are inde pendent. if a block is selected and locked, no array integrity check will occur. 3. set t0.ais bit for a sequential addressing only. 4. change the value in the ut0[mre] bit from 0 to 1. 5. select the margin level: ut0[mrv]=0 fo r 0s margin, ut0[mrv]=1 for 1s margin. 6. write a logic 1 to the ut0[aie] bit to start the ma rgin read setup or skip to step 6 to terminate. 7. wait until the ut0[aid] bit goes high. 8. compare umisr0-4 content with the expected result. 9. write a logic 0 to the ut0[aie] , ut0[mre], and ut0[mrv] bits. 10. if more blocks are to be checked, return to step 2. it is mandatory to leave ut0[ais] at 1 and use the linear address sequence, the usage of the proprietary sequence in margin read is forbidden. during the execution of the margin read operation it is forbidden to modify the content of block select (lms) and lock (lml, sll) registers, otherwise the misr value can vary in an unpredictable way. the read accesses will be done with the addition of a proper number of wait states to guarantee the correctness of the result. while ut0[aid] is low and ut0[aie] is high, the user may clear aie, resulting in a array integrity check abort. ut0[aid] must be checked to know wh en the aborting command has completed. example 30-6. margin read setup versus 1s umisr0 = 0x00000000; /* reset umisr0 content */ umisr1 = 0x00000000; /* reset umisr1 content */ umisr2 = 0x00000000; /* reset umisr2 content */ umisr3 = 0x00000000; /* reset umisr3 content */
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 865 umisr4 = 0x00000000; /* reset umisr4 content */ ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ lms = 0x00000006; /* set lsl2-1 in lms: select sectors */ ut0 = 0x80000004; /* set ais in ut0: select operation */ ut0 = 0x80000024; /* set mre in ut0: select operation */ ut0 = 0x80000034; /* set mrv in ut0: select margin versus 1?s */ ut0 = 0x80000036; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content*/ data1 = umisr1; /* read umisr1 content*/ data2 = umisr2; /* read umisr2 content*/ data3 = umisr3; /* read umisr3 content*/ data4 = umisr4; /* read umisr4 content*/ ut0 = 0x80000034; /* reset aie in ut0: operation end */ ut0 = 0x00000000; /* reset ute, mre, mrv, ais in ut0: deselect op. */ to exit from the margin read mode, a read reset operation must be executed. 30.6.3.2.3 ecc logic check ecc logic can be checked by forcing the input of ecc logic: the 64 bits of data and the 8 bits of ecc syndrome can be individually forced and they will drive simultane ously at the same value the ecc logic of the whole page (2 double words). the results of the ecc logic check can be verified by reading the misr value. the ecc logic check operation consists of the following sequence of events: 1. set ut0[ute] by writing the related password in ut0. 2. write in ut1[dai31?0] and ut2[ dai63?32] the double word input value. 3. write in ut0[dsi7?0] the syndrome input value. 4. select the ecc logic check: writ e a logic 1 to the ut0[eie] bit. 5. write a logic 1 to the ut0[aie] bit to start the ecc logic check. 6. wait until the ut0[aid] bit goes high. 7. compare umisr0?4 content with the expected result. 8. write a logic 0 to the ut0[aie] bit. notice that when ut0[aid] is lo w, umisr0?4, ut1?2, and bits mre, mrv, eie, ais, and dsi7?0 of ut0 are not accessible: read ing returns indeterminate data and write has no effect. example 30-7. ecc logic check ut0 = 0xf9f99999; /* set ute in ut0: enable user test */ ut1 = 0x55555555; /* set dai31-0 in ut1: even word input data */ ut2 = 0xaaaaaaaa; /* set dai63-32 in ut2: odd word input data */ ut0 = 0x80ff0000; /* set dsi7-0 in ut0: syndrome input data */ ut0 = 0x80ff0008; /* set eie in ut0: select ecc logic check */ ut0 = 0x80ff000a; /* set aie in ut0: operation start */ do /* loop to wait for aid=1 */ { tmp = ut0; /* read ut0 */ } while ( !(tmp & 0x00000001) ); data0 = umisr0; /* read umisr0 content (expected 0x55555555) */
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 866 freescale semiconductor data1 = umisr1; /* read umisr1 content (expected 0xaaaaaaaa) */ data2 = umisr2; /* read umisr2 content (expected 0x55555555) */ data3 = umisr3; /* read umisr3 content (expected 0xaaaaaaaa) */ data4 = umisr4; /* read umisr4 content (expected 0x00ff00ff) */ ut0 = 0x00000000; /* reset ute, aie and eie in ut0: operation end */ 30.6.3.3 error correction code (ecc) the flash memory module provides a me thod to improve the reliability of the data stored in flash memory: the usage of an error correction code . the word size is fixed at 64 bits. eight ecc bits, programmed to gua rantee a single error correc tion and a double error detection (sec-ded), are asso ciated to each 64-bit double word. ecc circuitry provides correcti on of single bit faults and is used to achieve auto motive reliability targets. some units will experience single bit corrections th roughout the life of the product with no impact to product reliability. 30.6.3.3.1 ecc algorithms the flash memory module supports one ecc algorithm: ?all 1s no erro r?. a modified hamming code is used that ensures the all erased st ate (that is, 0xffff.....ffff) data is a va lid state, and will not cause an ecc error. this allows the user to perfor m a blank check after a sector erase operation. 30.6.3.4 eeprom emulation the chosen ecc algorithm allows some bit manipulations so that a doubl e word can be rewritten several times without needing an erase of the sector. this allo ws to use a double word to store flags useful for the eeprom emulation. as an example, th e chosen ecc algorithm allows to start from an all 1s double word value and rewrite whichever of its four 16-bit half-words to an all 0s content by keeping the same ecc value. table 30-58 shows a set of double words sharing the same ecc value. table 30-58. bit manipulation: doubl e words with the same ecc value double word ecc all 1s no error 0xffff_ffff_ffff_ffff 0xff 0xffff_ffff_ffff_0000 0xff 0xffff_ffff_0000_ffff 0xff 0xffff_0000_ffff_ffff 0xff 0x0000_ffff_ffff_ffff 0xff 0xffff_ffff_0000_0000 0xff 0xffff_0000_ffff_0000 0xff 0x0000_ffff_ffff_0000 0xff 0xffff_0000_0000_ffff 0xff 0x0000_ffff_0000_ffff 0xff
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 867 when some flash memory sectors are used to perform an eeprom emulat ion, it is recommended for safety reasons to reserve at least 3 sectors to this purpose. 30.6.3.4.1 all 1s no error the all 1s no error algorith m detects as valid any double word read on a just erased sector (all the 72 bits are 1s). this option allows to perform a blank check after a sector erase operation. 30.6.3.5 protection strategy two kinds of protection are availa ble: modify protection to avoid unwanted program/erase in flash memory sectors and censored mode to avoid piracy. 30.6.3.5.1 modify protection the flash memory modify pr otection information is stor ed in nonvolatile flash memo ry cells located in the testflash. this information is read once during the flash memory initia lization phase following the exiting from reset and is stored in volatile registers that act as actuators. the reset state of all the volatile modify protection registers is the protected state. all the nonvolatile modify protecti on registers can be programmed through a normal double word program operation at the related locations in testflash. the nonvolatile modify protecti on registers cannot be erased. ? the nonvolatile modify protection registers are phys ically located in testflash their bits can be programmed to 0 only once and they can no more be restored to 1. ? the volatile modify protection re gisters are read/write registers whose bits can be written at 0 or 1 by the user application. a software mechanism is provided to independently lock/unlock each low, mi d, and high address space block against program and erase. software locking is done through the lml register. an alternate means to enable software locking for blocks of low address spa ce only is through the sll. all these registers have a nonvolatil e image stored in testflash (nvl ml, nvsll), so that the locking information is kept on reset. 0x0000_0000_ffff_ffff 0xff 0xffff_0000_0000_0000 0xff 0x0000_ffff_0000_0000 0xff 0x0000_0000_0000_0000 0xff table 30-58. bit manipulation: double word s with the same ecc value (continued) double word ecc all 1s no error
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 868 freescale semiconductor on delivery the testflash nonvolatile image is at all 1s, meaning all sectors are locked. by programming the nonvolatile lo cations in testflash the sel ected sectors can be unlocked. being the testflash one-time progr ammable (that is, not erasable), once unlocked the sectors cannot be locked again. of course, on the contrary, all the vol atile registers can be written at 0 or 1 at any time, therefore the user application can lock and unlock sectors when desired. 30.6.3.5.2 censored mode the censored mode information is stored in nonvolatile flash memory ce lls located in the shadow sector. this information is read once during the flash memo ry initialization phase following the exiting from reset and is stored in volatile registers that act as actuators. the reset state of all the volatile censored mode registers is the protected state. all the nonvolatile censored mode registers can be programmed through a normal double word program operation at the related locations in the shadow sector. the nonvolatile censored mode registers can be erased by erasing the shadow sector. ? the nonvolatile censored mode re gisters are physically located in the shadow sector their bits can be programmed to 0 and restored to 1 by erasing the shadow sector. ? the volatile censored mode registers are re gisters not accessible by the user application. the flash memory module provides two levels of protecti on against piracy: ? if bits cw15:0 of nvscc0 are programmed at 0x55aa and nvsc1 = nvscc0 the censored mode is disabled, while al l the other possible values enable the censored mode. ? if bits sc15:0 of nvscc0 are programmed at 0x55aa and nvsc1 = nvscc0 the public access is disabled, while all the other possi ble values enable the public access. the parts are delivered to the user with censored mode and public access disabled. 30.7 platform flash memory controller 30.7.1 introduction the platform flash memory controller acts as the interface between the system bus (ahb-lite 2.v6) and as many as two banks of integrated flash memory arrays (program and da ta). it intelligently converts the protocols between the system bus and the dedicated flash memory array interfaces. a block diagram of the e200z0h powe r architecture reduced product plat form (rpp) reference design is shown below in figure 30-41 with the platform flash memory controller module and its attached off-platform flash memory arrays highlighted.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 869 figure 30-41. power architecture e200z0h rpp reference platform block diagram the module list includes: ? power architecture e200z0h (harvard) core ? ahb crossbar switch ?lite? (xbar) ? memory protection unit (mpu) ? platform flash memory controller with connections to 2 memory banks ? platform sram memory controller (pram) ? ahb-to-ips/apb bus controller (pbridge) for access to on- and off-platform slave modules ? interrupt controller (intc) ? 4-channel system timers (stm) ? software watchdog timer (swt) ? error correction status module (ecsm) xbar memarray rpp_z0h_ref s0 s2 m0 s7 memarray pram pflash ips/apb intc ahb platform flash memory controller branch unit load/store i-fetcher dispatch gpr integer unit e200z0h core p_i_h* p_d_h* m1 m2 mpu on-platform irqs off-platform irqs debug unit m3 stm ips bus ips+apb bus flash regs ips+apb slave modules memarray flash regs bank0 bank1 ecsm swt
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 870 freescale semiconductor throughout this document, several im portant terms are used to describe the platform flash memory controller module and its connecti ons. these terms are defined here: ? port ? this is used to describe the amba-ahb connection(s) into the platform flash memory controller. from an architectural and program ming model viewpoint, the definition supports as many as two ahb ports, even though this speci fic controller only supports a single ahb connection. ? bank ? this term is used to describe the att ached flash memories. from the platform flash memory controller?s perspective, there may be one or two attached banks of flash memory. the code flash memory is required a nd always attached to bank0. additi onally, there is a data flash memory attached to bank1. the platform flash memo ry controller interface supports two separate connections, one to each memory bank. ? array ? within each memory bank, there is one flash memory array instantiations. ? page ? this value defines the number of bits read from the flash memory array in a single access. for this controller and memory, th e page size is 128 bits (16 bytes). the nomenclature ?page buffers and ?line buffers? are used interchangeably. 30.7.1.1 overview the platform flash memory controller supports a 32- bit data bus width at the ahb port and connections to 128-bit read data interf aces from two memory banks, where each bank contains one instantiations of the flash memory array. one flash memo ry bank is connected to the code flash memory and the other bank is connected to the optional data flash memory. the me mory controller capabiliti es vary between the two banks with each bank?s functionality optimized with the typical use cases associated with the attached flash memory. as an example, the platform flash memo ry controller logic associated with the code flash memory bank contains a four-entry page buffer, each entry containing 128 bits of data (1 flash memory page) plus an associated controller that prefetches sequential lines of data from the flash memory array into the buffer, while the controller logic associat ed with the data flash memory bank only supports a 128-bit register that serves as a temporary page holding register and does not support any prefetching. prefetch buffer hits from the code flash memory bank support zero-wait ahb data phase responses. ahb read requests that miss the buffers ge nerate the needed flash memory a rray access and are forwarded to the ahb upon completion, typically incurring two wait -states at an operating frequency of 60?64 mhz. this memory controller is optimi zed for applications wh ere a cacheless processor core, e.g., the power e200z0h, is connected through the platform to on-ch ip memories, e.g., flash memory and sram, where the processor and platform operate at the same frequency. for th ese applications, th e 2-stage pipeline amba-ahb system bus is effectivel y mapped directly into stages of the processor?s pipeline and zero wait-state responses for most memo ry accesses are critical for provi ding the required level of system performance. 30.7.1.2 features the following list summarizes the key features of the platfo rm flash memory controller: ? dual array interfaces support up to a total of 16 mb of flash memo ry, partitioned as two separate 8 mb banks
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 871 ? single ahb port inte rface supports a 32-bit data bus. all ahb aligned a nd unaligned reads within the 32-bit container are supported. only aligned word writes are supported. ? array interfaces support a 128- bit read data bus and a 64-bit write data bus for each bank ? interface with code flash memo ry (bank0) provides configurable read buffering and page prefetch support. four page read buffers (each 128 bits wide) and a prefetch controller are used to support single-cycle read responses (zero ahb data phase wa it-states) for hits in the buffers. the buffers implement a least recently used replaceme nt algorithm to maximize performance. ? interface with optional data fl ash memory (bank1) includes a 128- bit register to temporarily hold a single flash memory page. this logic supports single-cycle read responses (zero ahb data phase wait-states) for accesses that hit in the holdi ng register. there is no support for prefetching associated with this bank. ? programmable response for read-w hile-write sequences including support for stall-while-write, optional stall notification interr upt, optional flash memory opera tion abort, and optional abort notification interrupt ? separate and independent configur able access timing (on a per bank basis) to support use across a wide range of platforms and frequencies ? support of address-based read access timing for emulati on of other memory types ? support for reporting of single- and multi-bit flash memory ecc events ? typical operating configuration loaded into programming model by system reset 30.7.2 memory map and register description two memory maps are associated with the platform flash memory controller: one for the flash memory space and another for the program-visib le control and configur ation registers. the fl ash memory space is accessed via the amba-ahb port and the program-visible register s are accessed via the slave peripheral bus. details on both memory spaces are provided in section 30.7.2.1, memory map . there are no program-visible registers that physically reside inside the platform flash memory controller. rather, the platform flash memory controller receives control and configuration information from the flash memory array controller(s) to determine the operating configuration. these are pa rt of the flash memory array?s configuration regist ers mapped into its slave peripheral (ips) address sp ace but are described here. 30.7.2.1 memory map first, consider the flash memory space accessed vi a transactions from the platform flash memory controller?s ahb port. to support the two separate flash memo ry banks, each as large as 8 mb in size, the platform flash memory controller uses address bit 23 (ha ddr[23]) to steer the access to the appropriate memory bank. in addition to the actual flash memory regions, the system memory map includes shadow and test sectors. the program-visible control and configurat ion registers associated with each memory ar ray are included in the slave peripheral address region. the system memory map defines one c ode flash memory array and one data flash memory array. see table 30-59 .
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 872 freescale semiconductor for additional information on the address-based read access timing for emulation of other memory types, see section 30.8.11, wait-state emulation . next, consider the memory map associated wi th the control and configuration registers. regardless of the number of populated banks or the num ber of flash memory arra ys included in a given bank, the configuration of th e platform flash memory c ontroller is wholly specif ied by the platform flash memory controller registers associated with code flash memory array 0. the code array0 re gister settings define the operating behavior of both flash memory banks; it is reco mmended that the platform flash memory controller registers for all physically present arrays be set to the code flash memory array0 values. note to perform program and erase operations , the control registers in the actual referenced flash memory array must be programmed, but the configuration of the platform flash memory controll er module is defined by the platform flash controller regi sters of code array0. the 32-bit memory map for the platform flash memo ry controller control registers is shown in table 30-60 . the base address of the controller is 0xc3f8_8000. table 30-59. flash memory-related regions in the system memory map start address end address size [kb] region 0x0008_0000 0x000f_ffff 512 code flash memory array 1 0x0010_0000 0x0017_ffff 512 code flash memory array 2 0x0018_0000 0x001f_ffff 512 reserved 0x0020_0000 0x0027_ffff 16 code flash memory array 0: shadow sector 0x0028_0000 0x002f_ffff 1536 reserved 0x0040_0000 0x0040_3fff 16 code flash memory array 0: test sector 0x0040_4000 0x007f_ffff 4078 reserved 0x0080_0000 0x0080_ffff 64 data flash memory array 0 0x0081_0000 0x00bf_ffff 4032 reserved 0x00c0_0000 0x00c7_ffff 16 data flash memory array 0: test sector 0x00c8_0000 0x00ff_ffff 3584 reserved 0x0100_0000 0x1fff_ffff 50 7904 emulation mapping 0xc3f8_8000 0xc3f8_bfff 16 code flash memory array 0 configuration 0xc3f8_c000 0xc3f8_ffff 16 data flash memory array 0 configuration table 30-60. platform flash memory controller 32-bit memory map address offset register location 0x1c platform flash configuration register 0 (pfcr0) on page 873
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 873 see the MPC5606BK data sheet for detailed se ttings for different values of frequency. 30.7.2.2 register description this section details the individual registers of the platform flash memory controller. flash memory configuration registers must be written only with 32-bit wr ite operations to avoid any issues associated with register incoherency caused by bi ts spanning smaller-size (8- or 16-bit) boundaries. 30.7.2.2.1 platform flash confi guration register 0 (pfcr0) this register defines the configurat ion associated with the code flash memory bank0. it includes fields that provide specific information for as many as two se parate ahb ports (p0 and the optional p1). for the platform flash memory controller m odule, the fields associated with ahb port p1 are ignored. the register is described in figure 30-42 and table 30-61 . note do not execute code from flash memory when you are programming pfcr0. if you wish to pr ogram pfcr0, execute your application code from ram. 0x20 platform flash configuration register 1 (pfcr1) on page 876 0x24 platform flash access protection register (pfapr) on page 877 offset 0x01c access: read/write 0123456789101112131415 r bk0_apc bk0_wwsc bk0_rwsc bk0_rwwc w reset0001100011000111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bk0_rwwc 0000000 bk0_rwwc b0_p0_bcfg b0_p0_dpfe b0_p0_ipfe b0_p0_pflm b0_p0_bfe w reset1000000011101101 figure 30-42. pflash configur ation register 0 (pfcr0) table 30-60. platform flash memory controller 32-bit memory map (continued) address offset register location
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 874 freescale semiconductor table 30-61. pfcr0 field descriptions field description bk0_apc the setting for apc must be the same as rwsc. bk0_wwsc bank0 write wait-state control this field is used to control the number of wait-states to be added to the flash memory array access time for writes. this field must be set to a value appropriate to the operating frequency of the pflash. the required settings are documented in the device data sheet. higher operating frequencies require non-zero settings for this field for proper flash memory operation. this field is set to an appropriate value by hardware reset. 00000 no additional wait-states are added 00001 one additional wait-state is added 00010 two additional wait-states are added ... 11111 31 additional wait-states are added note: the platform flash memory controller does not support write wait-state control since this capability is not supported by the flash memory array. bk0_rwsc bank0 read wait-state control this field is used to control the number of wait-states to be added to the flash memory array access time for reads. this field must be set to a value corresponding to the operating frequency of the pflash and the actual read access time of the pf lash. the required settings are documented in the device datasheet. 00000 no additional wait-states are added 00001 one additional wait-state is added 00010 two additional wait-states are added ... 11111 31 additional wait-states are added note: the setting for rwsc must be the same as apc. bk0_rwwc bank0 read-while-write control this 3-bit field defines the controller response to flash memory reads while the array is busy with a program (write) or erase operation. 0?? this state should be avoided. setting to this state can cause unpredictable operation. 111 generate a bus stall for a read while write/eras e, disable the stall notification interrupt, disable the abort + abort notification interrupt 110 generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable the abort + abort notification interrupt 101 generate a bus stall for a read while write/erase, enable the operation abort, disable the abort notification interrupt 100 generate a bus stall for a read while write/erase, enable the operation abort and the abort notification interrupt this field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort and notification interrupts.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 875 b0_p0_bcfg bank0, port 0 page buffer configuration this field controls the configuration of the four pag e buffers in the pflash controller. the buffers can be organized as a pool of available resources, or with a fixed partition between instruction and data buffers. if enabled, when a buffer miss occurs, it is allocated to the least recently used buffer within the group and the just-fetched entry then marked as most re cently used. if the flash memory access is for the next-sequential line, the buffer is not marked as mo st recently used until the given address produces a buffer hit. 00 all four buffers are available for any flash memory access, that is, there is no partitioning of the buffers based on the access type. 01 reserved 10 the buffers are partitioned into two groups wit h buffers 0 and 1 allocated for instruction fetches and buffers 2 and 3 for data accesses. 11 the buffers are partitioned into two groups with buffers 0,1,2 allocated for instruction fetches and buffer 3 for data accesses. this field is set to 2b11 by hardware reset. b0_p0_dpfe bank0, port 0 data prefetch enable this field enables or disables prefetching initiated by a data read access. this field is cleared by hardware reset. prefetching can be enabled/d isabled on a per master basis at pfapr[mxpfd]. 0 no prefetching is triggered by a data read access 1 if page buffers are enabled (b0_p0_bfe = 1), prefetching is triggered by any data read access b0_p0_ipfe bank0, port 0 instruction prefetch enable this field enables or disables prefetching initiated by an instruction fetch read access. this field is set by hardware reset. prefetching can be en abled/disabled on a per master basis at pfapr[mxpfd]. 0 no prefetching is triggered by an instruction fetch read access 1 if page buffers are enabled (b0_p0_bfe = 1), prefetching is triggered by any instruction fetch read access b0_p0_pflm bank0, port 0 prefetch limit this field controls the prefetch algorithm used by the pflash controller. this field defines the prefetch behavior. in all situations when enabled, only a single prefetch is initiated on each buffer miss or hit. this field is set to 2b10 by hardware reset. 00 no prefetching is performed. 01 the referenced line is prefetched on a buffer miss, that is, prefetch on miss . 1? the referenced line is prefetched on a buffer mi ss, or the next sequential page is prefetched on a buffer hit (if not already present), that is, prefetch on miss or hit . b0_p0_bfe bank0, port 0 buffer enable this bit enables or disables page buffer read hits. it is also used to invalidate the buffers. this bit is set by hardware reset. 0 the page buffers are disabled from satisfying read requests, and all buffer valid bits are cleared. 1 the page buffers are enabled to satisfy read requests on hits. buffer valid bits may be set when the buffers are successfully filled. table 30-61. pfcr0 field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 876 freescale semiconductor 30.7.2.2.2 platform flash confi guration register 1 (pfcr1) this register defines the configur ation associated with flash memory bank1. this corresponds to the data flash memory. it includes fields th at provide specific information for as many as two separate ahb ports (p0 and the optional p1). for the platform flash memory controller module, the fiel ds associated with ahb port p1 are ignored. the register is described below in figure 30-43 and table 30-62 . note do not execute code from flash memory when you are programming pfcr1. if you wish to pr ogram pfcr1, execute your application code from ram. offset 0x020 access: read/write 0123456789101112131415 r bk1_apc bk1_wwsc bk1_rwsc bk1_rwwc w reset0001100011000111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r bk1_rwwc 0000000 bk1_rwwc 000000 b1_p0_bfe w reset1000000010000001 figure 30-43. pflash configur ation register 1 (pfcr1) table 30-62. pfcr1 field descriptions field description bk1_apc the setting for apc must be the same as rwsc. bk1_wwsc bank1 write wait-state control this field is used to control the number of wait-states to be added to the flash memory array access time for writes. this field must be set to a value appropriate to the operating frequency of the pflash. the required settings are documented in the device data sheet. higher operating frequencies require non-zero settings for this field for proper flash memory operation. this field is set to an appropriate value by hardware reset. 00000 no additional wait-states are added 00001 one additional wait-state is added 00010 two additional wait-states are added ... 11111 31 additional wait-states are added this field is ignored in single bank flash memory configurations. note: the platform flash memory controller does not support write wait-state control since this capability is not supported by the flash memory array.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 877 30.7.2.2.3 platform flash access protection register (pfapr) the pflash access protection register (pfapr) is used to control read and write accesses to the flash memory based on system master numbe r. prefetching capabilities are defi ned on a per master basis. this register also defines the arbitration mode for co ntrollers supporting two ahb ports. the register is described below in figure 30-44 and table 30-63 . the contents of the register are loaded from locat ion 0x203e00 of the shadow region in the code flash memory (bank0) array at reset. to te mporarily change the values of any of the fields in the pfapr, a write to the ips-mapped register is performed. to change the values loaded into the pfapr at reset , the word bk1_rwsc bank1 read wait-state control this field is used to control the number of wait-states to be added to the flash memory array access time for reads. this field must be set to a value corresponding to the operating frequency of the pflash and the actual read access time of the pf lash. the required settings are documented in the device data sheet. 00000 no additional wait-states are added 00001 one additional wait-state is added 00010 two additional wait-states are added ... 11111 31 additional wait-states are added this field is ignored in single bank flash memory configurations. note: the setting for rwsc must be the same as apc. bk1_rwwc bank1 read-while-write control this 3-bit field defines the controller response to flash memory reads while the array is busy with a program (write) or erase operation. 0?? this state is not supported 111 generate a bus stall for a read while write/eras e, disable the stall notification interrupt, disable the abort + abort notification interrupt 110 generate a bus stall for a read while write/erase, enable the stall notification interrupt, disable the abort + abort notification interrupt 101 generate a bus stall for a read while write/erase, enable the operation abort, disable the abort notification interrupt 100 generate a bus stall for a read while write/erase, enable the operation abort and the abort notification interrupt this field is set to 0b111 by hardware reset enabling the stall-while-write/erase and disabling the abort and notification interrupts. this field is ignored in single bank flash memory configurations. b1_p0_pfe bank1, port 0 buffer enable this bit enables or disables read hits from the 128- bit holding register. it is also used to invalidate the contents of the holding register. this bit is set by hardware reset, enabling the use of the holding register. 0 the holding register is disabled from satisfying read requests. 1 the holding register is enabled to satisfy read requests on hits. table 30-62. pfcr1 field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 878 freescale semiconductor location at address 0x203e00 of the sh adow region in the flash memory array must be programmed using the normal sequence of operations . the reset value shown in table 30-44 reflects an erased or unprogrammed value from the shadow region. offset 0x024 access: read/write 0123456789101112131415 r 0 0 0 0 0 0 0 0 0 0 0 0 0 m2pfd 0 m0pfd w reset defined by nvpfapr at cflash test sector address 0x203e00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 m2ap 0 0 m0ap w reset defined by nvpfapr at cflash test sector address 0x203e00 figure 30-44. pflash access protection register (pfapr) table 30-63. pfapr field descriptions field description m2pfd edma master 2 prefetch disable this field controls whether prefetching may be triggered based on the master number of the requesting ahb master. this field is further qualified by the pfcr0[b0_px_dpfe, b0_px_ipfe, b x _p y _bfe] bits. for master numbering, see table 19-1 . 0 prefetching may be triggered by this master 1 no prefetching may be triggered by this master m0pfd e200z0 core master 0 prefetch disable this field controls whether prefetching may be triggered based on the master number of the requesting ahb master. this field is further qualified by the pfcr0[b0_px_dpfe, b0_px_ipfe, b x _p y _bfe] bits. for master numbering, see table 19-1 . 0 prefetching may be triggered by this master 1 no prefetching may be triggered by this master
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 879 30.7.2.2.3.1 nonvolatile platform flash ac cess protection regi ster (nvpfapr) the nvpfapr register has a related nonvolatile pfapr located in the shadow sector that contains the default reset value for pfapr. duri ng the reset phase of the flash memo ry module, the nvpfapr register content is read and loaded into the pfapr. the nvpfapr register is a 64-bit register, of whic h the 32 most significant bits 63:32 are ?don?t care? and are used to manage ecc codes. m2ap edma master 2 access protection these fields control whether read and write access es to the flash memory are allowed based on the master number of the initiating module. for master numbering, see ta b l e 1 9 - 1 . 00 no accesses may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master m0ap e200z0 core master 0 access protection these fields control whether read and write access es to the flash memory are allowed based on the master number of the initiating module. for master numbering, see ta b l e 1 9 - 1 . 00 no accesses may be performed by this master 01 only read accesses may be performed by this master 10 only write accesses may be performed by this master 11 both read and write accesses may be performed by this master offset: 0x203e00 access: read/write 0123456789101112131415 r 1 1 1 1 1 1 1 1 1 1 1 1 1 m2pfd 1 m0pfd w reset 1111111111111111 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 0 0 0 0 0 0 0 0 0 m2ap 0 0 m0ap w reset 1111111111111111 figure 30-45. nonvolatile platform flash access protection register (nvpfapr) table 30-63. pfapr field descriptions (continued) field description
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 880 freescale semiconductor 30.8 functional description the platform flash memory controller interfaces between the ahb system bus and the flash memory arrays. the platform flash memory controller generates read and write enables, the flash memory array address, write size, and write data as inputs to the flash me mory array. the platform flash memory controller captures read data from the flash memory array interface and drives it onto the ahb. as many as four pages of data (128-bit widt h) from bank0 are buffered by the platform flash memory controller. lines may be prefetched in advance of being requested by the ahb interface, allowing single-cycle (zero ahb wait-states) read data responses on buffer hits. several prefetch control algorithms are available for co ntrolling page read buffer fills. prefetch triggering may be restricted to instruction accesses only, da ta accesses only, or may be unrestricted. prefetch triggering may also be contro lled on a per-master basis. buffers may also be selectively enabled or disabled for allocation by instruction and data prefetch. see section 30.7.2.2.1, platform flash conf iguration register 0 (pfcr0) , and section 30.7.2.2.2, platform flash configuration register 1 (pfcr1) . access protections may be applied on a per-master basis for both reads a nd writes to support security and privilege mechanisms. see section 30.7.2.2.3, platform flash access protection register (pfapr) . throughout this discussion, bkn_ is used as a prefix to refer to two signals, e ach for each bank: bk0_ and bk1_. also, the nomenclature b x _p y _regname is used to reference a program-visible register field associated with bank ?x? and port ?y?. 30.8.1 access protections the platform flash memory controller provides programmable configurable access protections for both read and write cycles from mast ers via the pflash access protecti on register (pfapr). it allows restriction of read and write requ ests on a per-master basis. this functionality is described in section 30.7.2.2.3, platform flash acce ss protection register (pfapr) . detection of a protection violation results in an error response from the plat form flash memory controller on the ahb transfer. 30.8.2 read cycles ? buffer miss read cycles from the flash memory array are initia ted by the platform flash memory controller. the platform flash memory controller then waits for the programmed num ber of read wait-states before table 30-64. nvpfapr field descriptions field description m2pfd see table 30-63 . m0pfd see table 30-63 . m2ap see table 30-63 . m0ap see table 30-63 .
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 881 sampling the read data from the flash memory array. this data is normally stor ed in the least-recently updated page read buffer for bank0 in parallel with the requested data being forwarded to the ahb. for bank1, the data is captured in the pa ge-wide temporary holding register as the request ed data is forwarded to the ahb bus. if the flash memory access wa s the direct result of an ahb transaction, the page buffer is marked as most recently used as it is being loaded. if the flash memo ry access was the result of a speculative prefetch to the next sequential line, it is first loaded into the least recently used buffer. the status of this buffer is not changed to most recently used until a subsequent buffer hit occurs. 30.8.3 read cycles ? buffer hit single cycle read responses to the ahb are possible with th e platform flash memory controller when the requested read access was previously loaded into one of the bank0 page buffers. in these buffer hit cases, read data is returned to the ahb data phase with a zero wait-state response. likewise, the bank1 logic includes a single 128-bit temporary holding regist er and sequential accesses that ?hit? in this register are also serv iced with a zero wait-state response. 30.8.4 write cycles write cycles are initiated by the plat form flash memory controller. the platform flash memory controller then waits for the appropriate nu mber of write wait-states before terminating the write operation. 30.8.5 error termination the first case that can cause an error response to the ahb is when an access is attempted by an ahb master whose corresponding read a ccess control or write access cont rol settings do not allow the access, thus causing a protection viol ation. in this case, the platform flash memory controller does not initiate a flash memory array access. the second case that can cause an error response to th e ahb is when an access is performed to the flash memory array and is ter minated with a flash memo ry error response. see section 30.8.7, flash error response operation . this may occur for either a read or a write operation. a third case involves an attempted read access wh ile the flash memory array is busy doing a write (program) or erase operation if the appropriate read-while-write cont rol field is programmed for this response. the 3-bit read-wh ile-write control allows fo r immediate termination of an attempted read, or various stall-while-write/er ase operations are occurring. 30.8.6 access pipelining the platform flash memory controller does not supp ort access pipelining since this capability is not supported by the flash memory array. as a result, th e apc (address pipelining control) field must be the same value as the rwsc (r ead wait-state control).
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 882 freescale semiconductor 30.8.7 flash error response operation the flash memory array may signal an error response to terminate a requested access with an error. this may occur due to an uncorrectable ecc error, or because of improper sequenc ing during program/erase operations. when an error response is received, the pl atform flash memory controller does not update or validate a bank0 page read buffer nor the bank1 tem porary holding register. an error response may be signaled on read or write operations. for additional information on the sy stem registers that capture the faulting address, attributes, data, and ecc information, see chapter 34, error correction status module (ecsm) . 30.8.8 bank0 page read buff ers and prefetch operation the logic associated with bank0 of the platform flash memory controlle r contains four 128-bit page read buffers that are used to hold instru ctions and data read from the flas h memory array. each buffer operates independently, and is filled using a single array access. the buffers are used for both prefetch and normal demand fetches. for the general case, a page buffer is written at the completion of an error-free flash memory access and the valid bit asserted. subsequent flash memory acce sses that hit the buffer, that is, the current access address matches the address stored in the buffer, can be serviced in 0 ahb wait-states as the stored read data is routed from the given page buf fer back to the requesting bus master. as noted in section 30.8.7, flash error response operation , a page buffer is not marked as valid if the flash memory array access terminated with a ny type of transfer error. however, the result is that flash memory array accesses that are tagged with a single-bit correctable ecc event are loaded into the page buffer and validated. for additional comme nts on this topic, see section 30.8.8.4, buffer invalidation . prefetch triggering is controllable on a per-master and access-type basi s. bus masters may be enabled or disabled from triggering prefetches , and triggering may be further re stricted based on whether a read access is for instruction or data. a read access to the platform flas h memory controller may trigger a prefetch to the next sequential page of array data on the first idle cycl e following the request. the access address is incremented to the next-higher 16-byte boundary, and a flash memory array prefetch is initiated if the data is not already re sident in a page buffer. prefetched data is always loaded into the least recently used buffer. buffers may be in one of six states, listed here in order of priority: 1. invalid ? the buffer contains no valid data. 2. used ? the buffer contains valid data that has been provided to satisfy an ahb burst type read. 3. valid ? the buffer contains valid data that has been pr ovided to satisfy an ahb single type read. 4. prefetched ? the buffer contains valid data that has been prefetch ed to satisfy a potential future ahb access. 5. busy ahb ? the buffer is currently being used to satisfy an ahb burst read. 6. busy fill ? the buffer has been allocated to recei ve data from the flash memory array, and the array access is still in progress.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 883 selection of a buffer to be loaded on a miss is based on the following replacement algorithm: 1. first, the buffers are examined to determine if there are any invalid buffers. if there are multiple invalid buffers, the one to be used is selected using a simple num eric priority, where buffer 0 is selected first, then buffer 1, etc. 2. if there are no invalid buffers, the least r ecently used buffer is selected for replacement. once the candidate page buffer has been selected, the flash memory array is accessed and r ead data loaded into the buffer. if the buffer load was in response to a miss, the just-loaded buf fer is immediately marked as most recently used. if the buffer load was in res ponse to a speculative fetch to the next-sequential line address after a buffer hit, the recently used status is not changed. rather, it is marked as most recently used only after a subsequent buffer hit. this policy maximizes performance ba sed on reference patterns of flas h memory accesses and allows for prefetched data to remain valid wh en non-prefetch enabled bus master s are granted flash memory access. several algorithms are available for prefetch contro l that trade off performanc e versus power. they are defined by the b x _p y _pflm (prefetch limit) register field. more aggressive prefetch ing increases power slightly due to the number of wa sted (discarded) prefetches, but may increase performance by lowering average read latency. in order for prefetching to occur, a number of control bits must be enabled. specifically, the global buffer enable (pfcr n [b x _p y _bfe]) must be set, th e prefetch limit (pfcr n [b x _p y _pflm]) must be non-zero, either instruction prefetching (pfcr n [b x _p y _ipfe]) or data prefetching (pfcr n [b x _p y _dpfe]) enabled, and master access must be enabled (pfapr[mxpfd]). see section 30.7.2.2, register description , for a description of these control fields. 30.8.8.1 instruction/data prefetch triggering prefetch triggering may be enabled for instruction reads via the b x _p y _ipfe control field, while prefetching for data reads is enabled via the b x _p y _dpfe control field. additionally, the b x _p y _pflim field must be set to enable prefetching. pr efetches are never triggered by write cycles. 30.8.8.2 per-master prefetch triggering prefetch triggering may be also controlled for individual bus masters. see section 30.7.2.2.3, platform flash access protection register (pfapr) , for details on these controls. 30.8.8.3 buffer allocation allocation of the line read buffers is c ontrolled via page buf fer configuration (b x _p y _bcfg) field. this field defines the operating or ganization of the four page buffers. the buffers can be orga nized as a pool of available resources (wit h all four buffers in the pool ) or with a fixed partition between buffers allocated to instruction or data accesses. for the fixed partition, two configurations are suppor ted. in one configuration, buffers 0 and 1 are allocated for instruction fetches and buffers 2 and 3 for data accesses. in the second configuration, buffers 0, 1, and 2 are allocated for in struction fetches and buffer 3 reserved for data accesses.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 884 freescale semiconductor 30.8.8.4 buffer invalidation the page read buffers may be invalida ted under hardware or software control. at the beginning of all pr ogram/erase operations, the flash memory array will invalidate the page read buffers. buffer invalidation occurs at the next ahb non-sequential ac cess boundary, but does not affect a burst from a page read buf fer that is in progress. software may invalidate th e buffers by clearing the b x _p y _bfe bit, which also disables the buffers. software may then re-assert the b x _p y _bfe bit to its previous state, and the buffers will have been invalidated. one special case needing software in validation relates to page buffer hi ts on flash memory data that was tagged with a single-bit ecc event on the original array access. recall that the page buffer structure includes an status bit signaling the array access dete cted and corrected a single-bit ecc error. on all subsequent buffer hits to this type of page data, a single-bit ecc event is si gnaled by the platform flash memory controller. depending on the specific hardware configuration, this repor ting of a single-bit ecc event may generate an ecc alert interrupt. in order to prevent repeated ecc alert interrupts, the page buffers need to be invalidated by software after the first notification of the single-bit ecc event. finally, the buffers are invali dated by hardware on any non-sequent ial access with a non-zero value on haddr[28:24] to support wait-state emulation. 30.8.9 bank1 temporary holding register recall the bank1 logic within the platform flash memory controll er includes a single 128- bit data register, used for capturing read data. since this bank does not support prefetching, the read data for the referenced address is bypassed directly back to the ahb data bus . the page is also loaded into the temporary data register and subsequent accesses to this page can hit from this register, if it is enabled (b1_p0_bfe). for the general case, a temporary hol ding register is written at the co mpletion of an error-free flash memory access and the valid bit asserted. subsequent fl ash memory accesses that hit the buffer, that is, the current access address matches the a ddress stored in the temporary holdi ng register, can be serviced in 0 ahb wait-states as the stored read data is routed fr om the temporary register back to the requesting bus master. the contents of the holding regist er are invalidated by the flash memo ry array at the beginning of all program/erase operations and on any non-sequential access with a non-zero value on haddr[28:24] (to support wait-state emulation) in th e same manner as the bank0 page buf fers. additionally, the b1_p0_bfe register bit can be cleared by software to i nvalidate the contents of the holding register. as noted in section 30.8.7, flash error response operation , the temporary holding register is not marked as valid if the flash memory array access terminated with any type of transfer erro r. however, the result is that flash memory array accesses that are tagged with a single-bit correctable ecc event are loaded into the temporary holding register and validated. accordingly, one special case needing software invalidation relates to holding register hits on flash memory da ta that was tagged with a single-bit ecc event. depending on the specific hardware configuration, the reporting of a single-bit ecc even t may generate an ecc alert interrupt. in order to prevent repeated ecc alert interrupts, the page buffers need to be invalidated by software after the first notification of the single-bit ecc event.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 885 the bank1 temporary holding register effect ively operates like a single page buffer. 30.8.10 read-while-write functionality the platform flash memory controller supports vari ous programmable responses for read accesses while the flash memory is busy performing a write (program) or er ase operation. for all situ ations, the platform flash memory controller uses the st ate of the flash memory array?s m cr[done] output to determine if it is busy performing some type of high voltage oper ation, namely, if mcr[done] = 0, the array is busy. specifically, two 3-bit read-while-write (bk n _rwwc) control register fields define the platform flash memory controller?s response to these types of access sequences. the follow ing unique responses are defined by the bk n _rwwc setting: one that imme diately reports an error on an attempted read and four settings that support various stall- while-write capabilities. consider the details of these settings. ?bk n _rwwc = 0b111 this defines the basic stall-while- write capability and re presents the default reset setting. for this mode, the platform flash memory c ontroller module simply stalls a ny read reference until the flash memory has completed its program/ erase operation. if a read access arrives while the array is busy or if mcr[done] goes low while a read is still in progress, the ahb data phase is stalled and the read access address is saved. once the array has completed it s program/erase operation, the platform flash memory controller uses the save d address and attribute information to create a pseudo address phase cycle to retr y the read reference and sends th e registered information to the array. once the retried address pha se is complete, the read is pr ocessed normally and once the data is valid, it is forwarded to the ahb bus to terminate the system bus transfer. ?bk n _rwwc = 0b110 this setting is similar to the basic st all-while-write capa bility provided when bk n _rwwc = 0b111 with the added ability to generate a notification interrupt if a read arrives while the array is busy with a program/erase ope ration. there are two notification interrupts, one for each bank (see chapter 18, interrupt controller (intc) ). ?bk n _rwwc = 0b101 again, this setting provides the basic stall-while-write capability with the added ability to abort any program/erase operation if a read acc ess is initiated. for this setti ng, the read request is captured and retried as described for the ba sic stall-while-write, plus the program/erase opera tion is aborted by the platform flash memory controller. for this setting, no notification interrupts are generated. ?bk n _rwwc = 0b100 this setting provides the basic stall-while-wr ite capability with the ability to abort any program/erase operation if a read access is initiated plus the gene ration of an abort notification interrupt. for this setting, the read request is captured and retried as described for the basic stall-while-write, the program/erase operation is aborted by the platform fl ash memory controller and an abort notification interrupt generated. ther e are two abort notifica tion interrupts, one for each bank. as detailed above, a total of four interrupt requests are associated with the stall-while-write functionality. these interrupt requests are captured as part of ecsm ?s interrupt register and logically summed together to form a single request to the interrupt controller.
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 886 freescale semiconductor 30.8.11 wait-state emulation emulation of other memory array ti mings are supported by the platform flash memory controller on read cycles to the flash memory. this functionality may be useful to maintain the access timing for blocks of memory that were used to overlay flash memory bl ocks for the purpose of system calibration or tuning during code development. the platform flash memory controller inserts a dditional wait-states according to the values of haddr[28:24]. when these inputs are non-zero, additiona l cycles are added to ahb read cycles. write cycles are not affected. in addition, no page read buffe r prefetches are initiated, and buffer hits are ignored. table 30-66 and table 30-67 show the relationship of haddr[28:24] to the number of additional primary wait-states. these wait-states are appl ied to the initial access of a burst fetch or to single-beat read accesses on the ahb system bus. note that the wait-state specification consists of two components: haddr[28: 26] and haddr[25:24], and effectively extends the flash memory read by (8 haddr[25:24] + haddr[28:26]) cycles. table 30-67 shows the relationship of haddr[25:24] to th e number of additional wa it-states. these are applied in addition to those specifi ed by haddr[28:26], and thus extend th e total wait-state specification capability. table 30-65. platform flash memory controller stall-while-write interrupts mir[n] interrupt description ecsm.mir[0] platform flash memory bank0 abort notification, mir[fb0ai] ecsm.mir[1] platform flash memory bank0 stall notification, mir[fb0si] ecsm.mir[2] platform flash memory bank1 abort notification, mir[fb1ai] ecsm.mir[3] platform flash memory bank1 stall notification, mir[fb1s1] table 30-66. additional wait-state encoding memory address haddr[28:26] additional wait-states 000 0 001 1 010 2 011 3 100 4 101 5 110 6 111 7
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 887 table 30-67. extended additional wait-state encoding memory address haddr[25:24] additional wait-states (added to those specified by haddr[28:26]) 00 0 01 8 10 16 11 24
chapter 30 flash memory MPC5606BK microcontroller reference manual, rev. 2 888 freescale semiconductor this page is intent ionally left blank.
chapter 31 static ram (sram) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 889 chapter 31 static ram (sram) 31.1 introduction this device has as much as 80 kb of general-purpose static ram (sram). the sram provides the following features: ? sram can be read/writte n from any bus master ? byte, halfword, and word addressable ? ecc (error correction code) protected with single-bit correction and double-bit detection 31.2 low power configuration in order to reduce leakage a portion of the sram can be switched off/unpow ered during standby mode. 31.3 register memory map the l2sram occupies 80 kb of memory st arting at the base address as shown in table 31-3 . the internal sram has no register s. registers for the sram ecc are located in the ecsm [see chapter 34, error correction status module (ecsm) , for more information]. table 31-1. sram behavior in chip modes sram ? 96 kb address mc_pcu control register run modes (drun, run0..3) low-power modes halt stop standby 8 kb 0x4000_0000 ? 0x4000_1fff pconf0[ ] always on always on always on always on 24 kb 0x4000_2000 ? 0x4000_bfff pconf2[ ] on/off on/off on/off on/off 64 kb 0x4000_c000 ? 0x4001_7fff pconf3[ ] on/off on/off on/off always off table 31-2. low power configuration mode configuration run, test, safe, and stop the entire sram is powered and operational. standby either 8 kb or 32 kb of the sram remains powered. this option is software-selectable. table 31-3. sram memory map address register name register description size 0x4000_0000 (base) ?sra80kb
chapter 31 static ram (sram) MPC5606BK microcontroller reference manual, rev. 2 890 freescale semiconductor 31.4 sram ecc mechanism the sram ecc detects the following condi tions and produces the following results: ? detects and corrects all 1-bit errors ? detects and flags all 2-bit erro rs as non-correctable errors ? detects 39-bit reads (32-bit data bus plus the 7-bit ecc) that return all zeros or all ones, asserts an error indicator on the bus cycle, and sets the error flag sram does not detect all er rors greater than 2 bits. internal sram write operations are pe rformed on the following byte boundaries: ? 1 byte (0:7 bits) ? 2 bytes (0:15 bits) ? 4 bytes or 1 word (0:31 bits) if the entire 32 data bits are written to sram, no re ad operation is performed and the ecc is calculated across the 32-bit data bus. the 8-bit ecc is appe nded to the data segment and written to sram. if the write operation is less than the entire 32-bit da ta width (1 or 2-byte segm ent), the following occurs: 1. the ecc mechanism checks the entire 32-bit data bus for errors, detecting and either correcting or flagging errors. 2. the write data bytes (1 or 2-byte segment) are merged with the corrected 32 bits on the data bus. 3. the ecc is then calculated on the resulti ng 32 bits formed in the previous step. 4. the 7-bit ecc result is appended to the 32 bits from the data bus, and th e 39-bit value is then written to sram. 31.4.1 access timing the system bus is a two-stage pipe lined bus, which makes the timing of any access dependent on the access during the previous clock cycle. table 31-4 lists the various combinations of read and write operations to sram and the number of wait states used for the each operation. the table columns contain the following information: ? current operation ? lists the type of sram operation currently executing ? previous operation ? lists the va lid types of sram operations that can precede the current sram operation (valid operati on during the preceding clock) ? wait states ? lists the number of wait states (bus clocks) the operation requires, which depends on the combination of the current and previous operation
chapter 31 static ram (sram) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 891 31.4.2 reset effects on sram accesses asynchronous reset will possibly corrupt sram if it asserts during a read or write operation to sram. the completion of that access depends on the cycle at which the reset occurs . data read from or written to sram before the reset event occurred is retained, and no other address locations are accessed or changed. in case of no access ongoing when reset oc curs, the sram corruption does not happen. instead, synchronous reset (sw reset) should be used in controlled f unction (without sram accesses) in case an initializat ion procedure without sram initialization is needed. 31.5 functional description ecc checks are performed during the read portion of an sram ecc read/wri te (r/w) operation, and ecc calculations are performed dur ing the write portion of a r/w ope ration. because the ecc bits can contain random data after the devi ce is powered on, the sram must be initialized by executing 32-bit write operations prior to any read accesses. this is also true for implicit read acc esses caused by any write accesses of less than 32 bits as discussed in section 31.4, sram ecc mechanism . 31.6 initialization and application information to use the sram, the ecc must check all bits that require initialization after power on. all writes must specify an even number of regist ers performed on 32-bit word-aligned boundaries. if the write is not the table 31-4. number of wait states required for sram operations operation type current operation previous operation number of wait states required read read idle 1 pipelined read 8, 16 or 32-bit write 0 (read from the same address) 1 (read from a different address) pipelined read read 0 write 8 or 16-bit write idle 1 read pipelined 8 or 16-bit write 2 32-bit write 8 or 16-bit write 0 (write to the same address) pipelined 8, 16 or 32-bit write 8, 16 or 32-bit write 0 32-bit write idle 0 32-bit write read
chapter 31 static ram (sram) MPC5606BK microcontroller reference manual, rev. 2 892 freescale semiconductor entire 32 bits (8 or 16 bits), a read / modify / writ e operation is generated that checks the ecc value upon the read. see section 31.4, sram ecc mechanism .
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 893 ??? integrity ???
MPC5606BK microcontroller reference manual, rev. 2 894 freescale semiconductor this page is intent ionally left blank.
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 895 chapter 32 register protection 32.1 introduction the register protection m odule offers a mechanism to protect de fined memory-mapped address locations in a module under protectio n from being written. the address locations that can be protected are module-specific. the protection module is located be tween the module under protection and the peripheral bridge. this is shown in figure 32-1 . figure 32-1. register protection block diagram please see the ?registers under protection? appendix for the list of protected registers. 32.2 features the register protection include s these distinctive features: ? restrict write accesses for the module unde r protection to supervisor mode only ? lock registers for first 6 kb of memory-mapped address space ? address mirror automatically sets corresponding lock bit ? once configured lock bits can be protected from changes pbridge supervisor access / lock registers module under protection protection module write data address / access size uaa hlb gcr access allowed? peripheral enable other control signals peripheral enable
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 896 freescale semiconductor 32.3 modes of operation the register protection module is operable when the modul e under protectio n is operable. 32.4 external signal description there are no external signals. 32.5 memory map and register description this section provides a detailed de scription of the memory map of a module usi ng the register protection. the original 16 kb module memory space is divided into five areas as shown in figure 32-2 . figure 32-2. register protection memory diagram area 1 spans 6 kb and holds the normal functional modul e registers and is transparent for all read/write operations. area 2 spans 2 kb starting at address 0x1800. it is a reserved area that cannot be accessed. area 3 spans 6 kb, starting at address 0x2000 and is a mirror of area 1. a read/write access to a 0x2000+x address will reads/writes the regi ster at address x. as a side ef fect, a write acces s to address 0x2000+x sets the optional soft lock bits for address x in the sa me cycle as the register at address x is written. not all registers in area 1 need to have protection defined by asso ciated soft lock bits. for unprotected registers module register space base + 0x0000 6kb 2 kb reserved mirror module register space 6kb 1.5 kb lock bits with user defined base + 0x1800 base + 0x2000 base + 0x3800 soft locking function 512 b configuration base + 0x3e00 base + 0x3fff area 1 area 2 area 3 area 4 area 5
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 897 at address y, accesses to address 0x2000+y will be iden tical to accesses at address y. only for registers implemented in area 1 and define d as protectable soft lock bi ts are available in area 4. area 4 is 1.5 kb and holds th e soft lock bits, one bit pe r byte in area 1. the four so ft lock bits associated with a module register word are a rranged at byte boundaries in the memory map. the soft lo ck bit registers can be directly writt en using a bit mask. area 5 is 512 byte and holds the confi guration bits of the protection mode . there is one configuration hard lock bit per module that prevents al l further modifications to the soft lock bits and can only be cleared by a system reset once set. the othe r bits, if set, will allow us er access to the protected module. if any locked byte is accessed with a write transaction, a transf er error will be issued to the system and the write transaction will not be ex ecuted. this is true even if not all accessed bytes are locked. accessing unimplemented 32-bit re gisters in areas 4 and 5 re sults in a transfer error. 32.5.1 memory map table 32-1 gives an overview on the register protection registers implemented. note reserved registers in area #2 will be handled according to the protected ip (module under protection). table 32-1. register protection memory map address offset register location 0x0000 module register 0 (mr0) on page 898 0x0001 module register 1 (mr1) on page 898 0x0002 module register 2 (mr2) on page 898 0x0003?0x17ff module register 3 (mr3) - module register 6143 (mr6143) on page 898 0x1800?0x1fff reserved ? 0x2000 module register 0 (mr0) + set soft lock bit 0 (lmr0) on page 898 0x2001 module register 1 (mr1) + set soft lock bit 1 (lmr1) on page 898 0x2002?0x37ff module register 2 (mr2) + set soft lock bit 2 (lmr2) ? module register 6143 (mr6143) + set soft lock bit 6143 (lmr6143) on page 898 0x3800 soft lock bit register 0 (slbr0): soft lock bits 0-3 on page 898 0x3801 soft lock bit register 1 (slbr1): soft lock bits 4-7 on page 898 0x3802?0x3dff soft lock bit register 2 (slbr2): soft lock bits 8-11 ? soft lock bit register 1535 (slb r1535): soft lock bits 6140-6143 on page 898 0x3e00?0x3ffb reserved ? 0x3ffc global configuration register (gcr) on page 899
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 898 freescale semiconductor 32.5.2 register description 32.5.2.1 module registers (mr0-6143) this is the lower 6 kb module memory space that holds all the functiona l registers of the module that is protected by the regi ster protection module. 32.5.2.2 module register and se t soft lock bit (lmr0-6143) this is memory area #3 that provides mirrored acce ss to the mr0-6143 registers with the side effect of setting soft lock bits in case of a write access to a mr that is defined as protectable by the locking mechanism. each mr is protectable by one associated bit in a slbr n .slb m , according to the mapping described in table 32-2 . 32.5.2.3 soft lock bit register (slbr0-1535) these registers hold the soft lock bits fo r the protected registers in memory area #1. figure 32-3 gives some examples how slbr n .slb and mr n go together. address 0x3800-0x3dff access: read always supervisor write 01234567 r0000 slb0 slb1 slb2 slb3 wwe0 we1 we2 we3 reset00000000 figure 32-3. soft lock bit register (slbr n ) table 32-2. slbr n field descriptions field description we0 we1 we2 we3 write enable bits for soft lock bits (slb): we0 enables writing to slb0 we1 enables writing to slb1 we2 enables writing to slb2 we3 enables writing to slb3 1 value is written to slb 0 slb is not modified slb0 slb1 slb2 slb3 soft lock bits for one mr n register: slb0 can block accesses to mr[ n 4 + 0] slb1 can block accesses to mr[ n 4 + 1] slb2 can block accesses to mr[ n 4 + 2] slb3 can block accesses to mr[ n 4 + 3] 1 associated mr n byte is locked against write accesses 0 associated mr n byte is unprotected and writable
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 899 32.5.2.4 global configuration register (gcr) this register is used to make global conf igurations related to register protection. table 32-3. soft lock bits vs. protected address soft lock bit protected address slbr0.slb0 mr0 slbr0.slb1 mr1 slbr0.slb2 mr2 slbr0.slb3 mr3 slbr1.slb0 mr4 slbr1.slb1 mr5 slbr1.slb2 mr6 slbr1.slb3 mr7 slbr2.slb0 mr8 ... ... address 0x3ffc access: read always supervisor write 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 r hlb0000000 uaa0000000 w reset 0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000000000 0 00 w reset 0000000000000 0 00 figure 32-4. global config uration register (gcr)
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 900 freescale semiconductor note the gcr.uaa bit has no effect on the allowed access modes for the registers in the register protection module. 32.6 functional description 32.6.1 general this module provides a generic regist er (address) write-prot ection mechanism. the protection size can be: ? 32-bit (address == multiples of 4) ? 16-bit (address == multiples of 2) ? 8-bit (address == multiples of 1) ? unprotected (address == multiples of 1) which addresses are protected and the protection size depend on the soc and/or module. therefore this section can just give examples fo r various protecti on configurations. for all addresses that are protected there are slbr n .slb m bits that specify whether the address is locked. when an address is locked it can be read but not written in any mode (supervisor/nor mal). if an address is unprotected the corresponding slbr n .slb m bit is always 0b0 no matter what software is writing to. 32.6.2 change lock settings to change the setting whether an address is locked or unlocked the corresponding slbr n .slb m bit needs to be changed. this can be done using the following methods: ? modify the slbr n .slb m directly by writing to area #4 ? set the slbr n .slb m bit(s) by writing to the mirror module space (area #3) both methods are explained in the following sections. table 32-4. gcr field descriptions field description hlb hard lock bit. this register cannot be cleared once it is set by software. it can only be cleared by a system reset. 1 all slb bits are write prot ected and cannot be modified 0 all slb bits are accessible and can be modified. uaa user access allowed. 1 the registers in the module under protection can be accessed in the mode defined for the module registers without any additional restrictions. 0 the registers in the module under protection can only be written in supervisor mode. all write accesses in non-supervisor mode are not execut ed and a transfer error is issued. this access restriction is in addition to any access restrictions imposed by the protected ip module.
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 901 32.6.2.1 change lock settings directly via area #4 memory area #4 contains the lock bits. they ca n be modified by writing to them. each slbr n .slb m bit has a mask bit slbr n .we m, which protects it from being modified. this masking makes clear-modify-write op erations unnecessary. figure 32-5 shows two modification examples . in the left example there is a write access to the slbr n register specifying a mask value th at allows modification of all slbr n .slb m bits. the example on the right specifies a mask that only a llows modification of the bits slbr n .slb[3:1]. figure 32-5. change lock settings directly via area #4 figure 32-5 shows four registers that ca n be protected 8-bit wise. in figure 32-6 registers with 16-bit protection and in figure 32-7 registers with 32-bi t protection are shown: figure 32-6. change lock settings for 16-bit protected addresses on the right side of figure 32-6 it is shown that the data written to slbr n .slb[0] is automatically written to slbr n .slb[1] also. this is done as the address reflected by slbr n .slb[0] is protected 16-bit wise. note that in this case the write enable slbr n .we[0] must be set while slbr n .we[1] does not matter. as the enable bits slbr n .we[3:2] are cleared the lock bits slbr n .slb[3:2] remain unchanged. in the example on the left side of figure 32-6 the data written to slbr n .slb[0] is mirrored to slbr n .slb[1] and the data written to slbr n .slb[2] is mirrored to slbr n .slb[3] as for both registers the write enables are set. 1 slb3 slb2 slb1 slb0 slbr n .we[3:0] slbr n .slb[3:0] slb3 slb2 slb1 slb0 slbr n .slb[3:0] change allowed to slb3 write data to slb2 to slb1 to slb0 1 1 1 1slbr n .we[3:0] to slb3 write data to slb2 to slb1 to slb0 1 1 0 change allowed slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 x1x slb0 slb1 slb2 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 x00
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 902 freescale semiconductor in figure 32-7 a 32-bit wise protected re gister is shown. when slbr n .we[0] is set the data written to slbr n .slb[0] is automatically written to slbr n .slb[3:1] also. otherwise slbr n .slb[3:0] remains unchanged. figure 32-7. change lock settings for 32-bit protected addresses in figure 32-8 an example is shown that has a mixed protection size configuration: figure 32-8. change lock se ttings for mixed protection the data written to slbr n .slb[0] is mirrored to slbr n .slb[1] as the corresponding register is 16-bit protected. the data written to slbr n .slb[2] is blocked as the corresponding regist er is unprotected. the data written to slbr n .slb[3] is written to slbr n .slb[3]. 32.6.2.2 enable lock ing via mirror m odule space (area #3) it is possible to enable locking for a register after writing to it. to do so the mirrored module address space must be used. figure 32-9 shows one example: 1 slb0 slb1 slb2 slb3 slbr n .we[3:0] slbr.slb[3:0] update lock bits to slb0 write data to slb1 to slb2 to slb3 xxx slb0 slb1 0 slb3 slbr update lock bits 1slbr n .we[3:0] to slb0 write data to slb1 to slb2 to slb3 xx1
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 903 figure 32-9. enable locking via mirror module space (area #3) when writing to address 0x0008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits rema in unchanged (left part of figure 32-6 ). when writing to address 0x2008 the registers mr9 and mr8 in the protected module are updated. the corresponding lock bits slbr2.slb[1 :0] are set while the lock bits slbr2.slb[3:2] remain unchanged (right part of figure 32-6 ). figure 32-10 shows an example where some addres ses are protected and some are not: figure 32-10. enable locking for protected and unprotected addresses in the example in figure 32-10 addresses 0x0c and 0x0d are unprot ected. therefore their corresponding lock bits slbr3.slb[1:0] are always 0b0 (shown in bold). when doing a 32-bit write access to address 0x200c only lock bits slbr3.slb[3:2] are set while bits slbr3.slb[1:0] stay 0b0. note lock bits can only be set via writes to the mirror module space. reads from the mirror module space will not change the lock bits. 32.6.2.3 write protection for locking bits changing the locking bits through any of the procedures mentioned in section 32.6.2.1, change lock settings directly via area #4 and section 32.6.2.2, enable locking via mirror module space (area #3) is only possible as long as the bit gcr.hlb is cleared. once this bit is set, the locking bits can no longer be modified until there is a system reset. slbr 2 we[3:0] 00000000 slb[3:0] 16-bit write to address 0x0008 no change write to mr[9:8] slbr 2 we[3:0] 00001100 slb[3:0] 16-bit write to address 0x2008 set lock bits write to mr[9:8] slbr 3 we[3:0] 00000000 slb[3:0] before write access slbr 3 we[3:0] 00000011 slb[3:0] 32-bit write to address 0x200c set lock bits write to mr[15:12] after write access
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 904 freescale semiconductor 32.6.3 access errors the protection module generates tran sfer errors under several circumst ances. for the area definition refer to figure 32-2 . 1. if accessing area #1 or area #3, the protection module transfers any access error from the underlying module under protection. 2. if user mode is not allowed, user write attempts to all ar eas will assert a transfer error and the writes will be blocked. 3. access attempts to the reserved area #2 cause a transfer error to be asserted. 4. access attempts to unimplemented 32-bit registers in area #4 or area #5 cause a transfer error to be asserted. 5. attempted writes to a register in area #1 or area #3 with soft lock bit set for any of the affected bytes causes a transfer error to be asserted a nd the write is blocked. th e complete write operation to non-protected bytes in this word is ignored. 6. if writing to a soft lock register in area #4 with th e hard lock bit being set a transfer error is asserted. 7. any write operation in any access mode to ar ea #3 while gcr.hlb is set result in a error. 32.7 reset the reset state of each individua l bit is shown within the regi ster description section (see section 32.5.2, register description ). in summary, after reset, locking for all mr n registers is disabled. the registers can be accessed in supervisor mode only. 32.8 protected registers for MPC5606BK the register protection m odule protects the registers shown in table 32-5 . table 32-5. protected registers module register protected size (bits) module base address register offset protected bits code flash memory 0, 4 registers to protect code flash 0 mcr 32 c3f88000 000 bits[0:31] code flash 0 pfcr0 32 c3f88000 01c bits[0:31] code flash 0 pfcr1 32 c3f88000 020 bits[0:31] code flash 0 pfapr 32 c3f88000 024 bits[0:31] data flash memory, 1 register to protect data flash mcr 32 c3f8c000 000 bits[0:31] siu lite, 64 registers to protect siul irer 32 c3f90000 018 bits[0:31] siul ireer 32 c3f90000 028 bits[0:31]
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 905 siul ifeer 32 c3f90000 02c bits[0:31] siul ifer 32 c3f90000 030 bits[0:31] siul pcr0 16 c3f90000 040 bits[0:15] siul pcr1 16 c3f90000 042 bits[0:15] siul pcr2 16 c3f90000 044 bits[0:15] siul pcr3 16 c3f90000 046 bits[0:15] siul pcr4 16 c3f90000 048 bits[0:15] siul pcr5 16 c3f90000 04a bits[0:15] siul pcr6 16 c3f90000 04c bits[0:15] siul pcr7 16 c3f90000 04e bits[0:15] siul pcr8 16 c3f90000 050 bits[0:15] siul pcr9 16 c3f90000 052 bits[0:15] siul pcr10 16 c3f90000 054 bits[0:15] siul pcr11 16 c3f90000 056 bits[0:15] siul pcr12 16 c3f90000 058 bits[0:15] siul pcr13 16 c3f90000 05a bits[0:15] siul pcr14 16 c3f90000 05c bits[0:15] siul pcr15 16 c3f90000 05e bits[0:15] siul pcr16 16 c3f90000 060 bits[0:15] siul pcr17 16 c3f90000 062 bits[0:15] siul pcr18 16 c3f90000 064 bits[0:15] siul pcr19 16 c3f90000 066 bits[0:15] siul pcr34 16 c3f90000 084 bits[0:15] siul pcr35 16 c3f90000 086 bits[0:15] siul pcr36 16 c3f90000 088 bits[0:15] siul pcr37 16 c3f90000 08a bits[0:15] siul pcr38 16 c3f90000 08c bits[0:15] siul pcr39 16 c3f90000 08e bits[0:15] siul pcr40 16 c3f90000 090 bits[0:15] siul pcr41 16 c3f90000 092 bits[0:15] siul pcr42 16 c3f90000 094 bits[0:15] siul pcr43 16 c3f90000 096 bits[0:15] table 32-5. protected registers (continued) module register protected size (bits) module base address register offset protected bits
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 906 freescale semiconductor siul pcr44 16 c3f90000 098 bits[0:15] siul pcr45 16 c3f90000 09a bits[0:15] siul pcr46 16 c3f90000 09c bits[0:15] siul pcr47 16 c3f90000 09e bits[0:15] siul pcr64 16 c3f90000 0c0 bits[0:15] siul pcr65 16 c3f90000 0c2 bits[0:15] siul pcr66 16 c3f90000 0c4 bits[0:15] siul pcr67 16 c3f90000 0c6 bits[0:15] siul pcr68 16 c3f90000 0c8 bits[0:15] siul pcr69 16 c3f90000 0ca bits[0:15] siul pcr70 16 c3f90000 0cc bits[0:15] siul pcr71 16 c3f90000 0ce bits[0:15] siul pcr72 16 c3f90000 0d0 bits[0:15] siul pcr73 16 c3f90000 0d2 bits[0:15] siul pcr74 16 c3f90000 0d4 bits[0:15] siul pcr75 16 c3f90000 0d6 bits[0:15] siul pcr76 16 c3f90000 0d8 bits[0:15] siul pcr77 16 c3f90000 0da bits[0:15] siul pcr78 16 c3f90000 0dc bits[0:15] siul pcr79 16 c3f90000 0de bits[0:15] siul pcr88 16 c3f90000 0f0 bits[0:15] siul pcr89 16 c3f90000 0f2 bits[0:15] siul pcr90 16 c3f90000 0f4 bits[0:15] siul pcr91 16 c3f90000 0f6 bits[0:15] siul pcr92 16 c3f90000 0f8 bits[0:15] siul pcr93 16 c3f90000 0fa bits[0:15] siul pcr94 16 c3f90000 0fc bits[0:15] siul pcr95 16 c3f90000 0fe bits[0:15] siul pcr96 16 c3f90000 100 bits[0:15] siul pcr97 16 c3f90000 102 bits[0:15] siul pcr98 16 c3f90000 104 bits[0:15] siul pcr99 16 c3f90000 106 bits[0:15] table 32-5. protected registers (continued) module register protected size (bits) module base address register offset protected bits
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 907 siul pcr100 16 c3f90000 108 bits[0:15] siul pcr101 16 c3f90000 10a bits[0:15] siul pcr102 16 c3f90000 10c bits[0:15] siul pcr103 16 c3f90000 10e bits[0:15] siul pcr104 16 c3f90000 110 bits[0:15] siul pcr105 16 c3f90000 112 bits[0:15] siul pcr106 16 c3f90000 114 bits[0:15] siul pcr107 16 c3f90000 116 bits[0:15] siul pcr108 16 c3f90000 118 bits[0:15] siul pcr109 16 c3f90000 11a bits[0:15] siul pcr110 16 c3f90000 11c bits[0:15] siul pcr111 16 c3f90000 11e bits[0:15] siul pcr112 16 c3f90000 120 bits[0:15] siul pcr113 16 c3f90000 122 bits[0:15] siul pcr114 16 c3f90000 124 bits[0:15] siul pcr115 16 c3f90000 126 bits[0:15] siul pcr123 16 c3f90000 136 bits[0:15] siul pcr124 16 c3f90000 138 bits[0:15] siul pcr125 16 c3f90000 13a bits[0:15] siul pcr126 16 c3f90000 13c bits[0:15] siul pcr127 16 c3f90000 13e bits[0:15] siul pcr128 16 c3f90000 140 bits[0:15] siul pcr129 16 c3f90000 142 bits[0:15] siul pcr130 16 c3f90000 144 bits[0:15] siul pcr131 16 c3f90000 146 bits[0:15] siul pcr132 16 c3f90000 148 bits[0:15] siul pcr133 16 c3f90000 14a bits[0:15] siul pcr134 16 c3f90000 14c bits[0:15] siul pcr135 16 c3f90000 14e bits[0:15] siul psmi0_3 8 c3f90000 500 bits[0:7] siul psmi4_7 8 c3f90000 504 bits[0:7] siul psmi8_11 8 c3f90000 508 bits[0:7] table 32-5. protected registers (continued) module register protected size (bits) module base address register offset protected bits
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 908 freescale semiconductor siul psmi12_15 8 c3f90000 50c bits[0:7] siul psmi16_19 8 c3f90000 510 bits[0:7] siul psmi20_23 32 c3f90000 514 bits[0:7] siul psmi24_27 32 c3f90000 518 bits[0:7] siul psmi28_31 32 c3f90000 51c bits[0:7] siul psmi32_35 32 c3f90000 520 bits[0:7] siul psmi36_39 32 c3f90000 524 bits[0:7] siul psmi40_43 32 c3f90000 528 bits[0:7] siul psmi44_47 32 c3f90000 52c bits[0:7] siul psmi48_51 32 c3f90000 530 bits[0:7] siul psmi52_55 32 c3f90000 534 bits[0:7] siul psmi56_59 32 c3f90000 538 bits[0:7] siul psmi61_63 32 c3f90000 53c bits[0:7] siul ifmc0 32 c3f90000 1000 bits[0:31] siul ifmc1 32 c3f90000 1004 bits[0:31] siul ifmc2 32 c3f90000 1008 bits[0:31] siul ifmc3 32 c3f90000 100c bits[0:31] siul ifmc4 32 c3f90000 1010 bits[0:31] siul ifmc5 32 c3f90000 1014 bits[0:31] siul ifmc6 32 c3f90000 1018 bits[0:31] siul ifmc7 32 c3f90000 101c bits[0:31] siul ifmc8 32 c3f90000 1020 bits[0:31] siul ifmc9 32 c3f90000 1024 bits[0:31] siul ifmc10 32 c3f90000 1028 bits[0:31] siul ifmc11 32 c3f90000 102c bits[0:31] siul ifmc12 32 c3f90000 1030 bits[0:31] siul ifmc13 32 c3f90000 1034 bits[0:31] siul ifmc14 32 c3f90000 1038 bits[0:31] siul ifmc15 32 c3f90000 103c bits[0:31] siul ifmc16 32 c3f90000 1040 bits[0:31] siul ifmc17 32 c3f90000 1044 bits[0:31] siul ifmc18 32 c3f90000 1048 bits[0:31] table 32-5. protected registers (continued) module register protected size (bits) module base address register offset protected bits
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 909 siul ifmc19 32 c3f90000 104c bits[0:31] siul ifmc20 32 c3f90000 1050 bits[0:31] siul ifmc21 32 c3f90000 1054 bits[0:31] siul ifmc22 32 c3f90000 1058 bits[0:31] siul ifmc23 32 c3f90000 105c bits[0:31] siul ifcpr 32 c3f90000 1080 bits[0:31] mode entry module, 41 registers to protect mc me me_me 32 c3fdc000 008 bits[0:31] mc me me_im 32 c3fdc000 010 bits[0:31] mc me me_test_mc 32 c3fdc000 024 bits[0:31] mc me me_safe_mc 32 c3 fdc000 028 bits[0:31] mc me me_drun_mc 32 c3fdc000 02c bits[0:31] mc me me_run0_mc 32 c3fdc000 030 bits[0:31] mc me me_run1_mc 32 c3fdc000 034 bits[0:31] mc me me_run2_mc 32 c3fdc000 038 bits[0:31] mc me me_run3_mc 32 c3fdc000 03c bits[0:31] mc me me_halt_mc 32 c3fdc000 040 bits[0:31] mc me me_stop_mc 32 c3fdc000 048 bits[0:31] mc me me_standby_mc 32 c3fdc000 054 bits[0:31] mc me me_run_pc0 32 c3fdc000 080 bits[0:31] mc me me_run_pc1 32 c3fdc000 084 bits[0:31] mc me me_run_pc2 32 c3fdc000 088 bits[0:31] mc me me_run_pc3 32 c3fdc000 08c bits[0:31] mc me me_run_pc4 32 c3fdc000 090 bits[0:31] mc me me_run_pc5 32 c3fdc000 094 bits[0:31] mc me me_run_pc6 32 c3fdc000 098 bits[0:31] mc me me_run_pc7 32 c3fdc000 09c bits[0:31] mc me me_lp_pc0 32 c3fdc000 0a0 bits[0:31] mc me me_lp_pc1 32 c3fdc000 0a4 bits[0:31] mc me me_lp_pc2 32 c3fdc000 0a8 bits[0:31] mc me me_lp_pc3 32 c3fdc000 0ac bits[0:31] mc me me_lp_pc4 32 c3fdc000 0b0 bits[0:31] table 32-5. protected registers (continued) module register protected size (bits) module base address register offset protected bits
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 910 freescale semiconductor mc me me_lp_pc5 32 c3fdc000 0b4 bits[0:31] mc me me_lp_pc6 32 c3fdc000 0b8 bits[0:31] mc me me_lp_pc7 32 c3fdc000 0bc bits[0:31] mc me me_pctl[4..7] 32 c3fdc000 0c4 bits[0:31] mc me me_pctl[16..19] 32 c3fdc000 0d0 bits[0:31] mc me me_pctl[20..23] 32 c3fdc000 0d4 bits[0:31] mc me me_pctl[32..35] 32 c3fdc000 0e0 bits[0:31] mc me me_pctl[44..47] 32 c3fdc000 0ec bits[0:31] mc me me_pctl[48..51] 32 c3fdc000 0f0 bits[0:31] mc me me_pctl[56..59] 32 c3fdc000 0f8 bits[0:31] mc me me_pctl[60..63] 32 c3fdc000 0fc bits[0:31] mc me me_pctl[68..71] 32 c3fdc000 104 bits[0:31] mc me me_pctl[72..75] 32 c3fdc000 108 bits[0:31] mc me me_pctl[88..91] 32 c3fdc000 118 bits[0:31] mc me me_pctl[92..95] 32 c3fdc000 11c bits[0:31] mc me me_pctl[104..107] 32 c3fdc000 128 bits[0:31] clock generation module, 3 registers to protect mc cgm cgm_oc_en 8 c3fe0000 373 bits[0:7] mc cgm cgm_ocds_sc 8 c 3fe0000 374 bits[0:7] mc cgm cgm_sc_dc[0..3] 32 c3fe0000 37c bits[0:31] cmu, 1 register to protect cmu cmu_csr 8 c3fe00e0 103 bits[24:31] reset generation module, 7 registers to protect mc rgm rgm_ferd 16 c3fe4000 004 bits[0:15] mc rgm rgm_derd 16 c3fe4000 006 bits[0:15] mc rgm rgm_fear 16 c3fe4000 010 bits[0:15] mc rgm rgm_dear 16 c3fe4000 012 bits[0:15] mc rgm rgm_fess 16 c3fe4000 018 bits[0:15] mc rgm rgm_stdby 16 c3fe4000 01a bits[0:15] mc rgm rgm_fbre 16 c3fe4000 01c bits[0:15] power control unit, 2 registers to protect table 32-5. protected registers (continued) module register protected size (bits) module base address register offset protected bits
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 911 mc pcu pconf2 32 c3fe8000 008 bits[0:31] mc pcu pconf3 32 c3fe8000 00c bits[0:31] table 32-5. protected registers (continued) module register protected size (bits) module base address register offset protected bits
chapter 32 register protection MPC5606BK microcontroller reference manual, rev. 2 912 freescale semiconductor this page is intent ionally left blank.
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 913 chapter 33 software watchdog timer (swt) 33.1 overview the swt is a peripheral m odule that can prevent system lockup in situations such as software getting trapped in a loop or if a bus tran saction fails to terminate. when enabled, the swt requires periodic execution of a watchdog servic ing sequence. writing the sequence resets the timer to a specified time-out period. if this servicing acti on does not occur before the timer expire s the swt generates an interrupt or hardware reset. the swt can be conf igured to generate a reset or inte rrupt on an initial time-out, a reset is always generated on a se cond consecutive time-out. the swt provides a window functionality. when this functionality is program med, the servicing action should take place within the defined window. when occurring outside the defined period, the swt generates a reset. 33.2 features the swt has the following features: ? 32-bit time-out register to set the time-out period ? the unique swt counter clock is the undivided slow internal rc oscillator 128 khz (sirc), no other clock source can be selected ? programmable selection of window mode or regular servicing ? programmable selection of reset or interrupt on an initial time-out ? master access protection ? hard and soft configuration lock bits ? the swt is started on exit of power-on phase (rgm phase 2) to monitor flash boot sequence phase. it is then reset during rg m phase3 and optionally enabled wh en platform reset is released depending on value of flash us er option bit 31 (watchdog_en). 33.3 modes of operation the swt supports three device mode s of operation: normal, debug, and stop. when the swt is enabled in normal mode, its counter runs continuously. in debug mode, operation of the counter is controlled by the frz bit in the swt_cr. if the frz bit is set, the counter is stopped in debug mode, otherwise it continues to run. in stop mode, oper ation of the counter is controlled by the stp bit in the swt_cr. if the stp bit is set, the counter is stopped in stop mode, otherwise it c ontinues to run. on exit from stop mode, the swt will continue from the st ate it was before entering this mode. the software watchdog is not availabl e during standby. on exit from st andby, the swt beha ves in a usual ?out of rese t? situation.
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 914 freescale semiconductor 33.4 external signal description the swt module does not have a ny external interface signals. 33.5 memory map and register description the swt programming model has six 32-bit register s. the programming model can only be accessed using 32-bit (word) accesses. references using a differ ent size are invalid. other types of invalid accesses include: writes to read only regist ers, incorrect values written to the service register when enabled, accesses to reserved addresses, and accesses by mast ers without permission. if the swt_cr[ria] bit is set, then the swt generates a system reset on an in valid access. otherwise, a bus error is generated. if either the hlk or slk bits in the swt_cr ar e set, then the swt_cr, swt_to, swt_sk, and swt_wn registers are read-only. point save 33.5.1 memory map the swt memory map is shown in table 33-1 . the reset values of sw t_cr, swt_to, and swt_wn are device-specific. these values are determined by swt inputs. table 33-1. swt memory map base address: 0xfff3_8000 address offset register access 1 1 in this column, r/w = read/write, r = read-only, and w = write-only. reset value 23 2 in this column, the format of the rese t value indicates the register width. t hus, reset values of the formats 0xhh, 0xhhhh, and 0xhhhh_hhhh, where h is a hexadecimal digit, i ndicate 8-, 16-, and 32-bit registers, respectively. 3 in this column, the symbol ?u? indicates one or more bits in a byte are undefined at reset. see the associated description for more information. location 0x0000 swt control register (swt_cr) r/w 0x4000_011u on page 915 0x0004 swt interrupt register (swt_ir) r/w 0x0000_0000 on page 916 0x0008 swt time-out register (swt_to) r/w 0x0000_0500 on page 917 0x000c swt window register (swt_wn) r/w 0x0000_0000 on page 917 0x0010 swt service regist er (swt_sr) w 0x0000_0000 on page 918 0x0014 swt counter output register (swt_co) r 0x0000_0000 on page 918 0x0018 swt service key register (swt_sk) w 0x0000_0000 on page 919 0x001c?0xffff reserved
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 915 33.5.2 register description 33.5.2.1 swt control register (swt_cr) the swt_cr contains fields for conf iguring and controlling the swt. the reset value of this register is device specific. some devices can be configured to automatically cl ear the swt_cr[wen] bit during the boot process. if either the swt_cr[hlk] or the swt_ cr[slk] bit is set, this register is read-only. figure 33-1. swt control register (swt_cr) this last bit is cleared when exiting me reset mode in case flash user option bit 31 (watchdog_en) is 0. address: base + 0x0000 access: user read/write 0123456789101112131415 r map 0 map 1 map 2 map 3 map 4 map 5 map 6 map 7 00000 0 00 w reset 1 1 the reset value for the swt_ cr is device-specific. 1000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 00000 key ria wnd itr hlk slk csl stp frz wen w reset0000000100011 0 1_ table 33-2. swt_cr field descriptions field description map n master access protection for master n . allows specific master to update watchdog. map0 = cpu, map2 = edma. the platform bus master assignments are device-specific. 0 access for the master is not enabled 1 access for the master is enabled key keyed service mode. 0 fixed service sequence, the fixed sequence 0xa602, 0xb480 is used to service the watchdog. 1 keyed service mode, two pseudorandom key value are used to service the watchdog. ria reset on invalid access. 0 invalid access to the swt generates a bus error. 1 invalid access to the swt caus es a system reset if wen = 1. wnd window mode. 0 regular mode, service sequence can be done at any time. 1 windowed mode, the service sequence is only valid when the down counter is less than the value in the swt_wn register. itr interrupt then reset. 0 generate a reset on a time-out. 1 generate an interrupt on an initial time-out, reset on a second consecutive time-out.
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 916 freescale semiconductor 33.5.2.2 swt interrupt register (swt_ir) the swt interrupt register (swt_ir) contains the time-out interrupt flag. hlk hard lock. this bit is only cleared at reset. 0 swt_cr, swt_to, swt_wn, and swt_sk are read/write registers if slk = 0. 1 swt_cr, swt_to, swt_wn, and swt_sk are read-only registers. slk soft lock. this bit is cleared by writing the unlock sequence to the swt service register (swt_sr). 0 swt_cr, swt_to, swt_wn, and swt_sk are read/write registers if hlk = 0. 1 swt_cr, swt_to, swt_wn, and swt_sk are read-only registers. csl clock selection. selects the sirc oscillat or clock that drives the internal timer. csl bit can be written.the status of the bit has no effect on counter clock selection on MPC5606BK device. 0 system clock (not applicable in MPC5606BK). 1 oscillator clock. stp stop mode control. allows the watchdog timer to be stopped when the device enters stop mode. 0 swt counter continues to run in stop mode. 1 swt counter is stopped in stop mode. frz debug mode control. allows the watchdog timer to be stopped when the device enters debug mode. 0 swt counter continues to run in debug mode. 1 swt counter is stopped in debug mode. wen watchdog enabled. 0 swt is disabled. 1 swt is enabled. address: base + 0x0004 access: user read/write 0123456789101112131415 r0000000000000 0 00 w reset0000000000000 0 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r 0 000000 0 0 0 0 0 0 0 0tif w w1c reset0000000000000 0 00 figure 33-2. swt interrupt register (swt_ir) table 33-2. swt_cr field descriptions field description
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 917 33.5.2.3 swt time-out register (swt_to) the swt time-out (swt_to) register contains the 32-bit time-out period. th e reset value for this register is device specific. if ei ther the swt_cr[hlk] or the swt_cr[slk] bit is set, this register is read-only. figure 33-3. swt time-out register (swt_to) the default counter value (swt_to_rst) is 1280 (0x0000_0500 hexadecimal), which corresponds to around 10 ms with a 128 khz clock. 33.5.2.4 swt window register (swt_wn) the swt window (swt_wn) register c ontains the 32-bit window start valu e. this register is cleared on reset. if either the swt_cr[hlk] or the swt_cr[ slk] bit is set, this register is read-only. figure 33-4. swt window register (swt_wn) table 33-3. swt_ir field descriptions field description tif time-out interrupt flag. the flag and interrupt are cl eared by writing a 1 to this bit. writing a 0 has no effect. 0 no interrupt request. 1 interrupt request due to an initial time-out. address: base + 0x0008 access: user read/write 012345678910111213141516171819202122232425262728293031 r wto w reset00000000000000000000010100000000 table 33-4. swt_to register field descriptions field description wto watchdog time-out period in clock cycles. when t he service sequence is written or when the swt is enabled, an internal 32-bit down counter is lo aded with the greater of this value or 0x100. address: base + 0x000c access: user read/write 012345678910111213141516171819202122232425262728293031 r wst w reset00000000000000000000000000000000
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 918 freescale semiconductor 33.5.2.5 swt service register (swt_sr) the swt time-out (swt_sr) service register is the target for servic e sequence writes used to reset the watchdog timer. figure 33-5. swt service register (swt_sr) 33.5.2.6 swt counter output register (swt_co) the swt counter output (swt_co) regi ster is a read only register that shows the value of the internal down counter when the swt is disabled. figure 33-6. swt counter output register (swt_co) table 33-5. swt_wn register field descriptions field description wst window start value. when window mode is enabled, the service sequence can only be written when the internal down counter is less than this value. address: base + 0x0010 access: user read/write 012345678910111213141516171819202122232425262728293031 r00000000000000000000000000000000 w wsc reset00000000000000000000000000000000 table 33-6. swt_sr field descriptions field description wsc watchdog service code.this field is used to se rvice the watchdog and to clear the soft lock bit (swt_cr[slk]). to service the wa tchdog, the value 0xa602 followe d by 0xb480 is written to the wsc field. to clear the soft lock bit (swt_cr.slk) , the value 0xc520 followed by 0xd928 is written to the wsc field. address: base + 0x0014 access: user read-only 012345678910111213141516171819202122232425262728293031 r cnt w reset00000000000000000000000000000000
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 919 33.5.2.7 swt service key register (swt_sk) the swt service key (swt_sk) register holds the prev ious (or initial) service key value. if either the swt_cr[hlk] or the swt_cr[slk] bit is set, this register is read-only. figure 7. swt service register (swt_sk) table 8. swt_sk field descriptions 33.6 functional description the swt is a 32-bit timer desi gned to enable the system to recover in situations such as software getting trapped in a loop or if a bus transact ion fails to terminate. it includes a a control register (swt_cr), an interrupt register (swt_ir), time -out register (swt_to), a window register (swt_wn), a service register (swt_sr), a counter out put register (swt_co), and a se rvice key register (swt_sk). the swt_cr includes bits to enable the timer, set c onfiguration options and lo ck configuration of the module. the watchdog is enabled by setting th e swt_cr[wen] bit. the reset value of the swt_cr[wen] bit is device specific1 (enabled). this last bit is cleared when exiting me reset mode in case flash user option bit 31 (watchdog_en) is 0. if the reset value of this bit is 1, the watchdog starts operation automatically after reset is released. some devices can be configured to clear this bit automatically during the boot process. the swt_to register holds the watc hdog time-out period in clock cycles unless the value is less than 0x100, in which case the time-out peri od is set to 0x100. this time-out pe riod is loaded into an internal 32-bit down counter when the swt is enabled and e ach time a valid service sequence is written. the table 33-7. swt_co field descriptions field description cnt watchdog count. when the watchdog is disabled (swt_cr[wen] = 0), this field shows the value of the internal down counter. when the watchdog is enabled, the value of this field is 0x0000_0000. values in this field can lag behi nd the internal counter value for as many as 6 system clock cycles plus 8 counter clock cycles. therefore, the value re ad from this field immediately after disabling the watchdog may be higher than the actual value of the internal counter. address: base + 0x0018 access: user read/write 012345678910111213141516171819202122232425262728293031 r 0 0 0 0 0 0000000000000 00000000 00 0 0 00 w sk reset00000000000000000000000000000000 field description sk service key.this field is the previous (or initial) service key value used in keyed service mode. if swt_cr[key] is set, the next key value to be written to the swt_sk is (17 sk + 3) mod 2 16 .
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 920 freescale semiconductor swt_cr.csl bit selects which clock (s ystem or oscillator) is used to drive the down counter. the reset value of the swt_to regi ster is device-specific as described previously. the configuration of the swt can be lo cked through use of either a soft lock or a hard lock. in either case, when locked the swt_cr, swt_to, swt_wn, and swt_sk registers are read only. the hard lock is enabled by setting the swt_cr[hlk] bit, which can only be cleared by a reset. the soft lock is enabled by setting the swt_cr[slk] bit and is cleared by writing the unlock seque nce to the service register. the unlock sequence is a write of 0xc 520 followed by a write of 0xd928 to the swt_sr[wsc] field. there is no timing requirement between the two writes. the unlock sequence logic ignores service sequence writes and recognizes the 0xc520, 0xd928 sequence regardless of prev ious writes. the unlock sequence can be written at any time and does not require the swt_cr[wen] bit to be set. when enabled, the swt requires periodic execution of the watchdog servicing sequence. writing the proper sequence of values loads th e internal down counter with the time-out period. there is no timing requirement between the tw o writes and the service sequence logic ignores unlock sequenc e writes. if the swt_cr[key] bit = 0, the fixed sequence 0xa602, 0xb 480 is written to the swt_sr[wsc] field to service the watchdog. if the swt_ cr[key] bit = 1, then two pseudorandom keys are written to the swt_sr[wsc] field to service th e watchdog. the key values are determined by the pseudorandom key generator defined in equation 33-1 . eqn. 33-1 this algorithm generates a sequence of 2 16 different key values before repeating. the state of the key generator is held in the swt_sk register. for example, if swt_sk[sk] is 0x0100 then the se rvice sequence keys are 0x1103, 0x2136. in this mode, each time a valid key is written to the swt_sr register, the swt_sk register is updated. so, after servicing the watchdog by writing 0x1103 and then 0x2136 to the swt_sr[wsc] field, swt_sk[sk] is 0x2136 and the next key sequence is 0x3499, 0x7e2c. accesses to swt registers occur with no peripheral bus wait states. (the peripheral bus bridge may add one or more system wait states.) however, due to synchronization logic in th e swt design, r ecognition of the service sequence or configuration changes may require as lo ng as 3 system plus 7 counter clock cycles. if window mode is enabled (swt_cr[wnd] bit is se t), the service sequence must be performed in the last part of the time-out period defined by the window register. the window is open when the down counter is less than the value in the swt_wn register. outs ide of this window, service sequence wr ites are invalid accesses and generate a bus error or reset depending on the value of th e swt_cr[ria] bit. for example, if the swt_to register is set to 5000 and the swt_wn re gister is set to 1000, then the service sequence must be performed in the last 20% of the time-out pe riod. there is a short lag in the time it takes for the window to open due to synchronization logic in the watchdog design. this delay could be as long as 3 system plus 4 counter clock cycles. the interrupt then reset bit (swt_cr[itr]) controls the action taken when a time-out occurs. if the swt_cr[itr] bit is not set, a reset is generated im mediately on a time-out. if the swt_cr[itr] bit is set, an initial time-out causes the swt to generate an inte rrupt and load the down c ounter with the time-out sk n+1 = (17*sk n +3) mod 2 16
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 921 period. if the service sequen ce is not written before the second c onsecutive time-out, the swt generates a system reset. the interrupt is indicated by the ti me-out interrupt flag (swt _ir[tif]). the interrupt request is cleared by writing a one to the swt_ir[tif] bit. the swt_co register shows the va lue of the down counter when the watchdog is disabled. when the watchdog is enabled this register is cleared. the value shown in this register can lag behind the value in the internal counter for as long as 6 system plus 8 counter clock cycles. the swt_co can be used during a so ftware self test of the swt. fo r example, the swt can be enabled and not serviced for a fixed period of time less than the time-out value. then the swt can be disabled (swt_cr[wen] cleared) and the value of the swt_co read to determine if the internal down counter is working properly. note watchdog is disabled at the start of bam execution. in the case of an unexpected issue during bam executi on, the cpu may be stalled and an external reset needs to be generated to recover.
chapter 33 software watchdog timer (swt) MPC5606BK microcontroller reference manual, rev. 2 922 freescale semiconductor this page is intent ionally left blank.
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 923 chapter 34 error correction status module (ecsm) 34.1 introduction the error correction status module (e csm) provides a myriad of miscel laneous control functions for the device including program-visible info rmation about configuration and revision levels, a reset status register, and information on memory er rors reported by error-correcting codes. 34.2 overview the error correction status module is mapped into the ips space and s upports a number of miscellaneous control functions for the device. the aips is the interface between the advanced hi gh performance bus (ahb) in terface and on-chip ips peripherals. ips peripherals are modules that contain readable/writa ble control and status registers. the ahb master reads and writes thes e registers through the aips. the aips generates module enables, the module address, transfer at tributes, byte enables, and write data. th ese elements then function as inputs to the ips peripherals. ? ips ? inter peripheral subsytem ? aips ? interface between the advanced high perf ormance bus (ahb) interface and on-chip ips peripherals ? ahb ? advance high-performance bus 34.3 features the ecsm includes these features: ? program-visible information on th e device configurat ion and revision ? registers for capturing information on memo ry errors due to error-correction codes ? registers to specify the generation of single- and double-bit memory data inversions for test purposes to check ecc protection 34.4 memory map and register description this section details the programming model for the error correction status module. this is a 128-byte space mapped to the region serviced by an ips bus controller. 34.4.1 memory map the error correction status module does not include a ny logic that provides access control. rather, this function is supported using the standard access control logic pr ovided by the ips controller. table 34-1 shows the ecsm?s memory map.
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 924 freescale semiconductor 34.4.2 register description attempted accesses to reserved addresses result in an error termination, while attempted writes to read-only registers are ignored and do not terminate with an error. unle ss noted otherwise, writes to the table 34-1. ecsm memory map base address: 0xfff4_0000 address offset register location 0x00 processor core type register (pct) on page 925 0x02 soc-defined platform revision register (rev) on page 925 0x04 reserved 0x08 ips on-platform module configuration register (iopmc) on page 925 0x0c?0x1e reserved 0x1f miscellaneous interrupt register (mir) on page 927 0x20?0x23 reserved 0x24 miscellaneous user-defined control register (mudcr) on page 928 0x28?0x42 reserved 0x43 ecc configuration register (ecr) on page 929 0x44?0x46 reserved 0x47 ecc status register (esr) on page 931 0x48?0x49 reserved 0x4a ecc error generation register (eegr) on page 932 0x4c?0x4f reserved 0x50 platform flash ecc address register (pfear) on page 935 0x54?0x55 reserved 0x56 platform flash ecc master number register (pfemr) on page 936 0x57 platform flash ecc attributes register (pfeat) on page 936 0x58?0x5b reserved 0x5c platform flash ecc data register (pfedr) on page 937 0x60 platform ram ecc address register (prear) on page 938 0x64 reserved 0x65 platform ram ecc syndrome register (presr) on page 938 0x66 platform ram ecc master number register (premr) on page 940 0x67 platform ram ecc attributes register (preat) on page 941 0x68?0x6b reserved 0x6c platform ram ecc data register (predr) on page 942
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 925 programming model must match the size of the register, e.g., an n-bit re gister only supports n-bit writes, etc. attempted writes of a different size than the re gister width produce an erro r termination of the bus cycle and no change to the targeted register. 34.4.2.1 processor core type register (pct) the pct is a 16-bit read-onl y register specifying the architecture of the processor core in the device. the state of this register is define d by a module input signal; it can onl y be read from the ips programming model. any attempted write is ignored. 34.4.2.2 soc-defined platform revision register (rev) the rev is a 16-bit read-only register specifying a revision number. the st ate of this register is defined by an input signal; it can only be read from the i ps programming model. any at tempted write is ignored. 34.4.2.3 ips on-platform module co nfiguration register (iopmc) the iopmc is a 32-bit read-only register identify ing the presence/absence of the 32 low-order ips peripheral modules connected to the primary ipi slave bu s controller. the state of this register is defined offset: 0x00 access: read 0123456789101112131415 rpct w reset1110000000010010 figure 34-1. processor core type register (pct) table 34-2. pct field descriptions field description pct processor core type offset: 0x02 access: read 0123456789101112131415 rrev w reset0000000000000000 figure 34-2. soc-defined platform revision register (rev) table 34-3. rev field descriptions field description rev revision the rev field is specified by an input signal to define a software-visible revision number.
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 926 freescale semiconductor by a module input signal; it can onl y be read from the ips programmi ng model. any attempted write is ignored. offset: 0x08 access: read 0123456789101112131415 r mc[31:16] w reset:0000100000000011 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r mc[15:0] w reset:1110000000000000 figure 34-3. ips on-platform module configuration register (iopmc) table 34-4. iopmc field descriptions field description mc ips module configuration mc[n] = 0 if an ips module connection to decoded slot n is absent mc[n] = 1 if an ips module connection to decoded slot n is present
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 927 34.4.2.4 miscellaneous interrupt register (mir) all interrupt requests associated with ecsm are coll ected in the mir. this includes the processor core system bus fault interrupt. during the appropriate interrupt serv ice routine handling these requests, the interrupt source contained in the mir must be explicitly cleared. see figure 34-4 and table 34-5 . offset: 0x1f access: special 01234567 r fb0ai fb0si fb1ai fb1si 0 0 0 0 w1111 reset:00000000 figure 34-4. miscellaneous interrupt (mir) register table 34-5. mir field descriptions field description fb0ai flash bank 0 abort interrupt 0 a flash bank 0 abort has not occurred. 1 a flash bank 0 abort has occurred. the interrupt request is negated by writing a 1 to this bit. writing a 0 has no effect. fb0si flash bank 0 stall interrupt 0 a flash bank 0 stall has not occurred. 1 a flash bank 0 stall has occurred. the interrupt requ est is negated by writing a 1 to this bit. writing a 0 has no effect. fb1ai flash bank 1 abort interrupt 0 a flash bank 1 abort has not occurred. 1 a flash bank 1 abort has occurred. the interrupt request is negated by writing a 1 to this bit. writing a 0 has no effect. fb1si flash bank 1 stall interrupt 0 a flash bank 1 stall has not occurred. 1 a flash bank 1 stall has occurred. the interrupt requ est is negated by writing a 1 to this bit. writing a 0 has no effect.
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 928 freescale semiconductor 34.4.2.5 miscellaneous user-defined control register (mudcr) the mudcr provides a program-v isible register for user-defined contro l functions. it typi cally is used as configuration control for miscellaneous soc-level modules. the contents of this register is simply output from the ecsm to other modules where the us er-defined control functions are implemented. 34.4.2.6 ecc registers for designs including error- correcting code (ecc) impl ementations to improve th e quality and reliability of memories, there are a number of program-visible registers for the so le purpose of reporting and logging of memory failures. these registers include: ? ecc configurati on register (ecr) ? ecc status register (esr) ? ecc error generation register (eegr) ? platform flash ecc addr ess register (pfear) ? platform flash ecc master number register (pfemr) ? platform flash ecc attri butes register (pfeat) ? platform flash ecc data register (pfedr) offset: 0x24 access: read/write 0123456789101112131415 r mudcr[31] 000000000000000 w reset:0000000000000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r0000000000000000 w reset:0000000000000000 figure 34-5. miscellaneous user-d efined control (mudcr) register table 34-6. mudcr field descriptions field description mudcr[31] xbar force_round_robin bit this bit is used to drive the force_round_robin bit of the xbar. this will force the slaves into round robin mode of arbitration rather than fixed mode ( unless a master is using priority elevation, which forces the design back into fixed mode regardless of this bit). by setting the hardware definition to enable_round_robin_reset, this bit will reset to 1. 1 xbar is in round robin mode 0 xbar is in fixed priority mode
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 929 ? platform ram ecc address register (prear) ? platform ram ecc syndr ome register (presr) ? platform ram ecc master number register (premr) ? platform ram ecc attributes register (preat) ? platform ram ecc data register (predr) the details on the ecc registers are provided in the subsequent sections. 34.4.2.6.1 ecc configur ation register (ecr) the ecc configuration register is an 8-bit control register for specifying which t ypes of memory errors are reported. in all systems with ecc, the occurrence of a non-correctable error causes the current access to be terminated with an error condition. in many cases , this error termination is reported directly by the initiating bus master. however, there are certain si tuations where the occurrence of this type of non-correctable error is not reported by the mast er. examples include speculati ve instruction fetches that are discarded due to a change-of-f low operation, and buffered operand wr ites. the ecc reporting logic in the ecsm provides an optional error interrupt mechanism to signal all non-correctable memory errors. in addition to the interrupt generation, the ecsm captures specific inform ation (memory address, attributes and data, bus master number, etc.), which may be useful for subsequent failure analysis. offset: 0x43 access: read/write 01234567 r0 0 er1br ef1br 00 erncr efncr w reset:00000000 figure 34-6. ecc configuration (ecr) register table 34-7. ecr field descriptions field description er1br enable sram 1-bit reporting this bit can only be set if the soc-configurable i nput enable signal is asserted. the occurrence of a single-bit sram correction generates a ecsm ecc interrupt request as signaled by the assertion of esr[r1bc]. the address, attributes, and data are also captured in the prear, presr, premr, preat, and predr registers. 0 reporting of single-bit sram corrections is disabled. 1 reporting of single-bit sram corrections is enabled. ef1br enable flash 1-bit reporting this bit can only be set if the soc-configurable i nput enable signal is asserted. the occurrence of a single-bit flash correction generates a ecsm ecc interrupt request as signaled by the assertion of esr[f1bc]. the address, attributes, and data are also captured in the pfear, pfemr, pfeat, and pfedr registers. 0 reporting of single-bit flash corrections is disabled. 1 reporting of single-bit flash corrections is enabled.
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 930 freescale semiconductor erncr enable sram non-correctable reporting the occurrence of a non-correctable multi-bit sram error generates a ecsm ecc interrupt request as signaled by the assertion of esr[rnce]. the faulting address, attributes, and data are also captured in the prear, presr, prem r, preat, and predr registers. 0 reporting of non-correctable sram errors is disabled. 1 reporting of non-correctable sram errors is enabled. efncr enable flash non-correctable reporting the occurrence of a non-correctable multi-bit flash error generates a ecsm ecc interrupt request as signaled by the assertion of esr[fnce]. the faulting address, attributes, and data are also captured in the pfear, pfemr, pfeat, and pfedr registers. 0 reporting of non-correctable flash errors is disabled. 1 reporting of non-correctable flash errors is enabled. table 34-7. ecr field descriptions (continued) field description
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 931 34.4.2.6.2 ecc stat us register (esr) the ecc status register is an 8-bit control regist er for signaling which type s of properly enabled ecc events have been detected. the esr signals the last, properly enabled memory event to be detected. ecc interrupt generation is separated in to single-bit error detection/correc tion, uncorrectable error detection and the combination of the two as de fined by the following boolean equations: ecsm_ecc1bit_irq = ecr[er1br] & esr[ r1bc]// ram, 1-bit correction | ecr[ef1br] & esr[f1bc]// flash, 1-bit correction ecsm_eccrncr_irq = ecr[erncr] & esr[rn ce]// ram, noncorrectable error ecsm_eccfncr_irq = ecr[efncr] & esr[fn ce]// flash, noncorrectable error ecsm_ecc2bit_irq = ecsm_eccrncr_irq/ / ram, noncorrectable error | ecsm_eccfncr_irq// flash, noncorrectable error ecsm_ecc_irq = ecsm_ecc1bit_irq // 1-bit correction | ecsm_ecc2bit_irq// noncorrectable error where the combination of a properl y enabled category in the ecr and the detection of the corresponding condition in the esr produces the interrupt request. the ecsm allows a maximum of one b it of the esr to be asserted at any given time. this preserves the association between the esr and the corresponding addr ess and attribute registers, which are loaded on each occurrence of an properly enabled ecc event. if there is a pending ecc interrupt and another properly enabled ecc event occurs, the ecsm ha rdware automatically ha ndles the esr reporting, clearing the previous data and loading the new state, thus guarantee ing that only a single flag is asserted. to maintain the coherent software view of the reported event, the fo llowing sequence in the ecsm error interrupt service routine is suggested: 1. read the esr and save it. 2. read and save all the address and attribute reporting registers. 3. re-read the esr and verify the current contents matches the original contents. if the two values are different, go back to step 1 and repeat. 4. when the values are identical, write a 1 to the a sserted esr flag to negate the interrupt request.
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 932 freescale semiconductor in the event that multiple status flags are signale d simultaneously, ecsm records the event with the r1bc as highest priority, then f1bc, then rnce, and finally fnce. 34.4.2.6.3 ecc error gene ration register (eegr) the ecc error generation register is a 16-bit control register used to force the generati on of single- and double-bit data inversions in the memories with ecc, most notably the sram. th is capability is provided for two purposes: ? it provides a software-controlled mechanism for injecting errors into the memories during data writes to verify the integrity of the ecc logic. offset: 0x47 access: read/write 01234567 r0 0 r1bc f1bc 00 rnce fnce w reset:00000000 figure 34-7. ecc status register (esr) table 34-8. esr field descriptions field description r1bc sram 1-bit correction this bit can only be set if ecr[epr1br] is asserted. the occurrence of a properly enabled single-bit sram correction generates a ecsm ecc interrupt request. the address, attributes, and data are also captured in the prear, pr esr, premr, preat, and predr regi sters. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable single-bit sram correction has been detected. 1 a reportable single-bit sram correction has been detected. f1bc flash memory 1-bit correction this bit can only be set if ecr[epf1br] is assert ed. the occurrence of a properly enabled single-bit flash memory correction generates a ecsm ecc interrupt request. the address, attributes, and data are also captured in the pf ear, pfemr, pfeat, and pfedr regi sters. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable single-bit flash memory correction has been detected. 1 a reportable single-bit flash memory correction has been detected. rnce sram non-correctable error the occurrence of a properly enabled non-co rrectable sram error generates a ecsm ecc interrupt request. the faulting address, attribut es, and data are also captured in the prear, presr, premr, preat, and predr re gisters. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable non-correctable sram error has been detected. 1 a reportable non-correctable sram error has been detected. fnce flash memory non-correctable error the occurrence of a properly enabled non-correctable flash memory error generates a ecsm ecc interrupt request. the faulting address, attribut es, and data are also captured in the pfear, pfemr, pfeat, and pfedr registers. to clear this interrupt flag, write a 1 to this bit. writing a 0 has no effect. 0 no reportable non-correctable flash memory error has been detected. 1 a reportable non-correctable flash memory error has been detected.
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 933 ? it provides a mechanism to allow testing of the so ftware service routines associated with memory error logging. it should be noted that while the eegr is associated with the sram, similar capabilities exist for the flash, that is, the ability to program the non-volatile me mory with single- or doubl e-bit errors is supported for the same two reasons previously identified. for both types of memories (sram and flash), the intent is to generate errors during data write cycles, such that subsequent reads of the corrupted addres s locations generate ecc events, either single-bit corrections or double-bit non-correct able errors that are termin ated with an error response. offset: 0x4a access: read/write 0123456789101112131415 r0 0 frc1bi fr11bi 00 frcnci fr1nci 0 errbit w reset:0000000000000000 figure 34-8. ecc error generation register (eegr) table 34-9. eegr field descriptions field description frc1bi force sram continuous 1-bit data inversions the assertion of this bit forces the sram controller to create 1-bit data inversions, as defined by the bit position specified in errbit[6:0], continuously on every write operation. the normal ecc generation takes place in the sram controller, but then the polarity of the bit position defined by errbit is inverted to introduce a 1-bit ecc event in the sram. after this bit has been enabled to generate another continuous 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. 0 no sram continuous 1-bit data inversions are generated. 1 1-bit data inversions in the sram are continuously generated. fr11bi force sram one 1-bit data inversion the assertion of this bit forces the sram controller to create one 1-bit data inversion, as defined by the bit position specified in errbit[6:0], on the first write operation after this bit is set. the normal ecc generation takes place in the sram controller, but then the polarity of the bit position defined by errbit is inverted to introduce a 1-bit ecc event in the sram. after this bit has been enabled to generate a single 1-bit data inversion, it must be cleared before being set again to properly re-enable the error generation logic. this bit can only be set if the same soc configurable input enable signal (as that used to enable single-bit correction reporting) is asserted. 0 no sram single 1-bit data inversion is generated. 1 one 1-bit data inversion in the sram is generated.
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 934 freescale semiconductor frcnci force sram continuous non-correctable data inversions the assertion of this bit forces the sram controller to create 2-bit data inversions, as defined by the bit position specified in errbit[6:0] and the overall odd parity bit, continuously on every write operation. after this bit has been enabled to generate another continuous non-correctable data inversion, it must be cleared before being set again to properly re-enable the error generation logic. the normal ecc generation takes place in the sram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the sram. 0 no sram continuous 2-bit data inversions are generated. 1 2-bit data inversions in the sram are continuously generated. fr1nci force sram one non-correctable data inversions the assertion of this bit forces the sram controller to create one 2-bit data inversion, as defined by the bit position specified in errbit[6:0] and the ov erall odd parity bit, on the first write operation after this bit is set. the normal ecc generation takes place in the sram controller, but then the polarity of the bit position defined by errbit and the overall odd parity bit are inverted to introduce a 2-bit ecc error in the sram. after this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to properly re-enable the error generation logic. 0 no sram single 2-bit data inversions are generated. 1 one 2-bit data inversion in the sram is generated. errbit error bit position the vector defines the bit position that is comple mented to create the data inversion on the write operation. for the creation of 2-bit data inversions, t he bit specified by this field plus the odd parity bit of the ecc code are inverted. the sram controller follows a vector bit ordering scheme where lsb = 0. errors in the ecc syndrome bits can be generated by setting this field to a value greater than the sram width. for example, consider a 32-bit sram implementation. the 32-bit ecc approach requires 7 code bits for a 32- bit word. for pram data width of 32 bits, the actual sram (32b data + 7b for ecc) = 39 bits. the following association between the errbit field and the corrupted memory bit is defined: if errbit = 0, then sram[0] of the odd bank is inverted if errbit = 1, then sram[1] of the odd bank is inverted ... if errbit = 31, then sram[31] of the odd bank is inverted if errbit = 64, then ecc parity[0] of the odd bank is inverted if errbit = 65, then ecc parity[1] of the odd bank is inverted ... if errbit = 70, then ecc parity[6] of the odd bank is inverted for errbit values of 32 to 63 and greater than 70, no bit position is inverted. table 34-9. eegr field descriptions (continued) field description
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 935 if an attempt to force a non-correctable invers ion (by asserting eegr[f rcnci] or eegr[frc1nci]) and eegr[errbit] equals 64, then no data inversion will be generated. the only allowable values for the 4 control bit enables {fr11bi, frc1bi , frcnci, fr1nci} are {0,0,0,0}, {1,0,0,0}, {0,1,0,0}, {0,0,1,0}, and {0,0,0,1}. all other values result in undefined behavior. 34.4.2.6.4 platform flash ec c address register (pfear) the pfear is a 32-bit register for capturing the addr ess of the last, properly enabled ecc event in the flash memory. depending on the state of the ecc configurati on register, an ecc even t in the flash causes the address, attributes, and data a ssociated with the access to be loaded into the pfear, pfemr, pfeat, and pfedr registers, and the appropria te flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips pr ogramming model; any atte mpted write is ignored. offset: 0x50 access: read 0123456789101112131415 r fear[31:16] w reset:???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fear[15:0] w reset:???????????????? figure 34-9. platform flash ecc address register (pfear) table 34-10. pfear field descriptions field description fear flash ecc address register this 32-bit register contains the faulting acce ss address of the last, properly enabled flash ecc event.
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 936 freescale semiconductor 34.4.2.6.5 platform flash ecc mast er number regi ster (pfemr) the pfemr is a 4-bit register for capturing the xbar bus master number of th e last, properly enabled ecc event in the flash memory. depe nding on the state of the ecc conf iguration register, an ecc event in the flash causes the address, attr ibutes, and data associated with the access to be loaded into the pfear, pfemr, pfeat, and pfedr registers, and the appropr iate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips pr ogramming model; any atte mpted write is ignored. . 34.4.2.6.6 platform flash ecc at tributes register (pfeat) the pfeat is an 8-bit register for capturing the xbar bus master attri butes of the last, properly enabled ecc event in the flash memory. depe nding on the state of the ecc conf iguration register, an ecc event in the flash causes the address, attr ibutes, and data associated with the access to be loaded into the pfear, pfemr, pfeat, and pfedr registers, and the appropr iate flag (f1bc or fnce) in the ecc status register to be asserted. this register can only be read from the ips pr ogramming model; any atte mpted write is ignored. offset: 0x56 access: read 01234567 r0000 femr w reset:0000???? figure 34-10. platform flash ecc master number register (pfemr) table 34-11. pfemr field descriptions field description femr flash ecc master number register this 4-bit register contains the xbar bus master number of the faul ting access of the last, properly enabled flash ecc event. offset: 0x57 access: read 01234567 r write size protection w reset:???????? figure 34-11. platform flash ecc attributes register (pfeat) table 34-12. pfeat field descriptions field description write amba-ahb hwrite 0 amba-ahb read access 1 amba-ahb write access
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 937 34.4.2.6.7 platform flash ecc data register (pfedr) the pfedr is a 32-bit register for capturing the data associated with the last, properly enabled ecc event in the flash memory. depending on th e state of the ecc configuration re gister, an ecc event in the flash causes the address, attributes, and data associated with the access to be loaded into the pfear, pfemr, pfeat, and pfedr registers, and the appropriate flag (f1bc or fnce) in the ecc st atus register to be asserted. the data captured on a multi-bit non- correctable ecc error is undefined. this register can only be read from the ips pr ogramming model; any atte mpted write is ignored. size amba-ahb hsize[2:0] 000 8-bit amba-ahb access 001 16-bit amba-ahb access 010 32-bit amba-ahb access 1xx reserved protection amba-ahb hprot[3:0] protection[3]: cacheable 0 = non-cacheable, 1 = cacheable protection[2]: bufferable 0 = non-bufferable, 1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data offset: 0x5c access: read 0123456789101112131415 r fedr[31:16] w reset:???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r fedr[15:0] w reset:???????????????? figure 34-12. platform flash ecc data register (pfedr) table 34-13. pfedr field descriptions field description fedr flash ecc data register this 32-bit register contains the data associated wi th the faulting access of the last, properly enabled flash ecc event. the register contains the data value taken directly from the data bus. table 34-12. pfeat field descriptions (continued) field description
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 938 freescale semiconductor 34.4.2.6.8 platform ram ec c address register (prear) the prear is a 32-bit register for capturing the addr ess of the last, properly enabled ecc event in the sram memory. depending on the state of the ecc configuration regist er, an ecc event in the sram causes the address, attributes, and data associated with the access to be loaded into the prear, presr, premr, preat, and predr registers, and the appr opriate flag (r1bc or rnce) in the ecc status register to be asserted. this register can only be read from the ips pr ogramming model; any atte mpted write is ignored. 34.4.2.6.9 platform ram ecc syndrome register (presr) the presr is an 8-bit register for capturing the er ror syndrome of the last, properly enabled ecc event in the sram memory. depending on th e state of the ecc configuration register, an ecc event in the sram causes the address, attributes , and data associated with the acce ss to be loaded into the prear, presr, premr, preat, and predr registers, and the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. this register can only be read from the ips pr ogramming model; any atte mpted write is ignored. offset: 0x60 access: read 0123456789101112131415 r rear[31:16] w reset:???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r rear[15:0] w reset:???????????????? figure 34-13. platform ram ecc address register (prear) table 34-14. prear field descriptions field description rear sram ecc address register this 32-bit register contains the faulting acce ss address of the last, properly enabled sram ecc event. offset: 0x65 access: read 01234567 r resr w reset:???????? figure 34-14. platform ram ecc syndrome register (presr)
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 939 table 34-16 associates the upper 7 bits of the ecc syndrome with the exact da ta bit in error for single-bit correctable codewords. this table follows the bit vectoring notation where the lsb = 0. note that the syndrome value of 0x01 implies no error condition but this value is not readable when the presr is read for the no error case. table 34-15. presr field descriptions field description resr sram ecc syndrome register this 8-bit syndrome field includes 6 bits of hamming decoded parity plus an odd-parity bit for the entire 39-bit (32-bit data + 7 ecc) code word. the upper 7 bits of the syndrome specify the exact bit position in error for single-bit correctable c odewords, and the combination of a non-zero 7-bit syndrome plus overall incorrect parity bit signal a multi-bit, non-correctable error. for correctable single-bit errors, the mapping shown in table 34-16 associates the upper 7 bits of the syndrome with the data bit in error. table 34-16. ram syndrome mapping for single-bit correctable errors presr[resr] data bit in error 0x00 ecc odd[0] 0x01 no error 0x02 ecc odd[1] 0x04 ecc odd[2] 0x06 data odd bank[31] 0x08 ecc odd[3] 0x0a data odd bank[30] 0x0c data odd bank[29] 0x0e data odd bank[28] 0x10 ecc odd[4] 0x12 data odd bank[27] 0x14 data odd bank[26] 0x16 data odd bank[25] 0x18 data odd bank[24] 0x1a data odd bank[23] 0x1c data odd bank[22] 0x50 data odd bank[21] 0x20 ecc odd[5] 0x22 data odd bank[20] 0x24 data odd bank[19] 0x26 data odd bank[18]
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 940 freescale semiconductor 34.4.2.6.10 platform ram ecc mast er number register (premr) the premr is a 4-bit register for capturing the xbar bus master number of th e last, properly enabled ecc event in the sram memory. depending on the st ate of the ecc configuration register, an ecc event in the sram causes the address, attributes, and data associated with the access to be loaded into the prear, presr, premr, preat, and predr register s, and the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. see chapter 19, crossbar switch (xbar) , for a listing of xbar bus master numbers. this register can only be read from the ips pr ogramming model; any atte mpted write is ignored. 0x28 data odd bank[17] 0x2a data odd bank[16 0x2c data odd bank[15] 0x58 data odd bank[14] 0x30 data odd bank[13] 0x32 data odd bank[12] 0x34 data odd bank[11] 0x64 data odd bank[10] 0x38 data odd bank[9] 0x62 data odd bank[8] 0x70 data odd bank[7] 0x60 data odd bank[6] 0x40 ecc odd[6] 0x42 data odd bank[5] 0x44 data odd bank[4] 0x46 data odd bank[3] 0x48 data odd bank[2] 0x4a data odd bank[1] 0x4c data odd bank[0] 0x03,0x05........0x4d multiple bit error > 0x4d multiple bit error table 34-16. ram syndrome mapping for singl e-bit correctable errors (continued) presr[resr] data bit in error
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 941 34.4.2.6.11 platform ram ecc at tributes register (preat) the preat is an 8-bit register for capturing the xbar bus ma ster attributes of th e last, properly enabled ecc event in the sram memory. depending on the st ate of the ecc configuration register, an ecc event in the sram causes the address, attributes, and data associated with the access to be loaded into the prear, presr, premr, preat, and predr register s, and the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. offset: 0x66 access: read 01234567 r0000 remr w reset:0000???? figure 34-15. platform ram ecc master number register (premr) table 34-17. premr field descriptions field description remr sram ecc master number register this 4-bit register contains the xbar bus master number of the faul ting access of the last, properly enabled sram ecc event. see chapter 19, crossbar switch (xbar) , for a listing of xbar bus master numbers. offset: 0x67 access: read 01234567 r write size protection w reset:???????? figure 34-16. platform ram ecc attributes register (preat) table 34-18. preat field descriptions field description write xbar hwrite 0 xbar read access 1 xbar write access size xbar hsize[2:0] 000 8-bit xbar access 001 16-bit xbar access 010 32-bit xbar access 1xx reserved protection xbar hprot[3:0] protection[3]: cacheable 0 = non-cacheable, 1 = cacheable protection[2]: bufferable 0 = non-bufferable, 1 = bufferable protection[1]: mode 0 = user mode, 1 = supervisor mode protection[0]: type 0 = i-fetch, 1 = data
chapter 34 error correction status module (ecsm) MPC5606BK microcontroller reference manual, rev. 2 942 freescale semiconductor 34.4.2.6.12 platform ram ec c data register (predr) the predr is a 32-bit regist er for capturing the data associated with the last, properly enabled ecc event in the sram memory. depending on th e state of the ecc configuration register, an ecc event in the sram causes the address, attributes , and data associated with the acce ss to be loaded into the prear, presr, premr, preat, and predr registers, and the appropriate flag (r1bc or rnce) in the ecc status register to be asserted. the data captured on a multi-bit non- correctable ecc error is undefined. 34.4.3 register protection logic exists that restricts acce sses to intc, ecsm, mpu, stm, and swt to supervisor mode only. accesses in user mode are not possible. offset: 0x6c access: read 0123456789101112131415 r redr[31:16] w reset:???????????????? 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rredr[15:0] w reset:???????????????? figure 34-17. platform ram ecc data register (predr) table 34-19. predr field descriptions field description redr sram ecc data register this 32-bit register contains the data associated wi th the faulting access of the last, properly enabled sram ecc event. the register contains the da ta value taken directly from the data bus.
MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 943 ??? debug ???
MPC5606BK microcontroller reference manual, rev. 2 944 freescale semiconductor this page is intent ionally left blank.
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 945 chapter 35 ieee 1149.1 test access port controller (jtagc) 35.1 introduction the jtag port of the device consists of three inputs and one output. these pins include test data input (tdi), test data output (tdo), test mode select (tms), and test cloc k input (tck). tdi, tdo, tms, and tck are compliant with the ieee 1149.1-2001 standard and are shared with the ndi through the test access port (tap) interface. 35.2 block diagram figure 35-1 is a block diagram of the jt ag controller (jtagc) block. figure 35-1. jtag controller block diagram 35.3 overview the jtagc provides the means to test chip functionality and connectivit y while remaining transparent to system logic when not in test mode . testing is performed via a boundary scan tec hnique, as defined in the ieee 1149.1-2001 standard. in additi on, instructions can be executed that allow the test access port (tap) to be shared with other modules on the mcu. all data input to and output from the jtagc is communicated in serial format. tck tms tdi test access port (tap) tdo 32-bit device identification register boundary scan register . . controller 1-bit bypass register . 5-bit tap instruction decoder 5-bit tap instruction register . . . power-on reset
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 946 freescale semiconductor 35.4 features the jtagc is compliant with the ieee 1149.1-2001 st andard, and supports th e following features: ? ieee 1149.1-2001 test access port (tap) interface ? four pins (tdi, tms, tck, and tdo)?refer to section 35.6, external signal description ? a 5-bit instruction register th at supports several ieee 1149.1-2001 defined instru ctions, as well as several public and private mcu specific instructions ? two test data registers: ? bypass register ? device identification register ? a tap controller state machine that controls the ope ration of the data register s, instruction register, and associated circuitry 35.5 modes of operation the jtagc uses a power-on reset indication as it s primary reset signals. several ieee 1149.1-2001 defined test modes are supporte d, as well as a bypass mode. 35.5.1 reset the jtagc is placed in reset when the tap controller state machine is in the test-logic-reset state. the test-logic-reset state is ente red upon the assertion of the power -on reset signal, or through tap controller state machine transitions controlled by tms. as serting power-on reset results in asynchronous entry into the reset state. while in reset, the following actions occur: ? the tap controller is forced into the test-logic- reset state, thereby disa bling the test logic and allowing normal operation of the on-chip system logic to continue unhindered. ? the instruction register is load ed with the idcode instruction. in addition, execution of certain instructions can result in assertion of the internal system reset. these instructions include extest. 35.5.2 ieee 1149.1-2001 defined test modes the jtagc supports several ieee 1149.1-2001 defined test modes. the test mode is selected by loading the appropriate instruction in to the instruction register while the jtagc is enabled. supported test instructions include extest, sample, and sample/ preload. each instruction defines the set of data registers that can operate and in teract with the on-chip system logi c while the instruction is current. only one test data register path is enabled to shift data betwee n tdi and tdo for each instruction. the boundary scan register is external to jtagc but can be accessed by jtagc tap through extest,sample,sample/preload instructions. th e functionality of each test mode is explained in more detail in section 35.8.4, jtagc instructions .
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 947 35.5.2.1 bypass mode when no test operation is required, the bypass instruction can be load ed to place the jtagc into bypass mode. while in bypass mode, the single-bit bypass shif t register is used to provide a minimum-length serial path to shift da ta between tdi and tdo. 35.5.2.2 tap sharing mode there are three selectable auxiliar y tap controllers that share the tap with the jtagc. selectable tap controllers include the platform. the instructions required to grant ownership of the tap to the auxiliary tap controllers ar e access_aux_tap_once and acce ss_aux_tap_tcu. instruction opcodes for each instruction are shown in table 35-3 . when the access instruction fo r an auxiliary tap is loaded, control of the jtag pins is transferred to the selected tap controller. a ny data input via tdi and tm s is passed to the selected tap controller, and any tdo output from the selected tap c ontroller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jt ag port during the update-dr st ate if the pause-dr state was entered. auxiliary tap controllers are held in run-test/idle while they are inactive. 35.6 external signal description the jtagc consists of four signals that connect to off-chip development tools and allow access to test support functions. the jtagc signals are outlined in table 35-1 : the jtagc pins are shared with gpio. tdo at rese t is a input pad and output direction control from jtagc. once tap enters shift-ir or shift-dr then out put direction control from jtagc, which allows the value to see on pad. it is up to the user to configure them as gpios accordingly. 35.7 memory map and register description this section provides a detailed de scription of the jtagc registers accessible thr ough the tap interface, including data registers and the instru ction register. individual bit-level descriptions and reset states of each register are included. these registers are not memory-mapped a nd can only be accessed through the tap. 35.7.1 instruction register the jtagc uses a 5-bit instruction register as shown in table 35-2 . the instruction register allows instructions to be loaded into the module to select the test to be performed or the test data register to be table 35-1. jtag signal properties name i/o function reset state tck i test clock pull up tdi i test data in pull up tdo o test data out high z tms i test mode select pull up
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 948 freescale semiconductor accessed or both. instructions are shifted in through tdi while the tap controller is in the shift-ir state, and latched on the falling edge of tck in the update -ir state. the latched inst ruction value can only be changed in the update-ir and te st-logic-reset tap controller st ates. synchronous entry into the test-logic-reset state results in the idcode inst ruction being loaded on the falling edge of tck. asynchronous entry into the test-logic-reset state results in asynchronous loading of the idcode instruction. during the capture-ir tap co ntroller state, the instruction sh ift register is loaded with the value 0b10101, making this value the register?s read value when the ta p controller is sequenced into the shift-ir state. 35.7.2 bypass register the bypass register is a single-bit shif t register path selected for serial data transfer be tween tdi and tdo when the bypass, or reserve instructions are active. after entry into the captur e-dr state, the single-bit shift register is set to a logic 0. therefore, the first bit shifted out after selecting the bypass register is always a logic 0. 35.7.3 device identification register the device identificati on register, shown in table 35-3 , allows the part revision number, design center, part identification number, and manufactu rer identity code to be determ ined through the tap. the device identification register is selected for serial data transfer betw een tdi and tdo when the idcode instruction is active. entry into the capture-dr stat e while the device identificat ion register is selected loads the idcode into the shift regi ster to be shifted out on tdo in the shift-dr st ate. no action occurs in the update-dr state. 43210 r1 0 1 01 w instruction code reset00001 figure 35-2. 5-bit instruction register ir[4:0]: 0_0001 (idcode) access: r/o 0 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031 r prn dc pin mic id w reset 00000110101001000010000000011101 figure 35-3. device identification register table 35-2. device identification register field descriptions field description 0?3 prn part revision number. contains the revision number of the device. this field changes with each revision of the device or module. 4?9 dc design center. for the MPC5606BK this value is 0x1a.
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 949 35.7.4 boundary scan register the boundary scan register is connected betw een tdi and tdo when the extest, sample or sample/preload instructions are active. it is used to capture input pin da ta, force fixed values on output pins, and select a logic value and direction fo r bidirectional pins. each bit of the boundary scan register represents a sepa rate boundary scan register cell, as described in the ieee 1149.1-2001 standard and discussed in section 35.8.5, boundary scan . the size of the boundary scan register is 464 bits. 35.8 functional description 35.8.1 jtagc reset configuration while in reset, the tap controller is forced into the test-logic-reset state, thus disabling the test logic and allowing normal operation of the on-chip system logic. in addition, the inst ruction register is loaded with the idcode instruction. 35.8.2 ieee 1149.1-2001 (j tag) test access port the jtagc uses the ieee 1149.1-2001 tap for accessing re gisters. this port can be shared with other tap controllers on the mcu. for more detail on tap sharing via jtagc in structions refer to section 35.8.4.2, access_aux_tap_x instructions . data is shifted between tdi and tdo though the selected register starting wi th the least significant bit, as illustrated in figure 35-4 . this applies for the instruction regist er, test data registers, and the bypass register. figure 35-4. shifting data through a register 35.8.3 tap controller state machine 10?19 pin part identification number. contains the part number of the device. for the MPC5606BK, this value is 0x244. 20?30 mic manufacturer identity code. contains the reduced joint electron device engineering council (jedec) id for freescale, 0xe 31 id idcode register id. identifies this register as the device identification re gister and not the bypass register. always set to 1. table 35-2. device identification register field descriptions field description selected register msb lsb tdi tdo
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 950 freescale semiconductor the tap controller is a synchronous state machine that interprets the sequence of logical values on the tms pin. figure 35-5 shows the machine?s states. the value show n next to each state is the value of the tms signal sampled on the rising edge of the tck signal. as figure 35-5 shows, holding tms at logic 1 while cloc king tck through a suffic ient number of rising edges also causes the state machine to enter the test-logic-reset state. figure 35-5. ieee 1149.1-2001 tap controller finite state machine test logic reset run-test/idle select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 1 0 1 1 1 00 0 0 1 1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 0 note: the value shown adjacent to each state transition in this figure represents the value of tms at the time of a rising edge of tck.
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 951 35.8.3.1 selecting an ie ee 1149.1-2001 register access to the jtagc data registers is done by loading the instruction register with any of the jtagc instructions while the jtagc is enab led. instructions are shifted in via the select-ir-scan path and loaded in the update-ir state. at this poi nt, all data register access is perf ormed via the select-dr-scan path. the select-dr-scan path is used to read or write the register data by shifting in the data (lsb first) during the shift-dr state. when reading a register, the register value is loaded into the ieee 1149.1-2001 shifter during the capture-dr state. when writing a register, the value is loaded from the ieee 1149.1-2001 shifter to the register during the update-dr state. wh en reading a register, there is no requirement to shift out the entire register c ontents. shifting can be terminated afte r fetching the required number of bits. 35.8.4 jtagc instructions this section gives an overview of each instructi on, refer to the ieee 1149.1-2001 standard for more details. the jtagc implements the ieee 1149.1-2001 defined instructions listed in table 35-3 . 35.8.4.1 bypass instruction bypass selects the bypass register, creating a single-bit shift regist er path between tdi and tdo. bypass enhances test efficiency by reducing the overall shift path when no test operation of the mcu is required. this allows more rapid move ment of test data to and from other components on a board that are required to perform test functions. while the bypass instruction is active the system logic operates normally. table 35-3. jtag instructions instruction code[4:0] instruction summary idcode 00001 selects device identification register for shift sample/preload 00010 selects boundary scan register for shifting, sampling, and preloading without disturbing functional operation sample 00011 selects boundary scan register for shifting and sampling without disturbing functional operation extest 00100 selects boundary scan register while applying preloaded values to output pins and asserting functional reset access_aux_tap_once 10001 grants the platform ownership of the tap reserved 10010 ? bypass 11111 selects bypass register for data operations factory debug reserved 1 1 intended for factory debug, and not customer use 00101 00110 01010 intended for factory debug only reserved 2 2 freescale reserves the right to change the decoding of reserved instruction codes all other codes decoded to select bypass register
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 952 freescale semiconductor 35.8.4.2 access_aux_tap_ x instructions the access_aux_tap_ x instructions allow the ne xus modules on the mcu to ta ke control of the tap. when this instruction is loaded, control of the tap pins is transferred to the selected auxiliary tap controller. any data input via tdi and tms is passed to the selected tap contro ller, and any tdo output from the selected tap controller is sent back to the jtagc to be output on the pins. the jtagc regains control of the jtag port during the update-dr state if the pause-dr state was entered. auxiliary tap controllers are held in run-test/idle while they are inactive. 35.8.4.3 extest ? extern al test instruction extest selects the boundary scan regi ster as the shift path between td i and tdo. it allows testing of off-chip circuitry and board-level interconnections by driving preloa ded data contained in the boundary scan register onto the syst em output pins. typically, th e preloaded data is loaded into the boundary scan register using the sample/preload instruction before the selecti on of extest. extest asserts the internal system reset for the mcu to force a predictable internal st ate while performing external boundary scan operations. 35.8.4.4 idcode instruction idcode selects the 32-bit device identification regist er as the shift path between tdi and tdo. this instruction allows interrogation of the mcu to determ ine its version number and other part identification data. idcode is the instruction placed into th e instruction register when the jtagc is reset. 35.8.4.5 sample instruction the sample instruction obtains a samp le of the system data and contro l signals present at the mcu input pins and just before the boundary scan register cells at the output pins . this sampling occurs on the rising edge of tck in the capture-dr state when the sample instruction is active. the sampled data is viewed by shifting it through th e boundary scan register to the tdo output during the shift-dr state. there is no defined action in the update -dr state. both the data capture and the shift operation are transparent to system operation. during the sample instruction, the fo llowing pad status is enforced: ? weak pull is disabled (i ndependent from pcrx[wpe]) ? analog switch is disabled (independent of pcrx[apc]) ? slew rate control is forced to the slowes t configuration (independe nt from pcrx[src[1]]) 35.8.4.6 sample/preload instruction the sample/preload instru ction has two functions: ? the sample part of the instruction samples the system data and control signals on the mcu input pins and just before the boundary scan register ce lls at the output pins. this sampling occurs on the rising-edge of tck in the capture-dr state wh en the sample/preload in struction is active. the sampled data is viewed by shifting it thr ough the boundary scan register to the tdo output
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 953 during the shift-dr state. both th e data capture and the shift operation are transparent to system operation. ? the preload part of the instruction initializes the boundary scan register cells before selecting the extest instructions to perform boundary scan tests. this is achieved by shifting in initialization data to the boundary sc an register during the shift-dr st ate. the initialization data is transferred to the parallel outputs of the boundary s can register cells on the falling edge of tck in the update-dr state. the data is applied to the external output pins by the extest instruction. system operation is not affected. during the sample/preload instruction, the following pad status is enforced: ? weak pull is disabled (i ndependent from pcrx[wpe]) ? analog switch is disabled (independent of pcrx[apc]) ? slew rate control is forced to the slowes t configuration (independe nt from pcrx[src[1]]) 35.8.5 boundary scan the boundary scan technique allows signals at component boundaries to be controlled and observed through the shift-register stage asso ciated with each pad. each stage is part of a larger boundary scan register cell, and cells for each pad are interconnected serially to form a shift-register chain around the border of the design. the boundary scan register consists of this shift -register chain, and is connected between tdi and tdo when the extest, sample, or sample/preload instructions are loaded. the shift-register chain contains a serial input and serial output, as well as clock and control signals. 35.9 e200z0 once controller the e200z0 core once controller supports a comple te set of nexus 1 debug features. a complete discussion of the e200z0 once debug features is available in the e200z0 reference manual . 35.9.1 e200z0 once controller block diagram figure 35-6 is a block diagram of the e200z0 once block.
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 954 freescale semiconductor figure 35-6. e200z0 once block diagram 35.9.2 e200z0 once contro ller functional description the functional description for the e200z0 once controller is the same as for the jtagc, with the differences described below. 35.9.2.1 enabling th e tap controller to access the e200z0 once controller, the proper jt agc instruction needs to be loaded in the jtagc instruction register, as discussed in section 35.5.2.2, tap sharing mode . 35.9.3 e200z0 once controller register description most e200z0 once debug register s are fully documented in the e200z0 reference manual . 35.9.3.1 once command register (ocmd) the once command register (ocmd) is a 10-bit shift re gister that receives its serial data from the tdi pin and serves as the instruction re gister (ir). it holds th e 10-bit commands to be used as input for the e200z0 once decoder. th e ocmd is shown in table 35-7 . the ocmd is updated when the tap controller enters the update -ir state. it contains fields for cont rolling access to a resource, as well as controlling single-step operati on and exit from once mode. tck e200z0_tms tdi test access port (tap) e200z0_tdo bypass register external data register . . controller tap instruction register . once mapped debug registers auxiliary data register . . . e200z0_trst (once ocmd) tdo mux control { from jtagc (to jtagc)
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 freescale semiconductor 955 although the ocmd is updated during the update-ir tap controller stat e, the correspondi ng resource is accessed in the dr scan sequence of the tap cont roller, and as such, the update-dr state must be transitioned through in order for an access to occu r. in addition, the update-dr state must also be transitioned through in order for the single-step and/or exit functionali ty to be performed, even though the command appears to have no data resour ce requirement associated with it. 0123456789 r r/w go ex rs[0:6] w reset:0000011011 figure 35-7. once command register (ocmd) table 35-4. e200z0 once register addressing rs[0:6] register selected 000 0000 000 0001 reserved 000 0010 jtag id (read-only) 000 0011 ? 000 1111 reserved 001 0000 cpu scan register (cpuscr) 001 0001 no register selected (bypass) 001 0010 once control register (ocr) 001 0011 ? 001 1111 reserved 010 0000 instruction address compare 1 (iac1) 010 0001 instruction address compare 2 (iac2) 010 0010 instruction address compare 3 (iac3) 010 0011 instruction address compare 4 (iac4) 010 0100 data address compare 1 (dac1) 010 0101 data address compare 2 (dac2) 010 0110 data value compare 1 (dvc1) 010 0111 data value compare 2 (dvc2) 010 1000 ? 010 1111 reserved 011 0000 debug status register (dbsr) 011 0001 debug control register 0 (dbcr0) 011 0010 debug control register 1 (dbcr1) 011 0011 debug control register 2 (dbcr2) 011 0100 ? 110 1111 reserved (do not access) 111 0000 ? 111 1001 general purpose register selects [0:9] 111 1010 ? 111 1100 reserved
chapter 35 ieee 1149.1 test access port controller (jtagc) MPC5606BK microcontroller reference manual, rev. 2 956 freescale semiconductor 35.10 initialization/application information the test logic is a static logic de sign, and tck can be stopped in either a high or low state without loss of data. however, the system clock is not synchroni zed to tck internally. a ny mixed operation using both the test logic and the system functional logic requires extern al synchronization. to initialize the jtagc module and enable access to registers, the follow ing sequence is required: 1. place the jtagc in reset through tap controller state machine transitions controlled by tms 2. load the appropriate instruction for the test or action to be performed. 111 1101 lsrl select (factory test use only) 111 1110 enable_once 111 1111 bypass table 35-4. e200z0 once register addressing (continued) rs[0:6] register selected
appendix a revision history 955 freescale semiconductor appendix a revision history this appendix describes corrections to the MPC5606BK microcontroller reference manual . for convenience, the corrections are grouped by revision. a.1 changes between revisions 1 and 2 table a-1. changes between revisions 1 and 2 chapter description throughout updated device name to MPC5606BK. chapter 2, introduction in figure 2-1 (MPC5606BK block diagram) : ? changed ?64-bit 2 3 crossbar switch? to ?32-bit 3 3 crossbar switch.? in table 2-1 (MPC5606BK family comparison) , added 100lqfp option for MPC5606BK and updated the code flash memory for 100 lqfp to 1024 kb. in table 2-2 (MPC5606BK series block summary) : ? changed ?supports simultaneous connections between two master ports? to ?supports simultaneous connections between three ma ster ports and three slave ports.? ? corrected ?32 khz oscillator? to ?32 khz oscillator.? in section 2.4.1, e200z0h core processor removed bullet item ?reservation instructions for implementing read-modify-write constructs and removed ?low cost? from the 1st bullet. in section 2.4.2, crossbar switch (xbar)) , changed ?two master ports? to ?three master ports.? added bullet item for edma. removed bullet item for reservation instructions. chapter 6, clock description added block for cgm_ac0_sc with inputs firc and fxosc to figure 6-6 (fmpll block diagram) added note: to section 6.8.4.1, cryst al clock monitor : note: functional fxosc monitoring can only be guaranteed when the fxosc frequency is greater than (firc / 2 rcdiv )+0.5mhz. added note: to section 6.8.4.2, fmpll clock monitor : note: functional fmpll monitoring can only be guaranteed when the fmpll frequency is greater than (firc / 4) + 0.5 mhz. in section 6.7.7, recommendations , changed this bullet item: ? use progressive clock switchi ng if system clock changes are re quired while t he pll is being used as the system clock source. mod_period , inc_step, spread_sel bits should be modified before activating the fm mode. then strobe has to be generated to enable the new settings. if strb_byp is set to 1 then mo d_period, inc_step, and spread_sel can be modified only when fmpll is in powerdown mode. ? use progressive clock switching (fmpll output clock can be changed when it is the system clock, but only when using pr ogressive clock switching). with ? use pll progressive clock swit ching to ramp system clock (/8, /4, /2, /1) automatically for the case when pll is ena bled and selected as system clock. ? mod_period, inc_step, spread_sel bits should be modified before activating the fm mode. then strobe has to be generated to enable the new settings. if strb_byp is set to 1 then mod_period, inc_step, and spread_sel can be modified only when fmpll is in powerdown mode. chapter 8, mode entry module (mc_me) reformatted figure 8-1 (mc_me block diagram) .
appendix a revision history 956 freescale semiconductor chapter 9, reset generation module (mc_rgm) replaced section 9.4.6, boot mode capturing with the following: the mc_rgm samples pa[9:8] whenever reset is asserted until five firc (16 mhz internal rc oscillator) clock cycles before its deassertion edge. the result of the sampling is used at the beginning of reset phase3 for boot mode selection and is retained after reset has been deasserted for subsequent boots after reset sequences during which reset is not asserted. note: in order to ensure that the boot mode is correctly captured, the application needs to apply the valid boot mode value the entire time that reset is asserted. reset can be asserted as a consequence of th e internal reset generat ion. this will force re-sampling of the boot mode pins. (see ta b l e 9 - 1 1 for details.) chapter 11, voltage regulators and power supplies changed block in figure 11-2 (power domain organization) from 64k ram (pd2/pd3 to 48 kb ram (pd2). chapter 12, wakeup unit (wkpu) removed column for 208 pkg from ta bl e 1 2 - 1 ; removed bullet point for 208 pkg from section 12.5.2, non-maskable interrupts . chapter 13, real time clock / autonomous periodic interrupt (rtc/api) in table 13-3 (rtcc field descriptions) , added note to rtcc[apival] field description: note: api functionality starts only when apival is nonzero. the first api interrupt takes two more cycles because of synchronization of apival to the rtc clock, and apival + 1 cycles for subsequent occurrences. after that, interrupts are periodic in nature. the minimum supported value of apival is 4. chapter 16, enhanced direct memory access (edma) replaced entire section 16.5.8, dynamic programming . chapter 19, crossbar switch (xbar) updated figure 19-1 (xbar block diagram) to show edma as master. in table 19-1 (xbar switch ports for MPC5606BK) : ? added row for edma ? swapped logical number and physical master id in section 19.4, features , added bullet item for edma. added row for edma to table 19-2 (hardwired bus master priorities) , changed title of column for master id to ?master #,? corrected master id for ?e200z0 core?cpu data? from 0 to 1. throughout the chapter, corrected ?two master ports? to ?three master ports?. chapter 21, memory protection unit (mpu) in section 21.5.2.1, mpu control/error status register (mpu_cesr) , moved sperr bitfield to bits 0:2, changed field tag to sperr[0:2]. moved mpu_edr n [eacd] bits from 8:15 to 0:7 ( figure 21-4 ). chapter 23, lin controller (linflex) added section 23.8.2.1.7, overrun in section 23.7.1.8, li n output compare register (linocr) , in figure 23-13., lin output compare register (linocr) , changed the footnote to ?if lintcsr[lt om] = 0, these fields are read-only.? changed the first sentence of section 23.8.3.1, lin timeout mode to ?clearing the ltom bit (setting its value to 0) in the lintcsr enables the lin timeout mode.? changed the first sentence of section 23.8.3.2, output compare mode to ?setting lintcsr[ltom] = 1 enables the output compare mode.? table a-1. changes between revisions 1 and 2 (continued) chapter description
appendix a revision history freescale semiconductor 957 chapter 24, lin controller (linflexd) added section 24.7.1.5, overrun . in section 24.7.3.2, identifier filter submode configuration , changed the second sentence to ?to configure an identifier filter, the filter must fi rst be activated by setting the corresponding bit in the ifer[fact] field.? in section 24.10.8, lin output compare register (linocr) , in figure 24-25 (lin output compare register (linocr)) , changed the footnote to ?if lintcsr[lt om] = 0, these fields are read-only.? changed the first sentence of section 24.12.1.1, lin timeout mode to ?clearing the ltom bit (setting its value to 0) in the lintcsr enables the lin timeout mode.? changed the first sentence of section 24.12.1.2, output compare mode to ?setting lintcsr[ltom] = 1 enables the output compare mode.? table a-1. changes between revisions 1 and 2 (continued) chapter description
appendix a revision history 958 freescale semiconductor chapter 25, flexcan removed references throughout the chapter to ?low-cost mcus.? removed note: at end of section 25.2.2, flexcan module features : note: the individual rx mask per message buffer feature may not be available in low cost mcus. please consult the specific m cu documentation to find out if this feature is supported. removed note: above ta b l e 2 5 - 2 : the individual rx mask per message buffer feature may not be available in low cost mcus. please consult the specific mcu documentation to find out if this feature is supported. if not supported, the address range 0x0880-0x097f is considered reserved space, independent of the value of the bcc bit. added this note in the rtr field description of table 25-4 (message buffer structure field description) : note: do not configure the last message buffer to be the rtr frame. in figure 25-5 (module configuration register (mcr)) , removed the wak_msk and wak_src fields. in table 25-8 (mcr field descriptions) , removed the wak_msk and wak_src fields. replaced the bcc bit description in table 25-8 (mcr field descriptions) . in table 25-10 (ctrl field descriptions) , removed the note from the clk_src field. in section 25.4.4.4, rx global mask (rxgmask) register , changed ?for mcus supporting individual masks per mb, setting the bcc bit in mcr causes the rxgmask register to have no effect on the module operation. for mcus not supporting individual masks per mb, this register is always effective.? to ?setting the bcc bit in mcr causes the rxgmask register to have no effect on the module operation.? in section 25.4.4.5, rx 14 mask (rx14mask) register , removed the phrase ?for mcus supporting individual masks per mb? from the first paragraph. in section 25.4.4.6, rx 15 mask (rx15mask) register , removed the phrase ?for mcus supporting individual masks per mb? from the first paragraph. removed note: in section 25.4.4.13, rx individual mask registers (rximr0?rximr63) : note: the individual rx mask per message buffer feature may not be available in low cost mcus. please consult the specific mcu documentation to find out if this feature is supported. if not supported, the rxgmask, rx14 mask, and rx15mask registers are available, regardless of the value of the bcc bit. updated the table title of table 25-22 (bosch can 2.0b standard compliant bit time segment settings) from ?can standard compliant bit time segment settings? to ?bosch can 2.0b standard compliant bit time segment settings.? removed note: at end of section 25.5.6, matching process : note: the individual rx mask per message buffer feature may not be available in low cost mcus. please consult the specific mcu documentation to find out if this feature is supported. if not supported, the rxgmask, rx14 mask, and rx15mask registers are available, regardless of the value of the bcc bit. changed the last sentence of section 25.5.1, overview to ?an mb programmed with 0000, 1000, (inactive), or 1001 (abort) will be temporarily deactivated (will not participate in the current arbitration or matching run) when the cpu writes to the c/s field of that mb (see section 25.5.7.2, message buffer deactivation ). in section 25.5.9.4, protocol timing , removed the note following figure 25-16 (can engine clocking scheme) : ?this clock selection feature may not be available in all mcus. a particular mcu may not have a pll, in which case it would have only the oscillator clock, or it may use only the pll clock feeding the flexcan module. in these cases, the clk_src bit in the ctrl register has no effect on the module operation.? table a-1. changes between revisions 1 and 2 (continued) chapter description
appendix a revision history freescale semiconductor 959 chapter 25, flexcan (cont.) in section 25.5.9.4, protocol timing , updated the note following table 25-22 (bosch can 2.0b standard compliant bit time segment settings) to read: ?other combinations of time segment 1 and time segment 2 can be valid. it is the user?s responsibility to ensure the bit time settings are in compliance with the can standard. for bit time calculations, use an ipt (information processing time) of 2, which is the va lue implemented in the flexcan module.? chapter 28, analog-to-digital converter (adc) throughout this chapter, corrected refere nces to register cwsel to cwselr. corrected offset for ceofcr1 in table 28-10 (12-bit adc_1 digital registers) to 0x0018; changed row for 0x0018 to ?reserved.? added note: under figure 28-15 (channel pending register 2 (ceocfr2)) , explaining that ceofcr1 was not implemented on adc_1. removed this paragraph in section 28.3.2, analog clock generator and conversion timings : the direct clock should basically be used only in low power mode when the device is using only the 16 mhz fast internal rc oscillator, but the conversion still requires a 16 mhz clock (an 8 mhz clock is not fast enough). in section 28.3.4.2, ctu in trigger mode , replaced sentence: ?if another ctu conversion is triggered before the end of the conversion, that request is discarded.? with: ?if another ctu conversion is triggered before the end of the current ctu triggered conversion, the new request is discarded.? in section 28.3.5.2, presampling channel enable signals , in table 28-7 (presampling voltage selection based on prevalx fields) , in the 01 row, changed the ?presampling voltage? field to: v1 = v dd_hv_adc0 or v dd_hv_adc1 . in table 28-10 (12-bit adc_1 digital registers) , added the following rows for these registers: ? 0x0028 cimr1 ? 0x0048 dmar1 ?0x0088 psr1 ?0x0098 ctr1 ?0x00a8 ncmr1 ?0x00b8 jcmr1 corrected surrounding rows to reflect these changes. made the following corrections to the adcstatus description field in table 28-12 (msr field descriptions) : the value of this parameter depends on adc status: 000 idle ? the adc is powered up but idle. 001 power-down ? the adc is powered down. 010 wait state ? the adc is waiting for an external multiplexer, this only occurs when the dsdr register is non-zero. 011 reserved 100 sample ? the adc is sampling the analog signal. 101 reserved 110 conversion ? the adc is converting the sampled signal. 111 reserved in section 28.4.2.2, main status register (msr) , added detailed explanations to the adcstatus field. corrected reset value of ctr n registers to 0x0203 section 28.4.7, conversion timing registers ctr[0..2] corrected cdr n registers from read/write to read-only ( figure 28-48 and figure 28-49 ). changed fields cwselr7[wsel_ch63] through cwselr7[wsel_ch60] to reserved ( figure 28-50 ). table a-1. changes between revisions 1 and 2 (continued) chapter description
appendix a revision history 960 freescale semiconductor chapter 28, analog-to-digital converter (adc) (contd..) reformatted table 28-14 . reformatted table 28-17 . reformatted table 28-24 . reformatted table 28-29 . reformatted table 28-31 . reformatted table 28-33 . reformatted table 28-35 . reformatted table 28-39 . reformatted table 28-41 . reformatted table 28-56 . ?in table 28-17 (cimr[0..2] register description) , added a row for adc_1 cimr1 bits ?enable bit for channel 32 to 39 (standard channels)? ? edited title for figure 28-18 (channel interrupt mask register 1 (cimr1) for adc_0) to specify usage with adc_0. ? added figure 28-19 (channel interrupt mask register 1 (cimr1) for adc_1) . ?in table 28-24 (dmar[0..2] register description) , added a row for adc_1 dmar1 bits ?enable bit for channel 32 to 39 (standard channels)? ? edited title for figure 28-27 (dma channel select register 1 (dmar1) for adc_0) to specify usage with adc_0. ? added figure 28-28 (dma channel select register 1 (dmar1) for adc_1) . ?in table 28-29 (psr[0..2] register description) , added a row for adc_1 psr1 bits ?enable bit for channel 32 to 39 (standard channels)? ? added figure 28-35 (presampling register 1 (psr1) for adc_1) . ? edited title for figure 28-27 (dma channel select register 1 (dmar1) for adc_0) to specify usage with adc_0. ?in table 28-31 (ctr[0..2] re gister description) , added a row for adc_1 ctr1 ?associated to internal standard channel 32 to 39? ?in table 28-33 (ncmr[0..2] register description) , added a row for adc_1 ncmr1 ?enable bit of normal sampling channel 32 to 39 (standard channels)? ? added figure 28-40 (normal conversion mask register 1 (ncmr1) for adc_1) . ?in table 28-35 (jcmr[0..2] register description) , added a row for adc_1 jcmr1 ?enable bit of normal sampling channel 32 to 39 (standard channels)? ? added figure 28-44 (injected conversion mask register 1 (jcmr1) for adc_1) . ? edited title for figure 28-43 (injected conversion ma sk register 1 (jcmr1) for adc_0) to specify usage with adc_0. added note: in section 28.3.11, auto-clock-off mode note: the auto-clock-off feature cannot operate when the digital interface runs at the same rate as the analog interface. this means that when mcr.adcclksel = 1, the analog clock will not shut down in idle mode. chapter 29, cross triggering unit (ctu) at the end of section 29.4.1, event configuration re gisters (ctu_evtcfgrx) (x = 0...63) , added the following note: the ctu tracks issued conversion requests to the adc. when the adc is being triggered by the ctu and there is a need to shut down the adc, the adc must be allowed to complete conversions before being shut down. this ensures that the ctu is notified of completion; if the adc is shut down while performing a ctu-trigge red conversion, the ctu is not notified and will not be able to trigger further conversions until the device is reset. table a-1. changes between revisions 1 and 2 (continued) chapter description
appendix a revision history freescale semiconductor 961 chapter 30, flash memory changed reserved area in table 30-8 from 0x001c ? 0x0038 to 0x001c ? 0x003b. in the third paragraph of section 30.4.2.1, cflash module sectorization , corrected ?bank 0 of the module is divided in 18 sectors ? to 14 sectors. updated field description of bkx_apc and bkx_rwsc fields of pfcrx registers (in section 30.7.2.2.1, platform flash configuration register 0 (pfcr0) and section 30.7.2.2.2, platform flash configuration register 1 (pfcr1) . updated section 30.8.6, access pipelining updated section 30.1, introduction . updated figure 30-1 (flash memory architecture) . updated figure 30-2 (cflash and dflash module structures) . chapter 33, software watchdog timer (swt) in figure 33-1 (swt control register (swt_cr)) corrected reset value from 0x4000_011b to 0x800_0011b. removed the following sentence from section 33.5.2.1, swt control register (swt_cr) default value for swt_cr_rst is 0x4000_011b, corresponding to map1 = 1 (only data bus access allowed), ria = 1 (reset on invalid swt access), slk = 1 (soft lock), csl = 1 (irc clock source for counter), frz = 1 (freeze on debug), wen = 1 (watchdog enable). in figure 33-2 (swt interrupt register (swt_ir)) updated the mapn field description to: master access protection for master n. allows specific master to update watchdog. map0 = cpu, map2=edma. the platform bus master assignments are device-specific. 0 access for the master is not enabled 1 access for the master is enabled in figure 33-2 (swt interrupt register (swt_ir)) ?swt interrupt register (swt_ir),? changed tif bit to ?w1c.? added swt service key register (swt_sk) information. updated section 33.6, functional description to describe additional service key functionality. chapter 34, error correction status module (ecsm) inserted the following in section 34.2, overview the aips is the interface between the advanced high performance bus (ahb) interface and on-chip ips peripherals. ips peripherals are modules that contain readable/writable control and status registers. the ahb mast er reads and writes these registers through the aips. the aips generates module enables, the module address, transfer attributes, byte enables, and write data. these elements then function as inputs to the ips peripherals. ? ips ? inter peripheral subsytem ? aips ? interface between the advanced high performance bus (ahb) interface and on-chip ips peripherals ? ahb ? advance high performance bus updated reset value of pct register to 0xe012 ( figure 34-1 (processor core type register (pct)) ) and reset value of iopmc register to 0x0803_e000 ( figure 34-3 (ips on-platform module configuration register (iopmc)) ). removed bullet ?configuration for additional sr am ws for system frequency above 64 + 4% mhz? from features list. removed mwcr register. appendix a, revision history added revision history appendix table a-1. changes between revisions 1 and 2 (continued) chapter description
how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provided solely to enable system and software implementers to use freescale semiconductor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. the power architecture and power.org word marks and the power and power.org logos and related marks are trademarks and service marks licensed by power.org. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2010?2014. all rights reserved. MPC5606BKrm rev. 2 05/2014

▲Up To Search▲

Price & Availability of MPC5606BK

	To Download MPC5606BK Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .